dma.h 4.3 KB

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  1. /*
  2. * 440SPe's DMA engines support header file
  3. *
  4. * 2006-2009 (C) DENX Software Engineering.
  5. *
  6. * Author: Yuri Tikhonov <yur@emcraft.com>
  7. *
  8. * This file is licensed under the term of the GNU General Public License
  9. * version 2. The program licensed "as is" without any warranty of any
  10. * kind, whether express or implied.
  11. */
  12. #ifndef _PPC440SPE_DMA_H
  13. #define _PPC440SPE_DMA_H
  14. #include <linux/types.h>
  15. /* Number of elements in the array with statical CDBs */
  16. #define MAX_STAT_DMA_CDBS 16
  17. /* Number of DMA engines available on the contoller */
  18. #define DMA_ENGINES_NUM 2
  19. /* Maximum h/w supported number of destinations */
  20. #define DMA_DEST_MAX_NUM 2
  21. /* FIFO's params */
  22. #define DMA0_FIFO_SIZE 0x1000
  23. #define DMA1_FIFO_SIZE 0x1000
  24. #define DMA_FIFO_ENABLE (1<<12)
  25. /* DMA Configuration Register. Data Transfer Engine PLB Priority: */
  26. #define DMA_CFG_DXEPR_LP (0<<26)
  27. #define DMA_CFG_DXEPR_HP (3<<26)
  28. #define DMA_CFG_DXEPR_HHP (2<<26)
  29. #define DMA_CFG_DXEPR_HHHP (1<<26)
  30. /* DMA Configuration Register. DMA FIFO Manager PLB Priority: */
  31. #define DMA_CFG_DFMPP_LP (0<<23)
  32. #define DMA_CFG_DFMPP_HP (3<<23)
  33. #define DMA_CFG_DFMPP_HHP (2<<23)
  34. #define DMA_CFG_DFMPP_HHHP (1<<23)
  35. /* DMA Configuration Register. Force 64-byte Alignment */
  36. #define DMA_CFG_FALGN (1 << 19)
  37. /*UIC0:*/
  38. #define D0CPF_INT (1<<12)
  39. #define D0CSF_INT (1<<11)
  40. #define D1CPF_INT (1<<10)
  41. #define D1CSF_INT (1<<9)
  42. /*UIC1:*/
  43. #define DMAE_INT (1<<9)
  44. /* I2O IOP Interrupt Mask Register */
  45. #define I2O_IOPIM_P0SNE (1<<3)
  46. #define I2O_IOPIM_P0EM (1<<5)
  47. #define I2O_IOPIM_P1SNE (1<<6)
  48. #define I2O_IOPIM_P1EM (1<<8)
  49. /* DMA CDB fields */
  50. #define DMA_CDB_MSK (0xF)
  51. #define DMA_CDB_64B_ADDR (1<<2)
  52. #define DMA_CDB_NO_INT (1<<3)
  53. #define DMA_CDB_STATUS_MSK (0x3)
  54. #define DMA_CDB_ADDR_MSK (0xFFFFFFF0)
  55. /* DMA CDB OpCodes */
  56. #define DMA_CDB_OPC_NO_OP (0x00)
  57. #define DMA_CDB_OPC_MV_SG1_SG2 (0x01)
  58. #define DMA_CDB_OPC_MULTICAST (0x05)
  59. #define DMA_CDB_OPC_DFILL128 (0x24)
  60. #define DMA_CDB_OPC_DCHECK128 (0x23)
  61. #define DMA_CUED_XOR_BASE (0x10000000)
  62. #define DMA_CUED_XOR_HB (0x00000008)
  63. #ifdef CONFIG_440SP
  64. #define DMA_CUED_MULT1_OFF 0
  65. #define DMA_CUED_MULT2_OFF 8
  66. #define DMA_CUED_MULT3_OFF 16
  67. #define DMA_CUED_REGION_OFF 24
  68. #define DMA_CUED_XOR_WIN_MSK (0xFC000000)
  69. #else
  70. #define DMA_CUED_MULT1_OFF 2
  71. #define DMA_CUED_MULT2_OFF 10
  72. #define DMA_CUED_MULT3_OFF 18
  73. #define DMA_CUED_REGION_OFF 26
  74. #define DMA_CUED_XOR_WIN_MSK (0xF0000000)
  75. #endif
  76. #define DMA_CUED_REGION_MSK 0x3
  77. #define DMA_RXOR123 0x0
  78. #define DMA_RXOR124 0x1
  79. #define DMA_RXOR125 0x2
  80. #define DMA_RXOR12 0x3
  81. /* S/G addresses */
  82. #define DMA_CDB_SG_SRC 1
  83. #define DMA_CDB_SG_DST1 2
  84. #define DMA_CDB_SG_DST2 3
  85. /*
  86. * DMAx engines Command Descriptor Block Type
  87. */
  88. struct dma_cdb {
  89. /*
  90. * Basic CDB structure (Table 20-17, p.499, 440spe_um_1_22.pdf)
  91. */
  92. u8 pad0[2]; /* reserved */
  93. u8 attr; /* attributes */
  94. u8 opc; /* opcode */
  95. u32 sg1u; /* upper SG1 address */
  96. u32 sg1l; /* lower SG1 address */
  97. u32 cnt; /* SG count, 3B used */
  98. u32 sg2u; /* upper SG2 address */
  99. u32 sg2l; /* lower SG2 address */
  100. u32 sg3u; /* upper SG3 address */
  101. u32 sg3l; /* lower SG3 address */
  102. };
  103. /*
  104. * DMAx hardware registers (p.515 in 440SPe UM 1.22)
  105. */
  106. struct dma_regs {
  107. u32 cpfpl;
  108. u32 cpfph;
  109. u32 csfpl;
  110. u32 csfph;
  111. u32 dsts;
  112. u32 cfg;
  113. u8 pad0[0x8];
  114. u16 cpfhp;
  115. u16 cpftp;
  116. u16 csfhp;
  117. u16 csftp;
  118. u8 pad1[0x8];
  119. u32 acpl;
  120. u32 acph;
  121. u32 s1bpl;
  122. u32 s1bph;
  123. u32 s2bpl;
  124. u32 s2bph;
  125. u32 s3bpl;
  126. u32 s3bph;
  127. u8 pad2[0x10];
  128. u32 earl;
  129. u32 earh;
  130. u8 pad3[0x8];
  131. u32 seat;
  132. u32 sead;
  133. u32 op;
  134. u32 fsiz;
  135. };
  136. /*
  137. * I2O hardware registers (p.528 in 440SPe UM 1.22)
  138. */
  139. struct i2o_regs {
  140. u32 ists;
  141. u32 iseat;
  142. u32 isead;
  143. u8 pad0[0x14];
  144. u32 idbel;
  145. u8 pad1[0xc];
  146. u32 ihis;
  147. u32 ihim;
  148. u8 pad2[0x8];
  149. u32 ihiq;
  150. u32 ihoq;
  151. u8 pad3[0x8];
  152. u32 iopis;
  153. u32 iopim;
  154. u32 iopiq;
  155. u8 iopoq;
  156. u8 pad4[3];
  157. u16 iiflh;
  158. u16 iiflt;
  159. u16 iiplh;
  160. u16 iiplt;
  161. u16 ioflh;
  162. u16 ioflt;
  163. u16 ioplh;
  164. u16 ioplt;
  165. u32 iidc;
  166. u32 ictl;
  167. u32 ifcpp;
  168. u8 pad5[0x4];
  169. u16 mfac0;
  170. u16 mfac1;
  171. u16 mfac2;
  172. u16 mfac3;
  173. u16 mfac4;
  174. u16 mfac5;
  175. u16 mfac6;
  176. u16 mfac7;
  177. u16 ifcfh;
  178. u16 ifcht;
  179. u8 pad6[0x4];
  180. u32 iifmc;
  181. u32 iodb;
  182. u32 iodbc;
  183. u32 ifbal;
  184. u32 ifbah;
  185. u32 ifsiz;
  186. u32 ispd0;
  187. u32 ispd1;
  188. u32 ispd2;
  189. u32 ispd3;
  190. u32 ihipl;
  191. u32 ihiph;
  192. u32 ihopl;
  193. u32 ihoph;
  194. u32 iiipl;
  195. u32 iiiph;
  196. u32 iiopl;
  197. u32 iioph;
  198. u32 ifcpl;
  199. u32 ifcph;
  200. u8 pad7[0x8];
  201. u32 iopt;
  202. };
  203. #endif /* _PPC440SPE_DMA_H */