adma.h 6.1 KB

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  1. /*
  2. * 2006-2009 (C) DENX Software Engineering.
  3. *
  4. * Author: Yuri Tikhonov <yur@emcraft.com>
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of
  8. * any kind, whether express or implied.
  9. */
  10. #ifndef _PPC440SPE_ADMA_H
  11. #define _PPC440SPE_ADMA_H
  12. #include <linux/types.h>
  13. #include "dma.h"
  14. #include "xor.h"
  15. #define to_ppc440spe_adma_chan(chan) \
  16. container_of(chan, struct ppc440spe_adma_chan, common)
  17. #define to_ppc440spe_adma_device(dev) \
  18. container_of(dev, struct ppc440spe_adma_device, common)
  19. #define tx_to_ppc440spe_adma_slot(tx) \
  20. container_of(tx, struct ppc440spe_adma_desc_slot, async_tx)
  21. /* Default polynomial (for 440SP is only available) */
  22. #define PPC440SPE_DEFAULT_POLY 0x4d
  23. #define PPC440SPE_ADMA_ENGINES_NUM (XOR_ENGINES_NUM + DMA_ENGINES_NUM)
  24. #define PPC440SPE_ADMA_WATCHDOG_MSEC 3
  25. #define PPC440SPE_ADMA_THRESHOLD 1
  26. #define PPC440SPE_DMA0_ID 0
  27. #define PPC440SPE_DMA1_ID 1
  28. #define PPC440SPE_XOR_ID 2
  29. #define PPC440SPE_ADMA_DMA_MAX_BYTE_COUNT 0xFFFFFFUL
  30. /* this is the XOR_CBBCR width */
  31. #define PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT (1 << 31)
  32. #define PPC440SPE_ADMA_ZERO_SUM_MAX_BYTE_COUNT PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT
  33. #define PPC440SPE_RXOR_RUN 0
  34. #define MQ0_CF2H_RXOR_BS_MASK 0x1FF
  35. #undef ADMA_LL_DEBUG
  36. /**
  37. * struct ppc440spe_adma_device - internal representation of an ADMA device
  38. * @dev: device
  39. * @dma_reg: base for DMAx register access
  40. * @xor_reg: base for XOR register access
  41. * @i2o_reg: base for I2O register access
  42. * @id: HW ADMA Device selector
  43. * @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
  44. * @dma_desc_pool: base of DMA descriptor region (DMA address)
  45. * @pool_size: size of the pool
  46. * @irq: DMAx or XOR irq number
  47. * @err_irq: DMAx error irq number
  48. * @common: embedded struct dma_device
  49. */
  50. struct ppc440spe_adma_device {
  51. struct device *dev;
  52. struct dma_regs __iomem *dma_reg;
  53. struct xor_regs __iomem *xor_reg;
  54. struct i2o_regs __iomem *i2o_reg;
  55. int id;
  56. void *dma_desc_pool_virt;
  57. dma_addr_t dma_desc_pool;
  58. size_t pool_size;
  59. int irq;
  60. int err_irq;
  61. struct dma_device common;
  62. };
  63. /**
  64. * struct ppc440spe_adma_chan - internal representation of an ADMA channel
  65. * @lock: serializes enqueue/dequeue operations to the slot pool
  66. * @device: parent device
  67. * @chain: device chain view of the descriptors
  68. * @common: common dmaengine channel object members
  69. * @all_slots: complete domain of slots usable by the channel
  70. * @pending: allows batching of hardware operations
  71. * @slots_allocated: records the actual size of the descriptor slot pool
  72. * @hw_chain_inited: h/w descriptor chain initialization flag
  73. * @irq_tasklet: bottom half where ppc440spe_adma_slot_cleanup runs
  74. * @needs_unmap: if buffers should not be unmapped upon final processing
  75. * @pdest_page: P destination page for async validate operation
  76. * @qdest_page: Q destination page for async validate operation
  77. * @pdest: P dma addr for async validate operation
  78. * @qdest: Q dma addr for async validate operation
  79. */
  80. struct ppc440spe_adma_chan {
  81. spinlock_t lock;
  82. struct ppc440spe_adma_device *device;
  83. struct list_head chain;
  84. struct dma_chan common;
  85. struct list_head all_slots;
  86. struct ppc440spe_adma_desc_slot *last_used;
  87. int pending;
  88. int slots_allocated;
  89. int hw_chain_inited;
  90. struct tasklet_struct irq_tasklet;
  91. u8 needs_unmap;
  92. struct page *pdest_page;
  93. struct page *qdest_page;
  94. dma_addr_t pdest;
  95. dma_addr_t qdest;
  96. };
  97. struct ppc440spe_rxor {
  98. u32 addrl;
  99. u32 addrh;
  100. int len;
  101. int xor_count;
  102. int addr_count;
  103. int desc_count;
  104. int state;
  105. };
  106. /**
  107. * struct ppc440spe_adma_desc_slot - PPC440SPE-ADMA software descriptor
  108. * @phys: hardware address of the hardware descriptor chain
  109. * @group_head: first operation in a transaction
  110. * @hw_next: pointer to the next descriptor in chain
  111. * @async_tx: support for the async_tx api
  112. * @slot_node: node on the iop_adma_chan.all_slots list
  113. * @chain_node: node on the op_adma_chan.chain list
  114. * @group_list: list of slots that make up a multi-descriptor transaction
  115. * for example transfer lengths larger than the supported hw max
  116. * @unmap_len: transaction bytecount
  117. * @hw_desc: virtual address of the hardware descriptor chain
  118. * @stride: currently chained or not
  119. * @idx: pool index
  120. * @slot_cnt: total slots used in an transaction (group of operations)
  121. * @src_cnt: number of sources set in this descriptor
  122. * @dst_cnt: number of destinations set in the descriptor
  123. * @slots_per_op: number of slots per operation
  124. * @descs_per_op: number of slot per P/Q operation see comment
  125. * for ppc440spe_prep_dma_pqxor function
  126. * @flags: desc state/type
  127. * @reverse_flags: 1 if a corresponding rxor address uses reversed address order
  128. * @xor_check_result: result of zero sum
  129. * @crc32_result: result crc calculation
  130. */
  131. struct ppc440spe_adma_desc_slot {
  132. dma_addr_t phys;
  133. struct ppc440spe_adma_desc_slot *group_head;
  134. struct ppc440spe_adma_desc_slot *hw_next;
  135. struct dma_async_tx_descriptor async_tx;
  136. struct list_head slot_node;
  137. struct list_head chain_node; /* node in channel ops list */
  138. struct list_head group_list; /* list */
  139. unsigned int unmap_len;
  140. void *hw_desc;
  141. u16 stride;
  142. u16 idx;
  143. u16 slot_cnt;
  144. u8 src_cnt;
  145. u8 dst_cnt;
  146. u8 slots_per_op;
  147. u8 descs_per_op;
  148. unsigned long flags;
  149. unsigned long reverse_flags[8];
  150. #define PPC440SPE_DESC_INT 0 /* generate interrupt on complete */
  151. #define PPC440SPE_ZERO_P 1 /* clear P destionaion */
  152. #define PPC440SPE_ZERO_Q 2 /* clear Q destination */
  153. #define PPC440SPE_COHERENT 3 /* src/dst are coherent */
  154. #define PPC440SPE_DESC_WXOR 4 /* WXORs are in chain */
  155. #define PPC440SPE_DESC_RXOR 5 /* RXOR is in chain */
  156. #define PPC440SPE_DESC_RXOR123 8 /* CDB for RXOR123 operation */
  157. #define PPC440SPE_DESC_RXOR124 9 /* CDB for RXOR124 operation */
  158. #define PPC440SPE_DESC_RXOR125 10 /* CDB for RXOR125 operation */
  159. #define PPC440SPE_DESC_RXOR12 11 /* CDB for RXOR12 operation */
  160. #define PPC440SPE_DESC_RXOR_REV 12 /* CDB has srcs in reversed order */
  161. #define PPC440SPE_DESC_PCHECK 13
  162. #define PPC440SPE_DESC_QCHECK 14
  163. #define PPC440SPE_DESC_RXOR_MSK 0x3
  164. struct ppc440spe_rxor rxor_cursor;
  165. union {
  166. u32 *xor_check_result;
  167. u32 *crc32_result;
  168. };
  169. };
  170. #endif /* _PPC440SPE_ADMA_H */