hw.h 6.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
  4. */
  5. #ifndef _IOAT_HW_H_
  6. #define _IOAT_HW_H_
  7. /* PCI Configuration Space Values */
  8. #define IOAT_MMIO_BAR 0
  9. /* CB device ID's */
  10. #define PCI_DEVICE_ID_INTEL_IOAT_IVB0 0x0e20
  11. #define PCI_DEVICE_ID_INTEL_IOAT_IVB1 0x0e21
  12. #define PCI_DEVICE_ID_INTEL_IOAT_IVB2 0x0e22
  13. #define PCI_DEVICE_ID_INTEL_IOAT_IVB3 0x0e23
  14. #define PCI_DEVICE_ID_INTEL_IOAT_IVB4 0x0e24
  15. #define PCI_DEVICE_ID_INTEL_IOAT_IVB5 0x0e25
  16. #define PCI_DEVICE_ID_INTEL_IOAT_IVB6 0x0e26
  17. #define PCI_DEVICE_ID_INTEL_IOAT_IVB7 0x0e27
  18. #define PCI_DEVICE_ID_INTEL_IOAT_IVB8 0x0e2e
  19. #define PCI_DEVICE_ID_INTEL_IOAT_IVB9 0x0e2f
  20. #define PCI_DEVICE_ID_INTEL_IOAT_HSW0 0x2f20
  21. #define PCI_DEVICE_ID_INTEL_IOAT_HSW1 0x2f21
  22. #define PCI_DEVICE_ID_INTEL_IOAT_HSW2 0x2f22
  23. #define PCI_DEVICE_ID_INTEL_IOAT_HSW3 0x2f23
  24. #define PCI_DEVICE_ID_INTEL_IOAT_HSW4 0x2f24
  25. #define PCI_DEVICE_ID_INTEL_IOAT_HSW5 0x2f25
  26. #define PCI_DEVICE_ID_INTEL_IOAT_HSW6 0x2f26
  27. #define PCI_DEVICE_ID_INTEL_IOAT_HSW7 0x2f27
  28. #define PCI_DEVICE_ID_INTEL_IOAT_HSW8 0x2f2e
  29. #define PCI_DEVICE_ID_INTEL_IOAT_HSW9 0x2f2f
  30. #define PCI_DEVICE_ID_INTEL_IOAT_BWD0 0x0C50
  31. #define PCI_DEVICE_ID_INTEL_IOAT_BWD1 0x0C51
  32. #define PCI_DEVICE_ID_INTEL_IOAT_BWD2 0x0C52
  33. #define PCI_DEVICE_ID_INTEL_IOAT_BWD3 0x0C53
  34. #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0 0x6f50
  35. #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1 0x6f51
  36. #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2 0x6f52
  37. #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3 0x6f53
  38. #define PCI_DEVICE_ID_INTEL_IOAT_BDX0 0x6f20
  39. #define PCI_DEVICE_ID_INTEL_IOAT_BDX1 0x6f21
  40. #define PCI_DEVICE_ID_INTEL_IOAT_BDX2 0x6f22
  41. #define PCI_DEVICE_ID_INTEL_IOAT_BDX3 0x6f23
  42. #define PCI_DEVICE_ID_INTEL_IOAT_BDX4 0x6f24
  43. #define PCI_DEVICE_ID_INTEL_IOAT_BDX5 0x6f25
  44. #define PCI_DEVICE_ID_INTEL_IOAT_BDX6 0x6f26
  45. #define PCI_DEVICE_ID_INTEL_IOAT_BDX7 0x6f27
  46. #define PCI_DEVICE_ID_INTEL_IOAT_BDX8 0x6f2e
  47. #define PCI_DEVICE_ID_INTEL_IOAT_BDX9 0x6f2f
  48. #define PCI_DEVICE_ID_INTEL_IOAT_SKX 0x2021
  49. #define PCI_DEVICE_ID_INTEL_IOAT_ICX 0x0b00
  50. #define IOAT_VER_1_2 0x12 /* Version 1.2 */
  51. #define IOAT_VER_2_0 0x20 /* Version 2.0 */
  52. #define IOAT_VER_3_0 0x30 /* Version 3.0 */
  53. #define IOAT_VER_3_2 0x32 /* Version 3.2 */
  54. #define IOAT_VER_3_3 0x33 /* Version 3.3 */
  55. #define IOAT_VER_3_4 0x34 /* Version 3.4 */
  56. int system_has_dca_enabled(struct pci_dev *pdev);
  57. #define IOAT_DESC_SZ 64
  58. struct ioat_dma_descriptor {
  59. uint32_t size;
  60. union {
  61. uint32_t ctl;
  62. struct {
  63. unsigned int int_en:1;
  64. unsigned int src_snoop_dis:1;
  65. unsigned int dest_snoop_dis:1;
  66. unsigned int compl_write:1;
  67. unsigned int fence:1;
  68. unsigned int null:1;
  69. unsigned int src_brk:1;
  70. unsigned int dest_brk:1;
  71. unsigned int bundle:1;
  72. unsigned int dest_dca:1;
  73. unsigned int hint:1;
  74. unsigned int rsvd2:13;
  75. #define IOAT_OP_COPY 0x00
  76. unsigned int op:8;
  77. } ctl_f;
  78. };
  79. uint64_t src_addr;
  80. uint64_t dst_addr;
  81. uint64_t next;
  82. uint64_t rsv1;
  83. uint64_t rsv2;
  84. /* store some driver data in an unused portion of the descriptor */
  85. union {
  86. uint64_t user1;
  87. uint64_t tx_cnt;
  88. };
  89. uint64_t user2;
  90. };
  91. struct ioat_xor_descriptor {
  92. uint32_t size;
  93. union {
  94. uint32_t ctl;
  95. struct {
  96. unsigned int int_en:1;
  97. unsigned int src_snoop_dis:1;
  98. unsigned int dest_snoop_dis:1;
  99. unsigned int compl_write:1;
  100. unsigned int fence:1;
  101. unsigned int src_cnt:3;
  102. unsigned int bundle:1;
  103. unsigned int dest_dca:1;
  104. unsigned int hint:1;
  105. unsigned int rsvd:13;
  106. #define IOAT_OP_XOR 0x87
  107. #define IOAT_OP_XOR_VAL 0x88
  108. unsigned int op:8;
  109. } ctl_f;
  110. };
  111. uint64_t src_addr;
  112. uint64_t dst_addr;
  113. uint64_t next;
  114. uint64_t src_addr2;
  115. uint64_t src_addr3;
  116. uint64_t src_addr4;
  117. uint64_t src_addr5;
  118. };
  119. struct ioat_xor_ext_descriptor {
  120. uint64_t src_addr6;
  121. uint64_t src_addr7;
  122. uint64_t src_addr8;
  123. uint64_t next;
  124. uint64_t rsvd[4];
  125. };
  126. struct ioat_pq_descriptor {
  127. union {
  128. uint32_t size;
  129. uint32_t dwbes;
  130. struct {
  131. unsigned int rsvd:25;
  132. unsigned int p_val_err:1;
  133. unsigned int q_val_err:1;
  134. unsigned int rsvd1:4;
  135. unsigned int wbes:1;
  136. } dwbes_f;
  137. };
  138. union {
  139. uint32_t ctl;
  140. struct {
  141. unsigned int int_en:1;
  142. unsigned int src_snoop_dis:1;
  143. unsigned int dest_snoop_dis:1;
  144. unsigned int compl_write:1;
  145. unsigned int fence:1;
  146. unsigned int src_cnt:3;
  147. unsigned int bundle:1;
  148. unsigned int dest_dca:1;
  149. unsigned int hint:1;
  150. unsigned int p_disable:1;
  151. unsigned int q_disable:1;
  152. unsigned int rsvd2:2;
  153. unsigned int wb_en:1;
  154. unsigned int prl_en:1;
  155. unsigned int rsvd3:7;
  156. #define IOAT_OP_PQ 0x89
  157. #define IOAT_OP_PQ_VAL 0x8a
  158. #define IOAT_OP_PQ_16S 0xa0
  159. #define IOAT_OP_PQ_VAL_16S 0xa1
  160. unsigned int op:8;
  161. } ctl_f;
  162. };
  163. uint64_t src_addr;
  164. uint64_t p_addr;
  165. uint64_t next;
  166. uint64_t src_addr2;
  167. union {
  168. uint64_t src_addr3;
  169. uint64_t sed_addr;
  170. };
  171. uint8_t coef[8];
  172. uint64_t q_addr;
  173. };
  174. struct ioat_pq_ext_descriptor {
  175. uint64_t src_addr4;
  176. uint64_t src_addr5;
  177. uint64_t src_addr6;
  178. uint64_t next;
  179. uint64_t src_addr7;
  180. uint64_t src_addr8;
  181. uint64_t rsvd[2];
  182. };
  183. struct ioat_pq_update_descriptor {
  184. uint32_t size;
  185. union {
  186. uint32_t ctl;
  187. struct {
  188. unsigned int int_en:1;
  189. unsigned int src_snoop_dis:1;
  190. unsigned int dest_snoop_dis:1;
  191. unsigned int compl_write:1;
  192. unsigned int fence:1;
  193. unsigned int src_cnt:3;
  194. unsigned int bundle:1;
  195. unsigned int dest_dca:1;
  196. unsigned int hint:1;
  197. unsigned int p_disable:1;
  198. unsigned int q_disable:1;
  199. unsigned int rsvd:3;
  200. unsigned int coef:8;
  201. #define IOAT_OP_PQ_UP 0x8b
  202. unsigned int op:8;
  203. } ctl_f;
  204. };
  205. uint64_t src_addr;
  206. uint64_t p_addr;
  207. uint64_t next;
  208. uint64_t src_addr2;
  209. uint64_t p_src;
  210. uint64_t q_src;
  211. uint64_t q_addr;
  212. };
  213. struct ioat_raw_descriptor {
  214. uint64_t field[8];
  215. };
  216. struct ioat_pq16a_descriptor {
  217. uint8_t coef[8];
  218. uint64_t src_addr3;
  219. uint64_t src_addr4;
  220. uint64_t src_addr5;
  221. uint64_t src_addr6;
  222. uint64_t src_addr7;
  223. uint64_t src_addr8;
  224. uint64_t src_addr9;
  225. };
  226. struct ioat_pq16b_descriptor {
  227. uint64_t src_addr10;
  228. uint64_t src_addr11;
  229. uint64_t src_addr12;
  230. uint64_t src_addr13;
  231. uint64_t src_addr14;
  232. uint64_t src_addr15;
  233. uint64_t src_addr16;
  234. uint64_t rsvd;
  235. };
  236. union ioat_sed_pq_descriptor {
  237. struct ioat_pq16a_descriptor a;
  238. struct ioat_pq16b_descriptor b;
  239. };
  240. #define SED_SIZE 64
  241. struct ioat_sed_raw_descriptor {
  242. uint64_t a[8];
  243. uint64_t b[8];
  244. uint64_t c[8];
  245. };
  246. #endif