idma64.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Core driver for the Intel integrated DMA 64-bit
  4. *
  5. * Copyright (C) 2015 Intel Corporation
  6. * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/delay.h>
  10. #include <linux/dmaengine.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/dmapool.h>
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. #include <linux/dma/idma64.h>
  18. #include "idma64.h"
  19. /* For now we support only two channels */
  20. #define IDMA64_NR_CHAN 2
  21. /* ---------------------------------------------------------------------- */
  22. static struct device *chan2dev(struct dma_chan *chan)
  23. {
  24. return &chan->dev->device;
  25. }
  26. /* ---------------------------------------------------------------------- */
  27. static void idma64_off(struct idma64 *idma64)
  28. {
  29. unsigned short count = 100;
  30. dma_writel(idma64, CFG, 0);
  31. channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
  32. channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask);
  33. channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask);
  34. channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask);
  35. channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
  36. do {
  37. cpu_relax();
  38. } while (dma_readl(idma64, CFG) & IDMA64_CFG_DMA_EN && --count);
  39. }
  40. static void idma64_on(struct idma64 *idma64)
  41. {
  42. dma_writel(idma64, CFG, IDMA64_CFG_DMA_EN);
  43. }
  44. /* ---------------------------------------------------------------------- */
  45. static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c)
  46. {
  47. u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
  48. u32 cfglo = 0;
  49. /* Set default burst alignment */
  50. cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN;
  51. channel_writel(idma64c, CFG_LO, cfglo);
  52. channel_writel(idma64c, CFG_HI, cfghi);
  53. /* Enable interrupts */
  54. channel_set_bit(idma64, MASK(XFER), idma64c->mask);
  55. channel_set_bit(idma64, MASK(ERROR), idma64c->mask);
  56. /*
  57. * Enforce the controller to be turned on.
  58. *
  59. * The iDMA is turned off in ->probe() and looses context during system
  60. * suspend / resume cycle. That's why we have to enable it each time we
  61. * use it.
  62. */
  63. idma64_on(idma64);
  64. }
  65. static void idma64_chan_stop(struct idma64 *idma64, struct idma64_chan *idma64c)
  66. {
  67. channel_clear_bit(idma64, CH_EN, idma64c->mask);
  68. }
  69. static void idma64_chan_start(struct idma64 *idma64, struct idma64_chan *idma64c)
  70. {
  71. struct idma64_desc *desc = idma64c->desc;
  72. struct idma64_hw_desc *hw = &desc->hw[0];
  73. channel_writeq(idma64c, SAR, 0);
  74. channel_writeq(idma64c, DAR, 0);
  75. channel_writel(idma64c, CTL_HI, IDMA64C_CTLH_BLOCK_TS(~0UL));
  76. channel_writel(idma64c, CTL_LO, IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
  77. channel_writeq(idma64c, LLP, hw->llp);
  78. channel_set_bit(idma64, CH_EN, idma64c->mask);
  79. }
  80. static void idma64_stop_transfer(struct idma64_chan *idma64c)
  81. {
  82. struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
  83. idma64_chan_stop(idma64, idma64c);
  84. }
  85. static void idma64_start_transfer(struct idma64_chan *idma64c)
  86. {
  87. struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
  88. struct virt_dma_desc *vdesc;
  89. /* Get the next descriptor */
  90. vdesc = vchan_next_desc(&idma64c->vchan);
  91. if (!vdesc) {
  92. idma64c->desc = NULL;
  93. return;
  94. }
  95. list_del(&vdesc->node);
  96. idma64c->desc = to_idma64_desc(vdesc);
  97. /* Configure the channel */
  98. idma64_chan_init(idma64, idma64c);
  99. /* Start the channel with a new descriptor */
  100. idma64_chan_start(idma64, idma64c);
  101. }
  102. /* ---------------------------------------------------------------------- */
  103. static void idma64_chan_irq(struct idma64 *idma64, unsigned short c,
  104. u32 status_err, u32 status_xfer)
  105. {
  106. struct idma64_chan *idma64c = &idma64->chan[c];
  107. struct idma64_desc *desc;
  108. spin_lock(&idma64c->vchan.lock);
  109. desc = idma64c->desc;
  110. if (desc) {
  111. if (status_err & (1 << c)) {
  112. dma_writel(idma64, CLEAR(ERROR), idma64c->mask);
  113. desc->status = DMA_ERROR;
  114. } else if (status_xfer & (1 << c)) {
  115. dma_writel(idma64, CLEAR(XFER), idma64c->mask);
  116. desc->status = DMA_COMPLETE;
  117. vchan_cookie_complete(&desc->vdesc);
  118. idma64_start_transfer(idma64c);
  119. }
  120. /* idma64_start_transfer() updates idma64c->desc */
  121. if (idma64c->desc == NULL || desc->status == DMA_ERROR)
  122. idma64_stop_transfer(idma64c);
  123. }
  124. spin_unlock(&idma64c->vchan.lock);
  125. }
  126. static irqreturn_t idma64_irq(int irq, void *dev)
  127. {
  128. struct idma64 *idma64 = dev;
  129. u32 status = dma_readl(idma64, STATUS_INT);
  130. u32 status_xfer;
  131. u32 status_err;
  132. unsigned short i;
  133. dev_vdbg(idma64->dma.dev, "%s: status=%#x\n", __func__, status);
  134. /* Check if we have any interrupt from the DMA controller */
  135. if (!status)
  136. return IRQ_NONE;
  137. status_xfer = dma_readl(idma64, RAW(XFER));
  138. status_err = dma_readl(idma64, RAW(ERROR));
  139. for (i = 0; i < idma64->dma.chancnt; i++)
  140. idma64_chan_irq(idma64, i, status_err, status_xfer);
  141. return IRQ_HANDLED;
  142. }
  143. /* ---------------------------------------------------------------------- */
  144. static struct idma64_desc *idma64_alloc_desc(unsigned int ndesc)
  145. {
  146. struct idma64_desc *desc;
  147. desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
  148. if (!desc)
  149. return NULL;
  150. desc->hw = kcalloc(ndesc, sizeof(*desc->hw), GFP_NOWAIT);
  151. if (!desc->hw) {
  152. kfree(desc);
  153. return NULL;
  154. }
  155. return desc;
  156. }
  157. static void idma64_desc_free(struct idma64_chan *idma64c,
  158. struct idma64_desc *desc)
  159. {
  160. struct idma64_hw_desc *hw;
  161. if (desc->ndesc) {
  162. unsigned int i = desc->ndesc;
  163. do {
  164. hw = &desc->hw[--i];
  165. dma_pool_free(idma64c->pool, hw->lli, hw->llp);
  166. } while (i);
  167. }
  168. kfree(desc->hw);
  169. kfree(desc);
  170. }
  171. static void idma64_vdesc_free(struct virt_dma_desc *vdesc)
  172. {
  173. struct idma64_chan *idma64c = to_idma64_chan(vdesc->tx.chan);
  174. idma64_desc_free(idma64c, to_idma64_desc(vdesc));
  175. }
  176. static void idma64_hw_desc_fill(struct idma64_hw_desc *hw,
  177. struct dma_slave_config *config,
  178. enum dma_transfer_direction direction, u64 llp)
  179. {
  180. struct idma64_lli *lli = hw->lli;
  181. u64 sar, dar;
  182. u32 ctlhi = IDMA64C_CTLH_BLOCK_TS(hw->len);
  183. u32 ctllo = IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN;
  184. u32 src_width, dst_width;
  185. if (direction == DMA_MEM_TO_DEV) {
  186. sar = hw->phys;
  187. dar = config->dst_addr;
  188. ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC |
  189. IDMA64C_CTLL_FC_M2P;
  190. src_width = __ffs(sar | hw->len | 4);
  191. dst_width = __ffs(config->dst_addr_width);
  192. } else { /* DMA_DEV_TO_MEM */
  193. sar = config->src_addr;
  194. dar = hw->phys;
  195. ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX |
  196. IDMA64C_CTLL_FC_P2M;
  197. src_width = __ffs(config->src_addr_width);
  198. dst_width = __ffs(dar | hw->len | 4);
  199. }
  200. lli->sar = sar;
  201. lli->dar = dar;
  202. lli->ctlhi = ctlhi;
  203. lli->ctllo = ctllo |
  204. IDMA64C_CTLL_SRC_MSIZE(config->src_maxburst) |
  205. IDMA64C_CTLL_DST_MSIZE(config->dst_maxburst) |
  206. IDMA64C_CTLL_DST_WIDTH(dst_width) |
  207. IDMA64C_CTLL_SRC_WIDTH(src_width);
  208. lli->llp = llp;
  209. }
  210. static void idma64_desc_fill(struct idma64_chan *idma64c,
  211. struct idma64_desc *desc)
  212. {
  213. struct dma_slave_config *config = &idma64c->config;
  214. unsigned int i = desc->ndesc;
  215. struct idma64_hw_desc *hw = &desc->hw[i - 1];
  216. struct idma64_lli *lli = hw->lli;
  217. u64 llp = 0;
  218. /* Fill the hardware descriptors and link them to a list */
  219. do {
  220. hw = &desc->hw[--i];
  221. idma64_hw_desc_fill(hw, config, desc->direction, llp);
  222. llp = hw->llp;
  223. desc->length += hw->len;
  224. } while (i);
  225. /* Trigger an interrupt after the last block is transfered */
  226. lli->ctllo |= IDMA64C_CTLL_INT_EN;
  227. /* Disable LLP transfer in the last block */
  228. lli->ctllo &= ~(IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
  229. }
  230. static struct dma_async_tx_descriptor *idma64_prep_slave_sg(
  231. struct dma_chan *chan, struct scatterlist *sgl,
  232. unsigned int sg_len, enum dma_transfer_direction direction,
  233. unsigned long flags, void *context)
  234. {
  235. struct idma64_chan *idma64c = to_idma64_chan(chan);
  236. struct idma64_desc *desc;
  237. struct scatterlist *sg;
  238. unsigned int i;
  239. desc = idma64_alloc_desc(sg_len);
  240. if (!desc)
  241. return NULL;
  242. for_each_sg(sgl, sg, sg_len, i) {
  243. struct idma64_hw_desc *hw = &desc->hw[i];
  244. /* Allocate DMA capable memory for hardware descriptor */
  245. hw->lli = dma_pool_alloc(idma64c->pool, GFP_NOWAIT, &hw->llp);
  246. if (!hw->lli) {
  247. desc->ndesc = i;
  248. idma64_desc_free(idma64c, desc);
  249. return NULL;
  250. }
  251. hw->phys = sg_dma_address(sg);
  252. hw->len = sg_dma_len(sg);
  253. }
  254. desc->ndesc = sg_len;
  255. desc->direction = direction;
  256. desc->status = DMA_IN_PROGRESS;
  257. idma64_desc_fill(idma64c, desc);
  258. return vchan_tx_prep(&idma64c->vchan, &desc->vdesc, flags);
  259. }
  260. static void idma64_issue_pending(struct dma_chan *chan)
  261. {
  262. struct idma64_chan *idma64c = to_idma64_chan(chan);
  263. unsigned long flags;
  264. spin_lock_irqsave(&idma64c->vchan.lock, flags);
  265. if (vchan_issue_pending(&idma64c->vchan) && !idma64c->desc)
  266. idma64_start_transfer(idma64c);
  267. spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
  268. }
  269. static size_t idma64_active_desc_size(struct idma64_chan *idma64c)
  270. {
  271. struct idma64_desc *desc = idma64c->desc;
  272. struct idma64_hw_desc *hw;
  273. size_t bytes = desc->length;
  274. u64 llp = channel_readq(idma64c, LLP);
  275. u32 ctlhi = channel_readl(idma64c, CTL_HI);
  276. unsigned int i = 0;
  277. do {
  278. hw = &desc->hw[i];
  279. if (hw->llp == llp)
  280. break;
  281. bytes -= hw->len;
  282. } while (++i < desc->ndesc);
  283. if (!i)
  284. return bytes;
  285. /* The current chunk is not fully transfered yet */
  286. bytes += desc->hw[--i].len;
  287. return bytes - IDMA64C_CTLH_BLOCK_TS(ctlhi);
  288. }
  289. static enum dma_status idma64_tx_status(struct dma_chan *chan,
  290. dma_cookie_t cookie, struct dma_tx_state *state)
  291. {
  292. struct idma64_chan *idma64c = to_idma64_chan(chan);
  293. struct virt_dma_desc *vdesc;
  294. enum dma_status status;
  295. size_t bytes;
  296. unsigned long flags;
  297. status = dma_cookie_status(chan, cookie, state);
  298. if (status == DMA_COMPLETE)
  299. return status;
  300. spin_lock_irqsave(&idma64c->vchan.lock, flags);
  301. vdesc = vchan_find_desc(&idma64c->vchan, cookie);
  302. if (idma64c->desc && cookie == idma64c->desc->vdesc.tx.cookie) {
  303. bytes = idma64_active_desc_size(idma64c);
  304. dma_set_residue(state, bytes);
  305. status = idma64c->desc->status;
  306. } else if (vdesc) {
  307. bytes = to_idma64_desc(vdesc)->length;
  308. dma_set_residue(state, bytes);
  309. }
  310. spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
  311. return status;
  312. }
  313. static void convert_burst(u32 *maxburst)
  314. {
  315. if (*maxburst)
  316. *maxburst = __fls(*maxburst);
  317. else
  318. *maxburst = 0;
  319. }
  320. static int idma64_slave_config(struct dma_chan *chan,
  321. struct dma_slave_config *config)
  322. {
  323. struct idma64_chan *idma64c = to_idma64_chan(chan);
  324. memcpy(&idma64c->config, config, sizeof(idma64c->config));
  325. convert_burst(&idma64c->config.src_maxburst);
  326. convert_burst(&idma64c->config.dst_maxburst);
  327. return 0;
  328. }
  329. static void idma64_chan_deactivate(struct idma64_chan *idma64c, bool drain)
  330. {
  331. unsigned short count = 100;
  332. u32 cfglo;
  333. cfglo = channel_readl(idma64c, CFG_LO);
  334. if (drain)
  335. cfglo |= IDMA64C_CFGL_CH_DRAIN;
  336. else
  337. cfglo &= ~IDMA64C_CFGL_CH_DRAIN;
  338. channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP);
  339. do {
  340. udelay(1);
  341. cfglo = channel_readl(idma64c, CFG_LO);
  342. } while (!(cfglo & IDMA64C_CFGL_FIFO_EMPTY) && --count);
  343. }
  344. static void idma64_chan_activate(struct idma64_chan *idma64c)
  345. {
  346. u32 cfglo;
  347. cfglo = channel_readl(idma64c, CFG_LO);
  348. channel_writel(idma64c, CFG_LO, cfglo & ~IDMA64C_CFGL_CH_SUSP);
  349. }
  350. static int idma64_pause(struct dma_chan *chan)
  351. {
  352. struct idma64_chan *idma64c = to_idma64_chan(chan);
  353. unsigned long flags;
  354. spin_lock_irqsave(&idma64c->vchan.lock, flags);
  355. if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) {
  356. idma64_chan_deactivate(idma64c, false);
  357. idma64c->desc->status = DMA_PAUSED;
  358. }
  359. spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
  360. return 0;
  361. }
  362. static int idma64_resume(struct dma_chan *chan)
  363. {
  364. struct idma64_chan *idma64c = to_idma64_chan(chan);
  365. unsigned long flags;
  366. spin_lock_irqsave(&idma64c->vchan.lock, flags);
  367. if (idma64c->desc && idma64c->desc->status == DMA_PAUSED) {
  368. idma64c->desc->status = DMA_IN_PROGRESS;
  369. idma64_chan_activate(idma64c);
  370. }
  371. spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
  372. return 0;
  373. }
  374. static int idma64_terminate_all(struct dma_chan *chan)
  375. {
  376. struct idma64_chan *idma64c = to_idma64_chan(chan);
  377. unsigned long flags;
  378. LIST_HEAD(head);
  379. spin_lock_irqsave(&idma64c->vchan.lock, flags);
  380. idma64_chan_deactivate(idma64c, true);
  381. idma64_stop_transfer(idma64c);
  382. if (idma64c->desc) {
  383. idma64_vdesc_free(&idma64c->desc->vdesc);
  384. idma64c->desc = NULL;
  385. }
  386. vchan_get_all_descriptors(&idma64c->vchan, &head);
  387. spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
  388. vchan_dma_desc_free_list(&idma64c->vchan, &head);
  389. return 0;
  390. }
  391. static void idma64_synchronize(struct dma_chan *chan)
  392. {
  393. struct idma64_chan *idma64c = to_idma64_chan(chan);
  394. vchan_synchronize(&idma64c->vchan);
  395. }
  396. static int idma64_alloc_chan_resources(struct dma_chan *chan)
  397. {
  398. struct idma64_chan *idma64c = to_idma64_chan(chan);
  399. /* Create a pool of consistent memory blocks for hardware descriptors */
  400. idma64c->pool = dma_pool_create(dev_name(chan2dev(chan)),
  401. chan->device->dev,
  402. sizeof(struct idma64_lli), 8, 0);
  403. if (!idma64c->pool) {
  404. dev_err(chan2dev(chan), "No memory for descriptors\n");
  405. return -ENOMEM;
  406. }
  407. return 0;
  408. }
  409. static void idma64_free_chan_resources(struct dma_chan *chan)
  410. {
  411. struct idma64_chan *idma64c = to_idma64_chan(chan);
  412. vchan_free_chan_resources(to_virt_chan(chan));
  413. dma_pool_destroy(idma64c->pool);
  414. idma64c->pool = NULL;
  415. }
  416. /* ---------------------------------------------------------------------- */
  417. #define IDMA64_BUSWIDTHS \
  418. BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
  419. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  420. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
  421. static int idma64_probe(struct idma64_chip *chip)
  422. {
  423. struct idma64 *idma64;
  424. unsigned short nr_chan = IDMA64_NR_CHAN;
  425. unsigned short i;
  426. int ret;
  427. idma64 = devm_kzalloc(chip->dev, sizeof(*idma64), GFP_KERNEL);
  428. if (!idma64)
  429. return -ENOMEM;
  430. idma64->regs = chip->regs;
  431. chip->idma64 = idma64;
  432. idma64->chan = devm_kcalloc(chip->dev, nr_chan, sizeof(*idma64->chan),
  433. GFP_KERNEL);
  434. if (!idma64->chan)
  435. return -ENOMEM;
  436. idma64->all_chan_mask = (1 << nr_chan) - 1;
  437. /* Turn off iDMA controller */
  438. idma64_off(idma64);
  439. ret = devm_request_irq(chip->dev, chip->irq, idma64_irq, IRQF_SHARED,
  440. dev_name(chip->dev), idma64);
  441. if (ret)
  442. return ret;
  443. INIT_LIST_HEAD(&idma64->dma.channels);
  444. for (i = 0; i < nr_chan; i++) {
  445. struct idma64_chan *idma64c = &idma64->chan[i];
  446. idma64c->vchan.desc_free = idma64_vdesc_free;
  447. vchan_init(&idma64c->vchan, &idma64->dma);
  448. idma64c->regs = idma64->regs + i * IDMA64_CH_LENGTH;
  449. idma64c->mask = BIT(i);
  450. }
  451. dma_cap_set(DMA_SLAVE, idma64->dma.cap_mask);
  452. dma_cap_set(DMA_PRIVATE, idma64->dma.cap_mask);
  453. idma64->dma.device_alloc_chan_resources = idma64_alloc_chan_resources;
  454. idma64->dma.device_free_chan_resources = idma64_free_chan_resources;
  455. idma64->dma.device_prep_slave_sg = idma64_prep_slave_sg;
  456. idma64->dma.device_issue_pending = idma64_issue_pending;
  457. idma64->dma.device_tx_status = idma64_tx_status;
  458. idma64->dma.device_config = idma64_slave_config;
  459. idma64->dma.device_pause = idma64_pause;
  460. idma64->dma.device_resume = idma64_resume;
  461. idma64->dma.device_terminate_all = idma64_terminate_all;
  462. idma64->dma.device_synchronize = idma64_synchronize;
  463. idma64->dma.src_addr_widths = IDMA64_BUSWIDTHS;
  464. idma64->dma.dst_addr_widths = IDMA64_BUSWIDTHS;
  465. idma64->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
  466. idma64->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
  467. idma64->dma.dev = chip->sysdev;
  468. dma_set_max_seg_size(idma64->dma.dev, IDMA64C_CTLH_BLOCK_TS_MASK);
  469. ret = dma_async_device_register(&idma64->dma);
  470. if (ret)
  471. return ret;
  472. dev_info(chip->dev, "Found Intel integrated DMA 64-bit\n");
  473. return 0;
  474. }
  475. static int idma64_remove(struct idma64_chip *chip)
  476. {
  477. struct idma64 *idma64 = chip->idma64;
  478. unsigned short i;
  479. dma_async_device_unregister(&idma64->dma);
  480. /*
  481. * Explicitly call devm_request_irq() to avoid the side effects with
  482. * the scheduled tasklets.
  483. */
  484. devm_free_irq(chip->dev, chip->irq, idma64);
  485. for (i = 0; i < idma64->dma.chancnt; i++) {
  486. struct idma64_chan *idma64c = &idma64->chan[i];
  487. tasklet_kill(&idma64c->vchan.task);
  488. }
  489. return 0;
  490. }
  491. /* ---------------------------------------------------------------------- */
  492. static int idma64_platform_probe(struct platform_device *pdev)
  493. {
  494. struct idma64_chip *chip;
  495. struct device *dev = &pdev->dev;
  496. struct device *sysdev = dev->parent;
  497. struct resource *mem;
  498. int ret;
  499. chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
  500. if (!chip)
  501. return -ENOMEM;
  502. chip->irq = platform_get_irq(pdev, 0);
  503. if (chip->irq < 0)
  504. return chip->irq;
  505. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  506. chip->regs = devm_ioremap_resource(dev, mem);
  507. if (IS_ERR(chip->regs))
  508. return PTR_ERR(chip->regs);
  509. ret = dma_coerce_mask_and_coherent(sysdev, DMA_BIT_MASK(64));
  510. if (ret)
  511. return ret;
  512. chip->dev = dev;
  513. chip->sysdev = sysdev;
  514. ret = idma64_probe(chip);
  515. if (ret)
  516. return ret;
  517. platform_set_drvdata(pdev, chip);
  518. return 0;
  519. }
  520. static int idma64_platform_remove(struct platform_device *pdev)
  521. {
  522. struct idma64_chip *chip = platform_get_drvdata(pdev);
  523. return idma64_remove(chip);
  524. }
  525. #ifdef CONFIG_PM_SLEEP
  526. static int idma64_pm_suspend(struct device *dev)
  527. {
  528. struct idma64_chip *chip = dev_get_drvdata(dev);
  529. idma64_off(chip->idma64);
  530. return 0;
  531. }
  532. static int idma64_pm_resume(struct device *dev)
  533. {
  534. struct idma64_chip *chip = dev_get_drvdata(dev);
  535. idma64_on(chip->idma64);
  536. return 0;
  537. }
  538. #endif /* CONFIG_PM_SLEEP */
  539. static const struct dev_pm_ops idma64_dev_pm_ops = {
  540. SET_SYSTEM_SLEEP_PM_OPS(idma64_pm_suspend, idma64_pm_resume)
  541. };
  542. static struct platform_driver idma64_platform_driver = {
  543. .probe = idma64_platform_probe,
  544. .remove = idma64_platform_remove,
  545. .driver = {
  546. .name = LPSS_IDMA64_DRIVER_NAME,
  547. .pm = &idma64_dev_pm_ops,
  548. },
  549. };
  550. module_platform_driver(idma64_platform_driver);
  551. MODULE_LICENSE("GPL v2");
  552. MODULE_DESCRIPTION("iDMA64 core driver");
  553. MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
  554. MODULE_ALIAS("platform:" LPSS_IDMA64_DRIVER_NAME);