fsl_raid.h 9.9 KB

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  1. /*
  2. * drivers/dma/fsl_raid.h
  3. *
  4. * Freescale RAID Engine device driver
  5. *
  6. * Author:
  7. * Harninder Rai <harninder.rai@freescale.com>
  8. * Naveen Burmi <naveenburmi@freescale.com>
  9. *
  10. * Rewrite:
  11. * Xuelin Shi <xuelin.shi@freescale.com>
  12. * Copyright (c) 2010-2012 Freescale Semiconductor, Inc.
  13. *
  14. * Redistribution and use in source and binary forms, with or without
  15. * modification, are permitted provided that the following conditions are met:
  16. * * Redistributions of source code must retain the above copyright
  17. * notice, this list of conditions and the following disclaimer.
  18. * * Redistributions in binary form must reproduce the above copyright
  19. * notice, this list of conditions and the following disclaimer in the
  20. * documentation and/or other materials provided with the distribution.
  21. * * Neither the name of Freescale Semiconductor nor the
  22. * names of its contributors may be used to endorse or promote products
  23. * derived from this software without specific prior written permission.
  24. *
  25. * ALTERNATIVELY, this software may be distributed under the terms of the
  26. * GNU General Public License ("GPL") as published by the Free Software
  27. * Foundation, either version 2 of that License or (at your option) any
  28. * later version.
  29. *
  30. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  31. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  32. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  34. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  35. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  36. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  39. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40. *
  41. */
  42. #define FSL_RE_MAX_CHANS 4
  43. #define FSL_RE_DPAA_MODE BIT(30)
  44. #define FSL_RE_NON_DPAA_MODE BIT(31)
  45. #define FSL_RE_GFM_POLY 0x1d000000
  46. #define FSL_RE_ADD_JOB(x) ((x) << 16)
  47. #define FSL_RE_RMVD_JOB(x) ((x) << 16)
  48. #define FSL_RE_CFG1_CBSI 0x08000000
  49. #define FSL_RE_CFG1_CBS0 0x00080000
  50. #define FSL_RE_SLOT_FULL_SHIFT 8
  51. #define FSL_RE_SLOT_FULL(x) ((x) >> FSL_RE_SLOT_FULL_SHIFT)
  52. #define FSL_RE_SLOT_AVAIL_SHIFT 8
  53. #define FSL_RE_SLOT_AVAIL(x) ((x) >> FSL_RE_SLOT_AVAIL_SHIFT)
  54. #define FSL_RE_PQ_OPCODE 0x1B
  55. #define FSL_RE_XOR_OPCODE 0x1A
  56. #define FSL_RE_MOVE_OPCODE 0x8
  57. #define FSL_RE_FRAME_ALIGN 16
  58. #define FSL_RE_BLOCK_SIZE 0x3 /* 4096 bytes */
  59. #define FSL_RE_CACHEABLE_IO 0x0
  60. #define FSL_RE_BUFFER_OUTPUT 0x0
  61. #define FSL_RE_INTR_ON_ERROR 0x1
  62. #define FSL_RE_DATA_DEP 0x1
  63. #define FSL_RE_ENABLE_DPI 0x0
  64. #define FSL_RE_RING_SIZE 0x400
  65. #define FSL_RE_RING_SIZE_MASK (FSL_RE_RING_SIZE - 1)
  66. #define FSL_RE_RING_SIZE_SHIFT 8
  67. #define FSL_RE_ADDR_BIT_SHIFT 4
  68. #define FSL_RE_ADDR_BIT_MASK (BIT(FSL_RE_ADDR_BIT_SHIFT) - 1)
  69. #define FSL_RE_ERROR 0x40000000
  70. #define FSL_RE_INTR 0x80000000
  71. #define FSL_RE_CLR_INTR 0x80000000
  72. #define FSL_RE_PAUSE 0x80000000
  73. #define FSL_RE_ENABLE 0x80000000
  74. #define FSL_RE_REG_LIODN_MASK 0x00000FFF
  75. #define FSL_RE_CDB_OPCODE_MASK 0xF8000000
  76. #define FSL_RE_CDB_OPCODE_SHIFT 27
  77. #define FSL_RE_CDB_EXCLEN_MASK 0x03000000
  78. #define FSL_RE_CDB_EXCLEN_SHIFT 24
  79. #define FSL_RE_CDB_EXCLQ1_MASK 0x00F00000
  80. #define FSL_RE_CDB_EXCLQ1_SHIFT 20
  81. #define FSL_RE_CDB_EXCLQ2_MASK 0x000F0000
  82. #define FSL_RE_CDB_EXCLQ2_SHIFT 16
  83. #define FSL_RE_CDB_BLKSIZE_MASK 0x0000C000
  84. #define FSL_RE_CDB_BLKSIZE_SHIFT 14
  85. #define FSL_RE_CDB_CACHE_MASK 0x00003000
  86. #define FSL_RE_CDB_CACHE_SHIFT 12
  87. #define FSL_RE_CDB_BUFFER_MASK 0x00000800
  88. #define FSL_RE_CDB_BUFFER_SHIFT 11
  89. #define FSL_RE_CDB_ERROR_MASK 0x00000400
  90. #define FSL_RE_CDB_ERROR_SHIFT 10
  91. #define FSL_RE_CDB_NRCS_MASK 0x0000003C
  92. #define FSL_RE_CDB_NRCS_SHIFT 6
  93. #define FSL_RE_CDB_DEPEND_MASK 0x00000008
  94. #define FSL_RE_CDB_DEPEND_SHIFT 3
  95. #define FSL_RE_CDB_DPI_MASK 0x00000004
  96. #define FSL_RE_CDB_DPI_SHIFT 2
  97. /*
  98. * the largest cf block is 19*sizeof(struct cmpnd_frame), which is 304 bytes.
  99. * here 19 = 1(cdb)+2(dest)+16(src), align to 64bytes, that is 320 bytes.
  100. * the largest cdb block: struct pq_cdb which is 180 bytes, adding to cf block
  101. * 320+180=500, align to 64bytes, that is 512 bytes.
  102. */
  103. #define FSL_RE_CF_DESC_SIZE 320
  104. #define FSL_RE_CF_CDB_SIZE 512
  105. #define FSL_RE_CF_CDB_ALIGN 64
  106. struct fsl_re_ctrl {
  107. /* General Configuration Registers */
  108. __be32 global_config; /* Global Configuration Register */
  109. u8 rsvd1[4];
  110. __be32 galois_field_config; /* Galois Field Configuration Register */
  111. u8 rsvd2[4];
  112. __be32 jq_wrr_config; /* WRR Configuration register */
  113. u8 rsvd3[4];
  114. __be32 crc_config; /* CRC Configuration register */
  115. u8 rsvd4[228];
  116. __be32 system_reset; /* System Reset Register */
  117. u8 rsvd5[252];
  118. __be32 global_status; /* Global Status Register */
  119. u8 rsvd6[832];
  120. __be32 re_liodn_base; /* LIODN Base Register */
  121. u8 rsvd7[1712];
  122. __be32 re_version_id; /* Version ID register of RE */
  123. __be32 re_version_id_2; /* Version ID 2 register of RE */
  124. u8 rsvd8[512];
  125. __be32 host_config; /* Host I/F Configuration Register */
  126. };
  127. struct fsl_re_chan_cfg {
  128. /* Registers for JR interface */
  129. __be32 jr_config_0; /* Job Queue Configuration 0 Register */
  130. __be32 jr_config_1; /* Job Queue Configuration 1 Register */
  131. __be32 jr_interrupt_status; /* Job Queue Interrupt Status Register */
  132. u8 rsvd1[4];
  133. __be32 jr_command; /* Job Queue Command Register */
  134. u8 rsvd2[4];
  135. __be32 jr_status; /* Job Queue Status Register */
  136. u8 rsvd3[228];
  137. /* Input Ring */
  138. __be32 inbring_base_h; /* Inbound Ring Base Address Register - High */
  139. __be32 inbring_base_l; /* Inbound Ring Base Address Register - Low */
  140. __be32 inbring_size; /* Inbound Ring Size Register */
  141. u8 rsvd4[4];
  142. __be32 inbring_slot_avail; /* Inbound Ring Slot Available Register */
  143. u8 rsvd5[4];
  144. __be32 inbring_add_job; /* Inbound Ring Add Job Register */
  145. u8 rsvd6[4];
  146. __be32 inbring_cnsmr_indx; /* Inbound Ring Consumer Index Register */
  147. u8 rsvd7[220];
  148. /* Output Ring */
  149. __be32 oubring_base_h; /* Outbound Ring Base Address Register - High */
  150. __be32 oubring_base_l; /* Outbound Ring Base Address Register - Low */
  151. __be32 oubring_size; /* Outbound Ring Size Register */
  152. u8 rsvd8[4];
  153. __be32 oubring_job_rmvd; /* Outbound Ring Job Removed Register */
  154. u8 rsvd9[4];
  155. __be32 oubring_slot_full; /* Outbound Ring Slot Full Register */
  156. u8 rsvd10[4];
  157. __be32 oubring_prdcr_indx; /* Outbound Ring Producer Index */
  158. };
  159. /*
  160. * Command Descriptor Block (CDB) for unicast move command.
  161. * In RAID Engine terms, memcpy is done through move command
  162. */
  163. struct fsl_re_move_cdb {
  164. __be32 cdb32;
  165. };
  166. /* Data protection/integrity related fields */
  167. #define FSL_RE_DPI_APPS_MASK 0xC0000000
  168. #define FSL_RE_DPI_APPS_SHIFT 30
  169. #define FSL_RE_DPI_REF_MASK 0x30000000
  170. #define FSL_RE_DPI_REF_SHIFT 28
  171. #define FSL_RE_DPI_GUARD_MASK 0x0C000000
  172. #define FSL_RE_DPI_GUARD_SHIFT 26
  173. #define FSL_RE_DPI_ATTR_MASK 0x03000000
  174. #define FSL_RE_DPI_ATTR_SHIFT 24
  175. #define FSL_RE_DPI_META_MASK 0x0000FFFF
  176. struct fsl_re_dpi {
  177. __be32 dpi32;
  178. __be32 ref;
  179. };
  180. /*
  181. * CDB for GenQ command. In RAID Engine terminology, XOR is
  182. * done through this command
  183. */
  184. struct fsl_re_xor_cdb {
  185. __be32 cdb32;
  186. u8 gfm[16];
  187. struct fsl_re_dpi dpi_dest_spec;
  188. struct fsl_re_dpi dpi_src_spec[16];
  189. };
  190. /* CDB for no-op command */
  191. struct fsl_re_noop_cdb {
  192. __be32 cdb32;
  193. };
  194. /*
  195. * CDB for GenQQ command. In RAID Engine terminology, P/Q is
  196. * done through this command
  197. */
  198. struct fsl_re_pq_cdb {
  199. __be32 cdb32;
  200. u8 gfm_q1[16];
  201. u8 gfm_q2[16];
  202. struct fsl_re_dpi dpi_dest_spec[2];
  203. struct fsl_re_dpi dpi_src_spec[16];
  204. };
  205. /* Compound frame */
  206. #define FSL_RE_CF_ADDR_HIGH_MASK 0x000000FF
  207. #define FSL_RE_CF_EXT_MASK 0x80000000
  208. #define FSL_RE_CF_EXT_SHIFT 31
  209. #define FSL_RE_CF_FINAL_MASK 0x40000000
  210. #define FSL_RE_CF_FINAL_SHIFT 30
  211. #define FSL_RE_CF_LENGTH_MASK 0x000FFFFF
  212. #define FSL_RE_CF_BPID_MASK 0x00FF0000
  213. #define FSL_RE_CF_BPID_SHIFT 16
  214. #define FSL_RE_CF_OFFSET_MASK 0x00001FFF
  215. struct fsl_re_cmpnd_frame {
  216. __be32 addr_high;
  217. __be32 addr_low;
  218. __be32 efrl32;
  219. __be32 rbro32;
  220. };
  221. /* Frame descriptor */
  222. #define FSL_RE_HWDESC_LIODN_MASK 0x3F000000
  223. #define FSL_RE_HWDESC_LIODN_SHIFT 24
  224. #define FSL_RE_HWDESC_BPID_MASK 0x00FF0000
  225. #define FSL_RE_HWDESC_BPID_SHIFT 16
  226. #define FSL_RE_HWDESC_ELIODN_MASK 0x0000F000
  227. #define FSL_RE_HWDESC_ELIODN_SHIFT 12
  228. #define FSL_RE_HWDESC_FMT_SHIFT 29
  229. #define FSL_RE_HWDESC_FMT_MASK (0x3 << FSL_RE_HWDESC_FMT_SHIFT)
  230. struct fsl_re_hw_desc {
  231. __be32 lbea32;
  232. __be32 addr_low;
  233. __be32 fmt32;
  234. __be32 status;
  235. };
  236. /* Raid Engine device private data */
  237. struct fsl_re_drv_private {
  238. u8 total_chans;
  239. struct dma_device dma_dev;
  240. struct fsl_re_ctrl *re_regs;
  241. struct fsl_re_chan *re_jrs[FSL_RE_MAX_CHANS];
  242. struct dma_pool *cf_desc_pool;
  243. struct dma_pool *hw_desc_pool;
  244. };
  245. /* Per job ring data structure */
  246. struct fsl_re_chan {
  247. char name[16];
  248. spinlock_t desc_lock; /* queue lock */
  249. struct list_head ack_q; /* wait to acked queue */
  250. struct list_head active_q; /* already issued on hw, not completed */
  251. struct list_head submit_q;
  252. struct list_head free_q; /* alloc available queue */
  253. struct device *dev;
  254. struct fsl_re_drv_private *re_dev;
  255. struct dma_chan chan;
  256. struct fsl_re_chan_cfg *jrregs;
  257. int irq;
  258. struct tasklet_struct irqtask;
  259. u32 alloc_count;
  260. /* hw descriptor ring for inbound queue*/
  261. dma_addr_t inb_phys_addr;
  262. struct fsl_re_hw_desc *inb_ring_virt_addr;
  263. u32 inb_count;
  264. /* hw descriptor ring for outbound queue */
  265. dma_addr_t oub_phys_addr;
  266. struct fsl_re_hw_desc *oub_ring_virt_addr;
  267. u32 oub_count;
  268. };
  269. /* Async transaction descriptor */
  270. struct fsl_re_desc {
  271. struct dma_async_tx_descriptor async_tx;
  272. struct list_head node;
  273. struct fsl_re_hw_desc hwdesc;
  274. struct fsl_re_chan *re_chan;
  275. /* hwdesc will point to cf_addr */
  276. void *cf_addr;
  277. dma_addr_t cf_paddr;
  278. void *cdb_addr;
  279. dma_addr_t cdb_paddr;
  280. int status;
  281. };