at_hdmac_regs.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Header file for the Atmel AHB DMA Controller driver
  4. *
  5. * Copyright (C) 2008 Atmel Corporation
  6. */
  7. #ifndef AT_HDMAC_REGS_H
  8. #define AT_HDMAC_REGS_H
  9. #include <linux/platform_data/dma-atmel.h>
  10. #define AT_DMA_MAX_NR_CHANNELS 8
  11. #define AT_DMA_GCFG 0x00 /* Global Configuration Register */
  12. #define AT_DMA_IF_BIGEND(i) (0x1 << (i)) /* AHB-Lite Interface i in Big-endian mode */
  13. #define AT_DMA_ARB_CFG (0x1 << 4) /* Arbiter mode. */
  14. #define AT_DMA_ARB_CFG_FIXED (0x0 << 4)
  15. #define AT_DMA_ARB_CFG_ROUND_ROBIN (0x1 << 4)
  16. #define AT_DMA_EN 0x04 /* Controller Enable Register */
  17. #define AT_DMA_ENABLE (0x1 << 0)
  18. #define AT_DMA_SREQ 0x08 /* Software Single Request Register */
  19. #define AT_DMA_SSREQ(x) (0x1 << ((x) << 1)) /* Request a source single transfer on channel x */
  20. #define AT_DMA_DSREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination single transfer on channel x */
  21. #define AT_DMA_CREQ 0x0C /* Software Chunk Transfer Request Register */
  22. #define AT_DMA_SCREQ(x) (0x1 << ((x) << 1)) /* Request a source chunk transfer on channel x */
  23. #define AT_DMA_DCREQ(x) (0x1 << (1 + ((x) << 1))) /* Request a destination chunk transfer on channel x */
  24. #define AT_DMA_LAST 0x10 /* Software Last Transfer Flag Register */
  25. #define AT_DMA_SLAST(x) (0x1 << ((x) << 1)) /* This src rq is last tx of buffer on channel x */
  26. #define AT_DMA_DLAST(x) (0x1 << (1 + ((x) << 1))) /* This dst rq is last tx of buffer on channel x */
  27. #define AT_DMA_SYNC 0x14 /* Request Synchronization Register */
  28. #define AT_DMA_SYR(h) (0x1 << (h)) /* Synchronize handshake line h */
  29. /* Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt registers */
  30. #define AT_DMA_EBCIER 0x18 /* Enable register */
  31. #define AT_DMA_EBCIDR 0x1C /* Disable register */
  32. #define AT_DMA_EBCIMR 0x20 /* Mask Register */
  33. #define AT_DMA_EBCISR 0x24 /* Status Register */
  34. #define AT_DMA_CBTC_OFFSET 8
  35. #define AT_DMA_ERR_OFFSET 16
  36. #define AT_DMA_BTC(x) (0x1 << (x))
  37. #define AT_DMA_CBTC(x) (0x1 << (AT_DMA_CBTC_OFFSET + (x)))
  38. #define AT_DMA_ERR(x) (0x1 << (AT_DMA_ERR_OFFSET + (x)))
  39. #define AT_DMA_CHER 0x28 /* Channel Handler Enable Register */
  40. #define AT_DMA_ENA(x) (0x1 << (x))
  41. #define AT_DMA_SUSP(x) (0x1 << ( 8 + (x)))
  42. #define AT_DMA_KEEP(x) (0x1 << (24 + (x)))
  43. #define AT_DMA_CHDR 0x2C /* Channel Handler Disable Register */
  44. #define AT_DMA_DIS(x) (0x1 << (x))
  45. #define AT_DMA_RES(x) (0x1 << ( 8 + (x)))
  46. #define AT_DMA_CHSR 0x30 /* Channel Handler Status Register */
  47. #define AT_DMA_EMPT(x) (0x1 << (16 + (x)))
  48. #define AT_DMA_STAL(x) (0x1 << (24 + (x)))
  49. #define AT_DMA_CH_REGS_BASE 0x3C /* Channel registers base address */
  50. #define ch_regs(x) (AT_DMA_CH_REGS_BASE + (x) * 0x28) /* Channel x base addr */
  51. /* Hardware register offset for each channel */
  52. #define ATC_SADDR_OFFSET 0x00 /* Source Address Register */
  53. #define ATC_DADDR_OFFSET 0x04 /* Destination Address Register */
  54. #define ATC_DSCR_OFFSET 0x08 /* Descriptor Address Register */
  55. #define ATC_CTRLA_OFFSET 0x0C /* Control A Register */
  56. #define ATC_CTRLB_OFFSET 0x10 /* Control B Register */
  57. #define ATC_CFG_OFFSET 0x14 /* Configuration Register */
  58. #define ATC_SPIP_OFFSET 0x18 /* Src PIP Configuration Register */
  59. #define ATC_DPIP_OFFSET 0x1C /* Dst PIP Configuration Register */
  60. /* Bitfield definitions */
  61. /* Bitfields in DSCR */
  62. #define ATC_DSCR_IF(i) (0x3 & (i)) /* Dsc feched via AHB-Lite Interface i */
  63. /* Bitfields in CTRLA */
  64. #define ATC_BTSIZE_MAX 0xFFFFUL /* Maximum Buffer Transfer Size */
  65. #define ATC_BTSIZE(x) (ATC_BTSIZE_MAX & (x)) /* Buffer Transfer Size */
  66. #define ATC_SCSIZE_MASK (0x7 << 16) /* Source Chunk Transfer Size */
  67. #define ATC_SCSIZE(x) (ATC_SCSIZE_MASK & ((x) << 16))
  68. #define ATC_SCSIZE_1 (0x0 << 16)
  69. #define ATC_SCSIZE_4 (0x1 << 16)
  70. #define ATC_SCSIZE_8 (0x2 << 16)
  71. #define ATC_SCSIZE_16 (0x3 << 16)
  72. #define ATC_SCSIZE_32 (0x4 << 16)
  73. #define ATC_SCSIZE_64 (0x5 << 16)
  74. #define ATC_SCSIZE_128 (0x6 << 16)
  75. #define ATC_SCSIZE_256 (0x7 << 16)
  76. #define ATC_DCSIZE_MASK (0x7 << 20) /* Destination Chunk Transfer Size */
  77. #define ATC_DCSIZE(x) (ATC_DCSIZE_MASK & ((x) << 20))
  78. #define ATC_DCSIZE_1 (0x0 << 20)
  79. #define ATC_DCSIZE_4 (0x1 << 20)
  80. #define ATC_DCSIZE_8 (0x2 << 20)
  81. #define ATC_DCSIZE_16 (0x3 << 20)
  82. #define ATC_DCSIZE_32 (0x4 << 20)
  83. #define ATC_DCSIZE_64 (0x5 << 20)
  84. #define ATC_DCSIZE_128 (0x6 << 20)
  85. #define ATC_DCSIZE_256 (0x7 << 20)
  86. #define ATC_SRC_WIDTH_MASK (0x3 << 24) /* Source Single Transfer Size */
  87. #define ATC_SRC_WIDTH(x) ((x) << 24)
  88. #define ATC_SRC_WIDTH_BYTE (0x0 << 24)
  89. #define ATC_SRC_WIDTH_HALFWORD (0x1 << 24)
  90. #define ATC_SRC_WIDTH_WORD (0x2 << 24)
  91. #define ATC_REG_TO_SRC_WIDTH(r) (((r) >> 24) & 0x3)
  92. #define ATC_DST_WIDTH_MASK (0x3 << 28) /* Destination Single Transfer Size */
  93. #define ATC_DST_WIDTH(x) ((x) << 28)
  94. #define ATC_DST_WIDTH_BYTE (0x0 << 28)
  95. #define ATC_DST_WIDTH_HALFWORD (0x1 << 28)
  96. #define ATC_DST_WIDTH_WORD (0x2 << 28)
  97. #define ATC_DONE (0x1 << 31) /* Tx Done (only written back in descriptor) */
  98. /* Bitfields in CTRLB */
  99. #define ATC_SIF(i) (0x3 & (i)) /* Src tx done via AHB-Lite Interface i */
  100. #define ATC_DIF(i) ((0x3 & (i)) << 4) /* Dst tx done via AHB-Lite Interface i */
  101. /* Specify AHB interfaces */
  102. #define AT_DMA_MEM_IF 0 /* interface 0 as memory interface */
  103. #define AT_DMA_PER_IF 1 /* interface 1 as peripheral interface */
  104. #define ATC_SRC_PIP (0x1 << 8) /* Source Picture-in-Picture enabled */
  105. #define ATC_DST_PIP (0x1 << 12) /* Destination Picture-in-Picture enabled */
  106. #define ATC_SRC_DSCR_DIS (0x1 << 16) /* Src Descriptor fetch disable */
  107. #define ATC_DST_DSCR_DIS (0x1 << 20) /* Dst Descriptor fetch disable */
  108. #define ATC_FC_MASK (0x7 << 21) /* Choose Flow Controller */
  109. #define ATC_FC_MEM2MEM (0x0 << 21) /* Mem-to-Mem (DMA) */
  110. #define ATC_FC_MEM2PER (0x1 << 21) /* Mem-to-Periph (DMA) */
  111. #define ATC_FC_PER2MEM (0x2 << 21) /* Periph-to-Mem (DMA) */
  112. #define ATC_FC_PER2PER (0x3 << 21) /* Periph-to-Periph (DMA) */
  113. #define ATC_FC_PER2MEM_PER (0x4 << 21) /* Periph-to-Mem (Peripheral) */
  114. #define ATC_FC_MEM2PER_PER (0x5 << 21) /* Mem-to-Periph (Peripheral) */
  115. #define ATC_FC_PER2PER_SRCPER (0x6 << 21) /* Periph-to-Periph (Src Peripheral) */
  116. #define ATC_FC_PER2PER_DSTPER (0x7 << 21) /* Periph-to-Periph (Dst Peripheral) */
  117. #define ATC_SRC_ADDR_MODE_MASK (0x3 << 24)
  118. #define ATC_SRC_ADDR_MODE_INCR (0x0 << 24) /* Incrementing Mode */
  119. #define ATC_SRC_ADDR_MODE_DECR (0x1 << 24) /* Decrementing Mode */
  120. #define ATC_SRC_ADDR_MODE_FIXED (0x2 << 24) /* Fixed Mode */
  121. #define ATC_DST_ADDR_MODE_MASK (0x3 << 28)
  122. #define ATC_DST_ADDR_MODE_INCR (0x0 << 28) /* Incrementing Mode */
  123. #define ATC_DST_ADDR_MODE_DECR (0x1 << 28) /* Decrementing Mode */
  124. #define ATC_DST_ADDR_MODE_FIXED (0x2 << 28) /* Fixed Mode */
  125. #define ATC_IEN (0x1 << 30) /* BTC interrupt enable (active low) */
  126. #define ATC_AUTO (0x1 << 31) /* Auto multiple buffer tx enable */
  127. /* Bitfields in CFG */
  128. /* are in at_hdmac.h */
  129. /* Bitfields in SPIP */
  130. #define ATC_SPIP_HOLE(x) (0xFFFFU & (x))
  131. #define ATC_SPIP_BOUNDARY(x) ((0x3FF & (x)) << 16)
  132. /* Bitfields in DPIP */
  133. #define ATC_DPIP_HOLE(x) (0xFFFFU & (x))
  134. #define ATC_DPIP_BOUNDARY(x) ((0x3FF & (x)) << 16)
  135. /*-- descriptors -----------------------------------------------------*/
  136. /* LLI == Linked List Item; aka DMA buffer descriptor */
  137. struct at_lli {
  138. /* values that are not changed by hardware */
  139. dma_addr_t saddr;
  140. dma_addr_t daddr;
  141. /* value that may get written back: */
  142. u32 ctrla;
  143. /* more values that are not changed by hardware */
  144. u32 ctrlb;
  145. dma_addr_t dscr; /* chain to next lli */
  146. };
  147. /**
  148. * struct at_desc - software descriptor
  149. * @at_lli: hardware lli structure
  150. * @txd: support for the async_tx api
  151. * @desc_node: node on the channed descriptors list
  152. * @len: descriptor byte count
  153. * @total_len: total transaction byte count
  154. */
  155. struct at_desc {
  156. /* FIRST values the hardware uses */
  157. struct at_lli lli;
  158. /* THEN values for driver housekeeping */
  159. struct list_head tx_list;
  160. struct dma_async_tx_descriptor txd;
  161. struct list_head desc_node;
  162. size_t len;
  163. size_t total_len;
  164. /* Interleaved data */
  165. size_t boundary;
  166. size_t dst_hole;
  167. size_t src_hole;
  168. /* Memset temporary buffer */
  169. bool memset_buffer;
  170. dma_addr_t memset_paddr;
  171. int *memset_vaddr;
  172. };
  173. static inline struct at_desc *
  174. txd_to_at_desc(struct dma_async_tx_descriptor *txd)
  175. {
  176. return container_of(txd, struct at_desc, txd);
  177. }
  178. /*-- Channels --------------------------------------------------------*/
  179. /**
  180. * atc_status - information bits stored in channel status flag
  181. *
  182. * Manipulated with atomic operations.
  183. */
  184. enum atc_status {
  185. ATC_IS_ERROR = 0,
  186. ATC_IS_PAUSED = 1,
  187. ATC_IS_CYCLIC = 24,
  188. };
  189. /**
  190. * struct at_dma_chan - internal representation of an Atmel HDMAC channel
  191. * @chan_common: common dmaengine channel object members
  192. * @device: parent device
  193. * @ch_regs: memory mapped register base
  194. * @mask: channel index in a mask
  195. * @per_if: peripheral interface
  196. * @mem_if: memory interface
  197. * @status: transmit status information from irq/prep* functions
  198. * to tasklet (use atomic operations)
  199. * @tasklet: bottom half to finish transaction work
  200. * @save_cfg: configuration register that is saved on suspend/resume cycle
  201. * @save_dscr: for cyclic operations, preserve next descriptor address in
  202. * the cyclic list on suspend/resume cycle
  203. * @dma_sconfig: configuration for slave transfers, passed via
  204. * .device_config
  205. * @lock: serializes enqueue/dequeue operations to descriptors lists
  206. * @active_list: list of descriptors dmaengine is being running on
  207. * @queue: list of descriptors ready to be submitted to engine
  208. * @free_list: list of descriptors usable by the channel
  209. */
  210. struct at_dma_chan {
  211. struct dma_chan chan_common;
  212. struct at_dma *device;
  213. void __iomem *ch_regs;
  214. u8 mask;
  215. u8 per_if;
  216. u8 mem_if;
  217. unsigned long status;
  218. struct tasklet_struct tasklet;
  219. u32 save_cfg;
  220. u32 save_dscr;
  221. struct dma_slave_config dma_sconfig;
  222. spinlock_t lock;
  223. /* these other elements are all protected by lock */
  224. struct list_head active_list;
  225. struct list_head queue;
  226. struct list_head free_list;
  227. };
  228. #define channel_readl(atchan, name) \
  229. __raw_readl((atchan)->ch_regs + ATC_##name##_OFFSET)
  230. #define channel_writel(atchan, name, val) \
  231. __raw_writel((val), (atchan)->ch_regs + ATC_##name##_OFFSET)
  232. static inline struct at_dma_chan *to_at_dma_chan(struct dma_chan *dchan)
  233. {
  234. return container_of(dchan, struct at_dma_chan, chan_common);
  235. }
  236. /*
  237. * Fix sconfig's burst size according to at_hdmac. We need to convert them as:
  238. * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
  239. *
  240. * This can be done by finding most significant bit set.
  241. */
  242. static inline void convert_burst(u32 *maxburst)
  243. {
  244. if (*maxburst > 1)
  245. *maxburst = fls(*maxburst) - 2;
  246. else
  247. *maxburst = 0;
  248. }
  249. /*
  250. * Fix sconfig's bus width according to at_hdmac.
  251. * 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2.
  252. */
  253. static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width)
  254. {
  255. switch (addr_width) {
  256. case DMA_SLAVE_BUSWIDTH_2_BYTES:
  257. return 1;
  258. case DMA_SLAVE_BUSWIDTH_4_BYTES:
  259. return 2;
  260. default:
  261. /* For 1 byte width or fallback */
  262. return 0;
  263. }
  264. }
  265. /*-- Controller ------------------------------------------------------*/
  266. /**
  267. * struct at_dma - internal representation of an Atmel HDMA Controller
  268. * @chan_common: common dmaengine dma_device object members
  269. * @atdma_devtype: identifier of DMA controller compatibility
  270. * @ch_regs: memory mapped register base
  271. * @clk: dma controller clock
  272. * @save_imr: interrupt mask register that is saved on suspend/resume cycle
  273. * @all_chan_mask: all channels availlable in a mask
  274. * @dma_desc_pool: base of DMA descriptor region (DMA address)
  275. * @chan: channels table to store at_dma_chan structures
  276. */
  277. struct at_dma {
  278. struct dma_device dma_common;
  279. void __iomem *regs;
  280. struct clk *clk;
  281. u32 save_imr;
  282. u8 all_chan_mask;
  283. struct dma_pool *dma_desc_pool;
  284. struct dma_pool *memset_pool;
  285. /* AT THE END channels table */
  286. struct at_dma_chan chan[];
  287. };
  288. #define dma_readl(atdma, name) \
  289. __raw_readl((atdma)->regs + AT_DMA_##name)
  290. #define dma_writel(atdma, name, val) \
  291. __raw_writel((val), (atdma)->regs + AT_DMA_##name)
  292. static inline struct at_dma *to_at_dma(struct dma_device *ddev)
  293. {
  294. return container_of(ddev, struct at_dma, dma_common);
  295. }
  296. /*-- Helper functions ------------------------------------------------*/
  297. static struct device *chan2dev(struct dma_chan *chan)
  298. {
  299. return &chan->dev->device;
  300. }
  301. #if defined(VERBOSE_DEBUG)
  302. static void vdbg_dump_regs(struct at_dma_chan *atchan)
  303. {
  304. struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
  305. dev_err(chan2dev(&atchan->chan_common),
  306. " channel %d : imr = 0x%x, chsr = 0x%x\n",
  307. atchan->chan_common.chan_id,
  308. dma_readl(atdma, EBCIMR),
  309. dma_readl(atdma, CHSR));
  310. dev_err(chan2dev(&atchan->chan_common),
  311. " channel: s0x%x d0x%x ctrl0x%x:0x%x cfg0x%x l0x%x\n",
  312. channel_readl(atchan, SADDR),
  313. channel_readl(atchan, DADDR),
  314. channel_readl(atchan, CTRLA),
  315. channel_readl(atchan, CTRLB),
  316. channel_readl(atchan, CFG),
  317. channel_readl(atchan, DSCR));
  318. }
  319. #else
  320. static void vdbg_dump_regs(struct at_dma_chan *atchan) {}
  321. #endif
  322. static void atc_dump_lli(struct at_dma_chan *atchan, struct at_lli *lli)
  323. {
  324. dev_crit(chan2dev(&atchan->chan_common),
  325. "desc: s%pad d%pad ctrl0x%x:0x%x l%pad\n",
  326. &lli->saddr, &lli->daddr,
  327. lli->ctrla, lli->ctrlb, &lli->dscr);
  328. }
  329. static void atc_setup_irq(struct at_dma *atdma, int chan_id, int on)
  330. {
  331. u32 ebci;
  332. /* enable interrupts on buffer transfer completion & error */
  333. ebci = AT_DMA_BTC(chan_id)
  334. | AT_DMA_ERR(chan_id);
  335. if (on)
  336. dma_writel(atdma, EBCIER, ebci);
  337. else
  338. dma_writel(atdma, EBCIDR, ebci);
  339. }
  340. static void atc_enable_chan_irq(struct at_dma *atdma, int chan_id)
  341. {
  342. atc_setup_irq(atdma, chan_id, 1);
  343. }
  344. static void atc_disable_chan_irq(struct at_dma *atdma, int chan_id)
  345. {
  346. atc_setup_irq(atdma, chan_id, 0);
  347. }
  348. /**
  349. * atc_chan_is_enabled - test if given channel is enabled
  350. * @atchan: channel we want to test status
  351. */
  352. static inline int atc_chan_is_enabled(struct at_dma_chan *atchan)
  353. {
  354. struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
  355. return !!(dma_readl(atdma, CHSR) & atchan->mask);
  356. }
  357. /**
  358. * atc_chan_is_paused - test channel pause/resume status
  359. * @atchan: channel we want to test status
  360. */
  361. static inline int atc_chan_is_paused(struct at_dma_chan *atchan)
  362. {
  363. return test_bit(ATC_IS_PAUSED, &atchan->status);
  364. }
  365. /**
  366. * atc_chan_is_cyclic - test if given channel has cyclic property set
  367. * @atchan: channel we want to test status
  368. */
  369. static inline int atc_chan_is_cyclic(struct at_dma_chan *atchan)
  370. {
  371. return test_bit(ATC_IS_CYCLIC, &atchan->status);
  372. }
  373. /**
  374. * set_desc_eol - set end-of-link to descriptor so it will end transfer
  375. * @desc: descriptor, signle or at the end of a chain, to end chain on
  376. */
  377. static void set_desc_eol(struct at_desc *desc)
  378. {
  379. u32 ctrlb = desc->lli.ctrlb;
  380. ctrlb &= ~ATC_IEN;
  381. ctrlb |= ATC_SRC_DSCR_DIS | ATC_DST_DSCR_DIS;
  382. desc->lli.ctrlb = ctrlb;
  383. desc->lli.dscr = 0;
  384. }
  385. #endif /* AT_HDMAC_REGS_H */