rk3399_dmc.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
  4. * Author: Lin Huang <hl@rock-chips.com>
  5. */
  6. #include <linux/arm-smccc.h>
  7. #include <linux/clk.h>
  8. #include <linux/delay.h>
  9. #include <linux/devfreq.h>
  10. #include <linux/devfreq-event.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/mfd/syscon.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm_opp.h>
  17. #include <linux/regmap.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <linux/rwsem.h>
  20. #include <linux/suspend.h>
  21. #include <soc/rockchip/rk3399_grf.h>
  22. #include <soc/rockchip/rockchip_sip.h>
  23. struct dram_timing {
  24. unsigned int ddr3_speed_bin;
  25. unsigned int pd_idle;
  26. unsigned int sr_idle;
  27. unsigned int sr_mc_gate_idle;
  28. unsigned int srpd_lite_idle;
  29. unsigned int standby_idle;
  30. unsigned int auto_pd_dis_freq;
  31. unsigned int dram_dll_dis_freq;
  32. unsigned int phy_dll_dis_freq;
  33. unsigned int ddr3_odt_dis_freq;
  34. unsigned int ddr3_drv;
  35. unsigned int ddr3_odt;
  36. unsigned int phy_ddr3_ca_drv;
  37. unsigned int phy_ddr3_dq_drv;
  38. unsigned int phy_ddr3_odt;
  39. unsigned int lpddr3_odt_dis_freq;
  40. unsigned int lpddr3_drv;
  41. unsigned int lpddr3_odt;
  42. unsigned int phy_lpddr3_ca_drv;
  43. unsigned int phy_lpddr3_dq_drv;
  44. unsigned int phy_lpddr3_odt;
  45. unsigned int lpddr4_odt_dis_freq;
  46. unsigned int lpddr4_drv;
  47. unsigned int lpddr4_dq_odt;
  48. unsigned int lpddr4_ca_odt;
  49. unsigned int phy_lpddr4_ca_drv;
  50. unsigned int phy_lpddr4_ck_cs_drv;
  51. unsigned int phy_lpddr4_dq_drv;
  52. unsigned int phy_lpddr4_odt;
  53. };
  54. struct rk3399_dmcfreq {
  55. struct device *dev;
  56. struct devfreq *devfreq;
  57. struct devfreq_simple_ondemand_data ondemand_data;
  58. struct clk *dmc_clk;
  59. struct devfreq_event_dev *edev;
  60. struct mutex lock;
  61. struct dram_timing timing;
  62. struct regulator *vdd_center;
  63. struct regmap *regmap_pmu;
  64. unsigned long rate, target_rate;
  65. unsigned long volt, target_volt;
  66. unsigned int odt_dis_freq;
  67. int odt_pd_arg0, odt_pd_arg1;
  68. };
  69. static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
  70. u32 flags)
  71. {
  72. struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
  73. struct dev_pm_opp *opp;
  74. unsigned long old_clk_rate = dmcfreq->rate;
  75. unsigned long target_volt, target_rate;
  76. struct arm_smccc_res res;
  77. bool odt_enable = false;
  78. int err;
  79. opp = devfreq_recommended_opp(dev, freq, flags);
  80. if (IS_ERR(opp))
  81. return PTR_ERR(opp);
  82. target_rate = dev_pm_opp_get_freq(opp);
  83. target_volt = dev_pm_opp_get_voltage(opp);
  84. dev_pm_opp_put(opp);
  85. if (dmcfreq->rate == target_rate)
  86. return 0;
  87. mutex_lock(&dmcfreq->lock);
  88. if (dmcfreq->regmap_pmu) {
  89. if (target_rate >= dmcfreq->odt_dis_freq)
  90. odt_enable = true;
  91. /*
  92. * This makes a SMC call to the TF-A to set the DDR PD
  93. * (power-down) timings and to enable or disable the
  94. * ODT (on-die termination) resistors.
  95. */
  96. arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0,
  97. dmcfreq->odt_pd_arg1,
  98. ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD,
  99. odt_enable, 0, 0, 0, &res);
  100. }
  101. /*
  102. * If frequency scaling from low to high, adjust voltage first.
  103. * If frequency scaling from high to low, adjust frequency first.
  104. */
  105. if (old_clk_rate < target_rate) {
  106. err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
  107. target_volt);
  108. if (err) {
  109. dev_err(dev, "Cannot set voltage %lu uV\n",
  110. target_volt);
  111. goto out;
  112. }
  113. }
  114. err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
  115. if (err) {
  116. dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate,
  117. err);
  118. regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
  119. dmcfreq->volt);
  120. goto out;
  121. }
  122. /*
  123. * Check the dpll rate,
  124. * There only two result we will get,
  125. * 1. Ddr frequency scaling fail, we still get the old rate.
  126. * 2. Ddr frequency scaling sucessful, we get the rate we set.
  127. */
  128. dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
  129. /* If get the incorrect rate, set voltage to old value. */
  130. if (dmcfreq->rate != target_rate) {
  131. dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n",
  132. target_rate, dmcfreq->rate);
  133. regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
  134. dmcfreq->volt);
  135. goto out;
  136. } else if (old_clk_rate > target_rate)
  137. err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
  138. target_volt);
  139. if (err)
  140. dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);
  141. dmcfreq->rate = target_rate;
  142. dmcfreq->volt = target_volt;
  143. out:
  144. mutex_unlock(&dmcfreq->lock);
  145. return err;
  146. }
  147. static int rk3399_dmcfreq_get_dev_status(struct device *dev,
  148. struct devfreq_dev_status *stat)
  149. {
  150. struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
  151. struct devfreq_event_data edata;
  152. int ret = 0;
  153. ret = devfreq_event_get_event(dmcfreq->edev, &edata);
  154. if (ret < 0)
  155. return ret;
  156. stat->current_frequency = dmcfreq->rate;
  157. stat->busy_time = edata.load_count;
  158. stat->total_time = edata.total_count;
  159. return ret;
  160. }
  161. static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
  162. {
  163. struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
  164. *freq = dmcfreq->rate;
  165. return 0;
  166. }
  167. static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
  168. .polling_ms = 200,
  169. .target = rk3399_dmcfreq_target,
  170. .get_dev_status = rk3399_dmcfreq_get_dev_status,
  171. .get_cur_freq = rk3399_dmcfreq_get_cur_freq,
  172. };
  173. static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
  174. {
  175. struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
  176. int ret = 0;
  177. ret = devfreq_event_disable_edev(dmcfreq->edev);
  178. if (ret < 0) {
  179. dev_err(dev, "failed to disable the devfreq-event devices\n");
  180. return ret;
  181. }
  182. ret = devfreq_suspend_device(dmcfreq->devfreq);
  183. if (ret < 0) {
  184. dev_err(dev, "failed to suspend the devfreq devices\n");
  185. return ret;
  186. }
  187. return 0;
  188. }
  189. static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
  190. {
  191. struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
  192. int ret = 0;
  193. ret = devfreq_event_enable_edev(dmcfreq->edev);
  194. if (ret < 0) {
  195. dev_err(dev, "failed to enable the devfreq-event devices\n");
  196. return ret;
  197. }
  198. ret = devfreq_resume_device(dmcfreq->devfreq);
  199. if (ret < 0) {
  200. dev_err(dev, "failed to resume the devfreq devices\n");
  201. return ret;
  202. }
  203. return ret;
  204. }
  205. static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
  206. rk3399_dmcfreq_resume);
  207. static int of_get_ddr_timings(struct dram_timing *timing,
  208. struct device_node *np)
  209. {
  210. int ret = 0;
  211. ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
  212. &timing->ddr3_speed_bin);
  213. ret |= of_property_read_u32(np, "rockchip,pd_idle",
  214. &timing->pd_idle);
  215. ret |= of_property_read_u32(np, "rockchip,sr_idle",
  216. &timing->sr_idle);
  217. ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
  218. &timing->sr_mc_gate_idle);
  219. ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
  220. &timing->srpd_lite_idle);
  221. ret |= of_property_read_u32(np, "rockchip,standby_idle",
  222. &timing->standby_idle);
  223. ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
  224. &timing->auto_pd_dis_freq);
  225. ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
  226. &timing->dram_dll_dis_freq);
  227. ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
  228. &timing->phy_dll_dis_freq);
  229. ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
  230. &timing->ddr3_odt_dis_freq);
  231. ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
  232. &timing->ddr3_drv);
  233. ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
  234. &timing->ddr3_odt);
  235. ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
  236. &timing->phy_ddr3_ca_drv);
  237. ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
  238. &timing->phy_ddr3_dq_drv);
  239. ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
  240. &timing->phy_ddr3_odt);
  241. ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
  242. &timing->lpddr3_odt_dis_freq);
  243. ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
  244. &timing->lpddr3_drv);
  245. ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
  246. &timing->lpddr3_odt);
  247. ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
  248. &timing->phy_lpddr3_ca_drv);
  249. ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
  250. &timing->phy_lpddr3_dq_drv);
  251. ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
  252. &timing->phy_lpddr3_odt);
  253. ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
  254. &timing->lpddr4_odt_dis_freq);
  255. ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
  256. &timing->lpddr4_drv);
  257. ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
  258. &timing->lpddr4_dq_odt);
  259. ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
  260. &timing->lpddr4_ca_odt);
  261. ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
  262. &timing->phy_lpddr4_ca_drv);
  263. ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
  264. &timing->phy_lpddr4_ck_cs_drv);
  265. ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
  266. &timing->phy_lpddr4_dq_drv);
  267. ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
  268. &timing->phy_lpddr4_odt);
  269. return ret;
  270. }
  271. static int rk3399_dmcfreq_probe(struct platform_device *pdev)
  272. {
  273. struct arm_smccc_res res;
  274. struct device *dev = &pdev->dev;
  275. struct device_node *np = pdev->dev.of_node, *node;
  276. struct rk3399_dmcfreq *data;
  277. int ret, index, size;
  278. uint32_t *timing;
  279. struct dev_pm_opp *opp;
  280. u32 ddr_type;
  281. u32 val;
  282. data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
  283. if (!data)
  284. return -ENOMEM;
  285. mutex_init(&data->lock);
  286. data->vdd_center = devm_regulator_get(dev, "center");
  287. if (IS_ERR(data->vdd_center)) {
  288. if (PTR_ERR(data->vdd_center) == -EPROBE_DEFER)
  289. return -EPROBE_DEFER;
  290. dev_err(dev, "Cannot get the regulator \"center\"\n");
  291. return PTR_ERR(data->vdd_center);
  292. }
  293. data->dmc_clk = devm_clk_get(dev, "dmc_clk");
  294. if (IS_ERR(data->dmc_clk)) {
  295. if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER)
  296. return -EPROBE_DEFER;
  297. dev_err(dev, "Cannot get the clk dmc_clk\n");
  298. return PTR_ERR(data->dmc_clk);
  299. }
  300. data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0);
  301. if (IS_ERR(data->edev))
  302. return -EPROBE_DEFER;
  303. ret = devfreq_event_enable_edev(data->edev);
  304. if (ret < 0) {
  305. dev_err(dev, "failed to enable devfreq-event devices\n");
  306. return ret;
  307. }
  308. /*
  309. * Get dram timing and pass it to arm trust firmware,
  310. * the dram driver in arm trust firmware will get these
  311. * timing and to do dram initial.
  312. */
  313. if (!of_get_ddr_timings(&data->timing, np)) {
  314. timing = &data->timing.ddr3_speed_bin;
  315. size = sizeof(struct dram_timing) / 4;
  316. for (index = 0; index < size; index++) {
  317. arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
  318. ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
  319. 0, 0, 0, 0, &res);
  320. if (res.a0) {
  321. dev_err(dev, "Failed to set dram param: %ld\n",
  322. res.a0);
  323. ret = -EINVAL;
  324. goto err_edev;
  325. }
  326. }
  327. }
  328. node = of_parse_phandle(np, "rockchip,pmu", 0);
  329. if (!node)
  330. goto no_pmu;
  331. data->regmap_pmu = syscon_node_to_regmap(node);
  332. of_node_put(node);
  333. if (IS_ERR(data->regmap_pmu)) {
  334. ret = PTR_ERR(data->regmap_pmu);
  335. goto err_edev;
  336. }
  337. regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
  338. ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
  339. RK3399_PMUGRF_DDRTYPE_MASK;
  340. switch (ddr_type) {
  341. case RK3399_PMUGRF_DDRTYPE_DDR3:
  342. data->odt_dis_freq = data->timing.ddr3_odt_dis_freq;
  343. break;
  344. case RK3399_PMUGRF_DDRTYPE_LPDDR3:
  345. data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq;
  346. break;
  347. case RK3399_PMUGRF_DDRTYPE_LPDDR4:
  348. data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq;
  349. break;
  350. default:
  351. ret = -EINVAL;
  352. goto err_edev;
  353. };
  354. no_pmu:
  355. arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
  356. ROCKCHIP_SIP_CONFIG_DRAM_INIT,
  357. 0, 0, 0, 0, &res);
  358. /*
  359. * In TF-A there is a platform SIP call to set the PD (power-down)
  360. * timings and to enable or disable the ODT (on-die termination).
  361. * This call needs three arguments as follows:
  362. *
  363. * arg0:
  364. * bit[0-7] : sr_idle
  365. * bit[8-15] : sr_mc_gate_idle
  366. * bit[16-31] : standby idle
  367. * arg1:
  368. * bit[0-11] : pd_idle
  369. * bit[16-27] : srpd_lite_idle
  370. * arg2:
  371. * bit[0] : odt enable
  372. */
  373. data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) |
  374. ((data->timing.sr_mc_gate_idle & 0xff) << 8) |
  375. ((data->timing.standby_idle & 0xffff) << 16);
  376. data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) |
  377. ((data->timing.srpd_lite_idle & 0xfff) << 16);
  378. /*
  379. * We add a devfreq driver to our parent since it has a device tree node
  380. * with operating points.
  381. */
  382. if (dev_pm_opp_of_add_table(dev)) {
  383. dev_err(dev, "Invalid operating-points in device tree.\n");
  384. ret = -EINVAL;
  385. goto err_edev;
  386. }
  387. of_property_read_u32(np, "upthreshold",
  388. &data->ondemand_data.upthreshold);
  389. of_property_read_u32(np, "downdifferential",
  390. &data->ondemand_data.downdifferential);
  391. data->rate = clk_get_rate(data->dmc_clk);
  392. opp = devfreq_recommended_opp(dev, &data->rate, 0);
  393. if (IS_ERR(opp)) {
  394. ret = PTR_ERR(opp);
  395. goto err_free_opp;
  396. }
  397. data->rate = dev_pm_opp_get_freq(opp);
  398. data->volt = dev_pm_opp_get_voltage(opp);
  399. dev_pm_opp_put(opp);
  400. rk3399_devfreq_dmc_profile.initial_freq = data->rate;
  401. data->devfreq = devm_devfreq_add_device(dev,
  402. &rk3399_devfreq_dmc_profile,
  403. DEVFREQ_GOV_SIMPLE_ONDEMAND,
  404. &data->ondemand_data);
  405. if (IS_ERR(data->devfreq)) {
  406. ret = PTR_ERR(data->devfreq);
  407. goto err_free_opp;
  408. }
  409. devm_devfreq_register_opp_notifier(dev, data->devfreq);
  410. data->dev = dev;
  411. platform_set_drvdata(pdev, data);
  412. return 0;
  413. err_free_opp:
  414. dev_pm_opp_of_remove_table(&pdev->dev);
  415. err_edev:
  416. devfreq_event_disable_edev(data->edev);
  417. return ret;
  418. }
  419. static int rk3399_dmcfreq_remove(struct platform_device *pdev)
  420. {
  421. struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev);
  422. /*
  423. * Before remove the opp table we need to unregister the opp notifier.
  424. */
  425. devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq);
  426. dev_pm_opp_of_remove_table(dmcfreq->dev);
  427. return 0;
  428. }
  429. static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
  430. { .compatible = "rockchip,rk3399-dmc" },
  431. { },
  432. };
  433. MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);
  434. static struct platform_driver rk3399_dmcfreq_driver = {
  435. .probe = rk3399_dmcfreq_probe,
  436. .remove = rk3399_dmcfreq_remove,
  437. .driver = {
  438. .name = "rk3399-dmc-freq",
  439. .pm = &rk3399_dmcfreq_pm,
  440. .of_match_table = rk3399dmc_devfreq_of_match,
  441. },
  442. };
  443. module_platform_driver(rk3399_dmcfreq_driver);
  444. MODULE_LICENSE("GPL v2");
  445. MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
  446. MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");