stm32-crc32.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) STMicroelectronics SA 2017
  4. * Author: Fabien Dessenne <fabien.dessenne@st.com>
  5. */
  6. #include <linux/bitrev.h>
  7. #include <linux/clk.h>
  8. #include <linux/crc32.h>
  9. #include <linux/crc32poly.h>
  10. #include <linux/io.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/mod_devicetable.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_runtime.h>
  16. #include <crypto/internal/hash.h>
  17. #include <asm/unaligned.h>
  18. #define DRIVER_NAME "stm32-crc32"
  19. #define CHKSUM_DIGEST_SIZE 4
  20. #define CHKSUM_BLOCK_SIZE 1
  21. /* Registers */
  22. #define CRC_DR 0x00000000
  23. #define CRC_CR 0x00000008
  24. #define CRC_INIT 0x00000010
  25. #define CRC_POL 0x00000014
  26. /* Registers values */
  27. #define CRC_CR_RESET BIT(0)
  28. #define CRC_CR_REV_IN_WORD (BIT(6) | BIT(5))
  29. #define CRC_CR_REV_IN_BYTE BIT(5)
  30. #define CRC_CR_REV_OUT BIT(7)
  31. #define CRC32C_INIT_DEFAULT 0xFFFFFFFF
  32. #define CRC_AUTOSUSPEND_DELAY 50
  33. static unsigned int burst_size;
  34. module_param(burst_size, uint, 0644);
  35. MODULE_PARM_DESC(burst_size, "Select burst byte size (0 unlimited)");
  36. struct stm32_crc {
  37. struct list_head list;
  38. struct device *dev;
  39. void __iomem *regs;
  40. struct clk *clk;
  41. spinlock_t lock;
  42. };
  43. struct stm32_crc_list {
  44. struct list_head dev_list;
  45. spinlock_t lock; /* protect dev_list */
  46. };
  47. static struct stm32_crc_list crc_list = {
  48. .dev_list = LIST_HEAD_INIT(crc_list.dev_list),
  49. .lock = __SPIN_LOCK_UNLOCKED(crc_list.lock),
  50. };
  51. struct stm32_crc_ctx {
  52. u32 key;
  53. u32 poly;
  54. };
  55. struct stm32_crc_desc_ctx {
  56. u32 partial; /* crc32c: partial in first 4 bytes of that struct */
  57. };
  58. static int stm32_crc32_cra_init(struct crypto_tfm *tfm)
  59. {
  60. struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
  61. mctx->key = 0;
  62. mctx->poly = CRC32_POLY_LE;
  63. return 0;
  64. }
  65. static int stm32_crc32c_cra_init(struct crypto_tfm *tfm)
  66. {
  67. struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
  68. mctx->key = CRC32C_INIT_DEFAULT;
  69. mctx->poly = CRC32C_POLY_LE;
  70. return 0;
  71. }
  72. static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key,
  73. unsigned int keylen)
  74. {
  75. struct stm32_crc_ctx *mctx = crypto_shash_ctx(tfm);
  76. if (keylen != sizeof(u32))
  77. return -EINVAL;
  78. mctx->key = get_unaligned_le32(key);
  79. return 0;
  80. }
  81. static struct stm32_crc *stm32_crc_get_next_crc(void)
  82. {
  83. struct stm32_crc *crc;
  84. spin_lock_bh(&crc_list.lock);
  85. crc = list_first_entry(&crc_list.dev_list, struct stm32_crc, list);
  86. if (crc)
  87. list_move_tail(&crc->list, &crc_list.dev_list);
  88. spin_unlock_bh(&crc_list.lock);
  89. return crc;
  90. }
  91. static int stm32_crc_init(struct shash_desc *desc)
  92. {
  93. struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
  94. struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
  95. struct stm32_crc *crc;
  96. unsigned long flags;
  97. crc = stm32_crc_get_next_crc();
  98. if (!crc)
  99. return -ENODEV;
  100. pm_runtime_get_sync(crc->dev);
  101. spin_lock_irqsave(&crc->lock, flags);
  102. /* Reset, set key, poly and configure in bit reverse mode */
  103. writel_relaxed(bitrev32(mctx->key), crc->regs + CRC_INIT);
  104. writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
  105. writel_relaxed(CRC_CR_RESET | CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
  106. crc->regs + CRC_CR);
  107. /* Store partial result */
  108. ctx->partial = readl_relaxed(crc->regs + CRC_DR);
  109. spin_unlock_irqrestore(&crc->lock, flags);
  110. pm_runtime_mark_last_busy(crc->dev);
  111. pm_runtime_put_autosuspend(crc->dev);
  112. return 0;
  113. }
  114. static int burst_update(struct shash_desc *desc, const u8 *d8,
  115. size_t length)
  116. {
  117. struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
  118. struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
  119. struct stm32_crc *crc;
  120. crc = stm32_crc_get_next_crc();
  121. if (!crc)
  122. return -ENODEV;
  123. pm_runtime_get_sync(crc->dev);
  124. if (!spin_trylock(&crc->lock)) {
  125. /* Hardware is busy, calculate crc32 by software */
  126. if (mctx->poly == CRC32_POLY_LE)
  127. ctx->partial = crc32_le(ctx->partial, d8, length);
  128. else
  129. ctx->partial = __crc32c_le(ctx->partial, d8, length);
  130. goto pm_out;
  131. }
  132. /*
  133. * Restore previously calculated CRC for this context as init value
  134. * Restore polynomial configuration
  135. * Configure in register for word input data,
  136. * Configure out register in reversed bit mode data.
  137. */
  138. writel_relaxed(bitrev32(ctx->partial), crc->regs + CRC_INIT);
  139. writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
  140. writel_relaxed(CRC_CR_RESET | CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
  141. crc->regs + CRC_CR);
  142. if (d8 != PTR_ALIGN(d8, sizeof(u32))) {
  143. /* Configure for byte data */
  144. writel_relaxed(CRC_CR_REV_IN_BYTE | CRC_CR_REV_OUT,
  145. crc->regs + CRC_CR);
  146. while (d8 != PTR_ALIGN(d8, sizeof(u32)) && length) {
  147. writeb_relaxed(*d8++, crc->regs + CRC_DR);
  148. length--;
  149. }
  150. /* Configure for word data */
  151. writel_relaxed(CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
  152. crc->regs + CRC_CR);
  153. }
  154. for (; length >= sizeof(u32); d8 += sizeof(u32), length -= sizeof(u32))
  155. writel_relaxed(*((u32 *)d8), crc->regs + CRC_DR);
  156. if (length) {
  157. /* Configure for byte data */
  158. writel_relaxed(CRC_CR_REV_IN_BYTE | CRC_CR_REV_OUT,
  159. crc->regs + CRC_CR);
  160. while (length--)
  161. writeb_relaxed(*d8++, crc->regs + CRC_DR);
  162. }
  163. /* Store partial result */
  164. ctx->partial = readl_relaxed(crc->regs + CRC_DR);
  165. spin_unlock(&crc->lock);
  166. pm_out:
  167. pm_runtime_mark_last_busy(crc->dev);
  168. pm_runtime_put_autosuspend(crc->dev);
  169. return 0;
  170. }
  171. static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
  172. unsigned int length)
  173. {
  174. const unsigned int burst_sz = burst_size;
  175. unsigned int rem_sz;
  176. const u8 *cur;
  177. size_t size;
  178. int ret;
  179. if (!burst_sz)
  180. return burst_update(desc, d8, length);
  181. /* Digest first bytes not 32bit aligned at first pass in the loop */
  182. size = min_t(size_t, length, burst_sz + (size_t)d8 -
  183. ALIGN_DOWN((size_t)d8, sizeof(u32)));
  184. for (rem_sz = length, cur = d8; rem_sz;
  185. rem_sz -= size, cur += size, size = min(rem_sz, burst_sz)) {
  186. ret = burst_update(desc, cur, size);
  187. if (ret)
  188. return ret;
  189. }
  190. return 0;
  191. }
  192. static int stm32_crc_final(struct shash_desc *desc, u8 *out)
  193. {
  194. struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
  195. struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
  196. /* Send computed CRC */
  197. put_unaligned_le32(mctx->poly == CRC32C_POLY_LE ?
  198. ~ctx->partial : ctx->partial, out);
  199. return 0;
  200. }
  201. static int stm32_crc_finup(struct shash_desc *desc, const u8 *data,
  202. unsigned int length, u8 *out)
  203. {
  204. return stm32_crc_update(desc, data, length) ?:
  205. stm32_crc_final(desc, out);
  206. }
  207. static int stm32_crc_digest(struct shash_desc *desc, const u8 *data,
  208. unsigned int length, u8 *out)
  209. {
  210. return stm32_crc_init(desc) ?: stm32_crc_finup(desc, data, length, out);
  211. }
  212. static unsigned int refcnt;
  213. static DEFINE_MUTEX(refcnt_lock);
  214. static struct shash_alg algs[] = {
  215. /* CRC-32 */
  216. {
  217. .setkey = stm32_crc_setkey,
  218. .init = stm32_crc_init,
  219. .update = stm32_crc_update,
  220. .final = stm32_crc_final,
  221. .finup = stm32_crc_finup,
  222. .digest = stm32_crc_digest,
  223. .descsize = sizeof(struct stm32_crc_desc_ctx),
  224. .digestsize = CHKSUM_DIGEST_SIZE,
  225. .base = {
  226. .cra_name = "crc32",
  227. .cra_driver_name = "stm32-crc32-crc32",
  228. .cra_priority = 200,
  229. .cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
  230. .cra_blocksize = CHKSUM_BLOCK_SIZE,
  231. .cra_alignmask = 3,
  232. .cra_ctxsize = sizeof(struct stm32_crc_ctx),
  233. .cra_module = THIS_MODULE,
  234. .cra_init = stm32_crc32_cra_init,
  235. }
  236. },
  237. /* CRC-32Castagnoli */
  238. {
  239. .setkey = stm32_crc_setkey,
  240. .init = stm32_crc_init,
  241. .update = stm32_crc_update,
  242. .final = stm32_crc_final,
  243. .finup = stm32_crc_finup,
  244. .digest = stm32_crc_digest,
  245. .descsize = sizeof(struct stm32_crc_desc_ctx),
  246. .digestsize = CHKSUM_DIGEST_SIZE,
  247. .base = {
  248. .cra_name = "crc32c",
  249. .cra_driver_name = "stm32-crc32-crc32c",
  250. .cra_priority = 200,
  251. .cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
  252. .cra_blocksize = CHKSUM_BLOCK_SIZE,
  253. .cra_alignmask = 3,
  254. .cra_ctxsize = sizeof(struct stm32_crc_ctx),
  255. .cra_module = THIS_MODULE,
  256. .cra_init = stm32_crc32c_cra_init,
  257. }
  258. }
  259. };
  260. static int stm32_crc_probe(struct platform_device *pdev)
  261. {
  262. struct device *dev = &pdev->dev;
  263. struct stm32_crc *crc;
  264. int ret;
  265. crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
  266. if (!crc)
  267. return -ENOMEM;
  268. crc->dev = dev;
  269. crc->regs = devm_platform_ioremap_resource(pdev, 0);
  270. if (IS_ERR(crc->regs)) {
  271. dev_err(dev, "Cannot map CRC IO\n");
  272. return PTR_ERR(crc->regs);
  273. }
  274. crc->clk = devm_clk_get(dev, NULL);
  275. if (IS_ERR(crc->clk)) {
  276. dev_err(dev, "Could not get clock\n");
  277. return PTR_ERR(crc->clk);
  278. }
  279. ret = clk_prepare_enable(crc->clk);
  280. if (ret) {
  281. dev_err(crc->dev, "Failed to enable clock\n");
  282. return ret;
  283. }
  284. pm_runtime_set_autosuspend_delay(dev, CRC_AUTOSUSPEND_DELAY);
  285. pm_runtime_use_autosuspend(dev);
  286. pm_runtime_get_noresume(dev);
  287. pm_runtime_set_active(dev);
  288. pm_runtime_irq_safe(dev);
  289. pm_runtime_enable(dev);
  290. spin_lock_init(&crc->lock);
  291. platform_set_drvdata(pdev, crc);
  292. spin_lock(&crc_list.lock);
  293. list_add(&crc->list, &crc_list.dev_list);
  294. spin_unlock(&crc_list.lock);
  295. mutex_lock(&refcnt_lock);
  296. if (!refcnt) {
  297. ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
  298. if (ret) {
  299. mutex_unlock(&refcnt_lock);
  300. dev_err(dev, "Failed to register\n");
  301. clk_disable_unprepare(crc->clk);
  302. return ret;
  303. }
  304. }
  305. refcnt++;
  306. mutex_unlock(&refcnt_lock);
  307. dev_info(dev, "Initialized\n");
  308. pm_runtime_put_sync(dev);
  309. return 0;
  310. }
  311. static int stm32_crc_remove(struct platform_device *pdev)
  312. {
  313. struct stm32_crc *crc = platform_get_drvdata(pdev);
  314. int ret = pm_runtime_get_sync(crc->dev);
  315. if (ret < 0)
  316. return ret;
  317. spin_lock(&crc_list.lock);
  318. list_del(&crc->list);
  319. spin_unlock(&crc_list.lock);
  320. mutex_lock(&refcnt_lock);
  321. if (!--refcnt)
  322. crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
  323. mutex_unlock(&refcnt_lock);
  324. pm_runtime_disable(crc->dev);
  325. pm_runtime_put_noidle(crc->dev);
  326. clk_disable_unprepare(crc->clk);
  327. return 0;
  328. }
  329. static int __maybe_unused stm32_crc_suspend(struct device *dev)
  330. {
  331. struct stm32_crc *crc = dev_get_drvdata(dev);
  332. int ret;
  333. ret = pm_runtime_force_suspend(dev);
  334. if (ret)
  335. return ret;
  336. clk_unprepare(crc->clk);
  337. return 0;
  338. }
  339. static int __maybe_unused stm32_crc_resume(struct device *dev)
  340. {
  341. struct stm32_crc *crc = dev_get_drvdata(dev);
  342. int ret;
  343. ret = clk_prepare(crc->clk);
  344. if (ret) {
  345. dev_err(crc->dev, "Failed to prepare clock\n");
  346. return ret;
  347. }
  348. return pm_runtime_force_resume(dev);
  349. }
  350. static int __maybe_unused stm32_crc_runtime_suspend(struct device *dev)
  351. {
  352. struct stm32_crc *crc = dev_get_drvdata(dev);
  353. clk_disable(crc->clk);
  354. return 0;
  355. }
  356. static int __maybe_unused stm32_crc_runtime_resume(struct device *dev)
  357. {
  358. struct stm32_crc *crc = dev_get_drvdata(dev);
  359. int ret;
  360. ret = clk_enable(crc->clk);
  361. if (ret) {
  362. dev_err(crc->dev, "Failed to enable clock\n");
  363. return ret;
  364. }
  365. return 0;
  366. }
  367. static const struct dev_pm_ops stm32_crc_pm_ops = {
  368. SET_SYSTEM_SLEEP_PM_OPS(stm32_crc_suspend,
  369. stm32_crc_resume)
  370. SET_RUNTIME_PM_OPS(stm32_crc_runtime_suspend,
  371. stm32_crc_runtime_resume, NULL)
  372. };
  373. static const struct of_device_id stm32_dt_ids[] = {
  374. { .compatible = "st,stm32f7-crc", },
  375. {},
  376. };
  377. MODULE_DEVICE_TABLE(of, stm32_dt_ids);
  378. static struct platform_driver stm32_crc_driver = {
  379. .probe = stm32_crc_probe,
  380. .remove = stm32_crc_remove,
  381. .driver = {
  382. .name = DRIVER_NAME,
  383. .pm = &stm32_crc_pm_ops,
  384. .of_match_table = stm32_dt_ids,
  385. },
  386. };
  387. module_platform_driver(stm32_crc_driver);
  388. MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
  389. MODULE_DESCRIPTION("STMicrolectronics STM32 CRC32 hardware driver");
  390. MODULE_LICENSE("GPL");