rk3288_crypto_ahash.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Crypto acceleration support for Rockchip RK3288
  4. *
  5. * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
  6. *
  7. * Author: Zain Wang <zain.wang@rock-chips.com>
  8. *
  9. * Some ideas are from marvell/cesa.c and s5p-sss.c driver.
  10. */
  11. #include <linux/device.h>
  12. #include "rk3288_crypto.h"
  13. /*
  14. * IC can not process zero message hash,
  15. * so we put the fixed hash out when met zero message.
  16. */
  17. static int zero_message_process(struct ahash_request *req)
  18. {
  19. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  20. int rk_digest_size = crypto_ahash_digestsize(tfm);
  21. switch (rk_digest_size) {
  22. case SHA1_DIGEST_SIZE:
  23. memcpy(req->result, sha1_zero_message_hash, rk_digest_size);
  24. break;
  25. case SHA256_DIGEST_SIZE:
  26. memcpy(req->result, sha256_zero_message_hash, rk_digest_size);
  27. break;
  28. case MD5_DIGEST_SIZE:
  29. memcpy(req->result, md5_zero_message_hash, rk_digest_size);
  30. break;
  31. default:
  32. return -EINVAL;
  33. }
  34. return 0;
  35. }
  36. static void rk_ahash_crypto_complete(struct crypto_async_request *base, int err)
  37. {
  38. if (base->complete)
  39. base->complete(base, err);
  40. }
  41. static void rk_ahash_reg_init(struct rk_crypto_info *dev)
  42. {
  43. struct ahash_request *req = ahash_request_cast(dev->async_req);
  44. struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
  45. int reg_status = 0;
  46. reg_status = CRYPTO_READ(dev, RK_CRYPTO_CTRL) |
  47. RK_CRYPTO_HASH_FLUSH | _SBF(0xffff, 16);
  48. CRYPTO_WRITE(dev, RK_CRYPTO_CTRL, reg_status);
  49. reg_status = CRYPTO_READ(dev, RK_CRYPTO_CTRL);
  50. reg_status &= (~RK_CRYPTO_HASH_FLUSH);
  51. reg_status |= _SBF(0xffff, 16);
  52. CRYPTO_WRITE(dev, RK_CRYPTO_CTRL, reg_status);
  53. memset_io(dev->reg + RK_CRYPTO_HASH_DOUT_0, 0, 32);
  54. CRYPTO_WRITE(dev, RK_CRYPTO_INTENA, RK_CRYPTO_HRDMA_ERR_ENA |
  55. RK_CRYPTO_HRDMA_DONE_ENA);
  56. CRYPTO_WRITE(dev, RK_CRYPTO_INTSTS, RK_CRYPTO_HRDMA_ERR_INT |
  57. RK_CRYPTO_HRDMA_DONE_INT);
  58. CRYPTO_WRITE(dev, RK_CRYPTO_HASH_CTRL, rctx->mode |
  59. RK_CRYPTO_HASH_SWAP_DO);
  60. CRYPTO_WRITE(dev, RK_CRYPTO_CONF, RK_CRYPTO_BYTESWAP_HRFIFO |
  61. RK_CRYPTO_BYTESWAP_BRFIFO |
  62. RK_CRYPTO_BYTESWAP_BTFIFO);
  63. CRYPTO_WRITE(dev, RK_CRYPTO_HASH_MSG_LEN, dev->total);
  64. }
  65. static int rk_ahash_init(struct ahash_request *req)
  66. {
  67. struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
  68. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  69. struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  70. ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
  71. rctx->fallback_req.base.flags = req->base.flags &
  72. CRYPTO_TFM_REQ_MAY_SLEEP;
  73. return crypto_ahash_init(&rctx->fallback_req);
  74. }
  75. static int rk_ahash_update(struct ahash_request *req)
  76. {
  77. struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
  78. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  79. struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  80. ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
  81. rctx->fallback_req.base.flags = req->base.flags &
  82. CRYPTO_TFM_REQ_MAY_SLEEP;
  83. rctx->fallback_req.nbytes = req->nbytes;
  84. rctx->fallback_req.src = req->src;
  85. return crypto_ahash_update(&rctx->fallback_req);
  86. }
  87. static int rk_ahash_final(struct ahash_request *req)
  88. {
  89. struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
  90. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  91. struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  92. ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
  93. rctx->fallback_req.base.flags = req->base.flags &
  94. CRYPTO_TFM_REQ_MAY_SLEEP;
  95. rctx->fallback_req.result = req->result;
  96. return crypto_ahash_final(&rctx->fallback_req);
  97. }
  98. static int rk_ahash_finup(struct ahash_request *req)
  99. {
  100. struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
  101. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  102. struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  103. ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
  104. rctx->fallback_req.base.flags = req->base.flags &
  105. CRYPTO_TFM_REQ_MAY_SLEEP;
  106. rctx->fallback_req.nbytes = req->nbytes;
  107. rctx->fallback_req.src = req->src;
  108. rctx->fallback_req.result = req->result;
  109. return crypto_ahash_finup(&rctx->fallback_req);
  110. }
  111. static int rk_ahash_import(struct ahash_request *req, const void *in)
  112. {
  113. struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
  114. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  115. struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  116. ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
  117. rctx->fallback_req.base.flags = req->base.flags &
  118. CRYPTO_TFM_REQ_MAY_SLEEP;
  119. return crypto_ahash_import(&rctx->fallback_req, in);
  120. }
  121. static int rk_ahash_export(struct ahash_request *req, void *out)
  122. {
  123. struct rk_ahash_rctx *rctx = ahash_request_ctx(req);
  124. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  125. struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  126. ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
  127. rctx->fallback_req.base.flags = req->base.flags &
  128. CRYPTO_TFM_REQ_MAY_SLEEP;
  129. return crypto_ahash_export(&rctx->fallback_req, out);
  130. }
  131. static int rk_ahash_digest(struct ahash_request *req)
  132. {
  133. struct rk_ahash_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
  134. struct rk_crypto_info *dev = tctx->dev;
  135. if (!req->nbytes)
  136. return zero_message_process(req);
  137. else
  138. return dev->enqueue(dev, &req->base);
  139. }
  140. static void crypto_ahash_dma_start(struct rk_crypto_info *dev)
  141. {
  142. CRYPTO_WRITE(dev, RK_CRYPTO_HRDMAS, dev->addr_in);
  143. CRYPTO_WRITE(dev, RK_CRYPTO_HRDMAL, (dev->count + 3) / 4);
  144. CRYPTO_WRITE(dev, RK_CRYPTO_CTRL, RK_CRYPTO_HASH_START |
  145. (RK_CRYPTO_HASH_START << 16));
  146. }
  147. static int rk_ahash_set_data_start(struct rk_crypto_info *dev)
  148. {
  149. int err;
  150. err = dev->load_data(dev, dev->sg_src, NULL);
  151. if (!err)
  152. crypto_ahash_dma_start(dev);
  153. return err;
  154. }
  155. static int rk_ahash_start(struct rk_crypto_info *dev)
  156. {
  157. struct ahash_request *req = ahash_request_cast(dev->async_req);
  158. struct crypto_ahash *tfm;
  159. struct rk_ahash_rctx *rctx;
  160. dev->total = req->nbytes;
  161. dev->left_bytes = req->nbytes;
  162. dev->aligned = 0;
  163. dev->align_size = 4;
  164. dev->sg_dst = NULL;
  165. dev->sg_src = req->src;
  166. dev->first = req->src;
  167. dev->src_nents = sg_nents(req->src);
  168. rctx = ahash_request_ctx(req);
  169. rctx->mode = 0;
  170. tfm = crypto_ahash_reqtfm(req);
  171. switch (crypto_ahash_digestsize(tfm)) {
  172. case SHA1_DIGEST_SIZE:
  173. rctx->mode = RK_CRYPTO_HASH_SHA1;
  174. break;
  175. case SHA256_DIGEST_SIZE:
  176. rctx->mode = RK_CRYPTO_HASH_SHA256;
  177. break;
  178. case MD5_DIGEST_SIZE:
  179. rctx->mode = RK_CRYPTO_HASH_MD5;
  180. break;
  181. default:
  182. return -EINVAL;
  183. }
  184. rk_ahash_reg_init(dev);
  185. return rk_ahash_set_data_start(dev);
  186. }
  187. static int rk_ahash_crypto_rx(struct rk_crypto_info *dev)
  188. {
  189. int err = 0;
  190. struct ahash_request *req = ahash_request_cast(dev->async_req);
  191. struct crypto_ahash *tfm;
  192. dev->unload_data(dev);
  193. if (dev->left_bytes) {
  194. if (dev->aligned) {
  195. if (sg_is_last(dev->sg_src)) {
  196. dev_warn(dev->dev, "[%s:%d], Lack of data\n",
  197. __func__, __LINE__);
  198. err = -ENOMEM;
  199. goto out_rx;
  200. }
  201. dev->sg_src = sg_next(dev->sg_src);
  202. }
  203. err = rk_ahash_set_data_start(dev);
  204. } else {
  205. /*
  206. * it will take some time to process date after last dma
  207. * transmission.
  208. *
  209. * waiting time is relative with the last date len,
  210. * so cannot set a fixed time here.
  211. * 10us makes system not call here frequently wasting
  212. * efficiency, and make it response quickly when dma
  213. * complete.
  214. */
  215. while (!CRYPTO_READ(dev, RK_CRYPTO_HASH_STS))
  216. udelay(10);
  217. tfm = crypto_ahash_reqtfm(req);
  218. memcpy_fromio(req->result, dev->reg + RK_CRYPTO_HASH_DOUT_0,
  219. crypto_ahash_digestsize(tfm));
  220. dev->complete(dev->async_req, 0);
  221. tasklet_schedule(&dev->queue_task);
  222. }
  223. out_rx:
  224. return err;
  225. }
  226. static int rk_cra_hash_init(struct crypto_tfm *tfm)
  227. {
  228. struct rk_ahash_ctx *tctx = crypto_tfm_ctx(tfm);
  229. struct rk_crypto_tmp *algt;
  230. struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg);
  231. const char *alg_name = crypto_tfm_alg_name(tfm);
  232. algt = container_of(alg, struct rk_crypto_tmp, alg.hash);
  233. tctx->dev = algt->dev;
  234. tctx->dev->addr_vir = (void *)__get_free_page(GFP_KERNEL);
  235. if (!tctx->dev->addr_vir) {
  236. dev_err(tctx->dev->dev, "failed to kmalloc for addr_vir\n");
  237. return -ENOMEM;
  238. }
  239. tctx->dev->start = rk_ahash_start;
  240. tctx->dev->update = rk_ahash_crypto_rx;
  241. tctx->dev->complete = rk_ahash_crypto_complete;
  242. /* for fallback */
  243. tctx->fallback_tfm = crypto_alloc_ahash(alg_name, 0,
  244. CRYPTO_ALG_NEED_FALLBACK);
  245. if (IS_ERR(tctx->fallback_tfm)) {
  246. dev_err(tctx->dev->dev, "Could not load fallback driver.\n");
  247. return PTR_ERR(tctx->fallback_tfm);
  248. }
  249. crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
  250. sizeof(struct rk_ahash_rctx) +
  251. crypto_ahash_reqsize(tctx->fallback_tfm));
  252. return tctx->dev->enable_clk(tctx->dev);
  253. }
  254. static void rk_cra_hash_exit(struct crypto_tfm *tfm)
  255. {
  256. struct rk_ahash_ctx *tctx = crypto_tfm_ctx(tfm);
  257. free_page((unsigned long)tctx->dev->addr_vir);
  258. return tctx->dev->disable_clk(tctx->dev);
  259. }
  260. struct rk_crypto_tmp rk_ahash_sha1 = {
  261. .type = ALG_TYPE_HASH,
  262. .alg.hash = {
  263. .init = rk_ahash_init,
  264. .update = rk_ahash_update,
  265. .final = rk_ahash_final,
  266. .finup = rk_ahash_finup,
  267. .export = rk_ahash_export,
  268. .import = rk_ahash_import,
  269. .digest = rk_ahash_digest,
  270. .halg = {
  271. .digestsize = SHA1_DIGEST_SIZE,
  272. .statesize = sizeof(struct sha1_state),
  273. .base = {
  274. .cra_name = "sha1",
  275. .cra_driver_name = "rk-sha1",
  276. .cra_priority = 300,
  277. .cra_flags = CRYPTO_ALG_ASYNC |
  278. CRYPTO_ALG_NEED_FALLBACK,
  279. .cra_blocksize = SHA1_BLOCK_SIZE,
  280. .cra_ctxsize = sizeof(struct rk_ahash_ctx),
  281. .cra_alignmask = 3,
  282. .cra_init = rk_cra_hash_init,
  283. .cra_exit = rk_cra_hash_exit,
  284. .cra_module = THIS_MODULE,
  285. }
  286. }
  287. }
  288. };
  289. struct rk_crypto_tmp rk_ahash_sha256 = {
  290. .type = ALG_TYPE_HASH,
  291. .alg.hash = {
  292. .init = rk_ahash_init,
  293. .update = rk_ahash_update,
  294. .final = rk_ahash_final,
  295. .finup = rk_ahash_finup,
  296. .export = rk_ahash_export,
  297. .import = rk_ahash_import,
  298. .digest = rk_ahash_digest,
  299. .halg = {
  300. .digestsize = SHA256_DIGEST_SIZE,
  301. .statesize = sizeof(struct sha256_state),
  302. .base = {
  303. .cra_name = "sha256",
  304. .cra_driver_name = "rk-sha256",
  305. .cra_priority = 300,
  306. .cra_flags = CRYPTO_ALG_ASYNC |
  307. CRYPTO_ALG_NEED_FALLBACK,
  308. .cra_blocksize = SHA256_BLOCK_SIZE,
  309. .cra_ctxsize = sizeof(struct rk_ahash_ctx),
  310. .cra_alignmask = 3,
  311. .cra_init = rk_cra_hash_init,
  312. .cra_exit = rk_cra_hash_exit,
  313. .cra_module = THIS_MODULE,
  314. }
  315. }
  316. }
  317. };
  318. struct rk_crypto_tmp rk_ahash_md5 = {
  319. .type = ALG_TYPE_HASH,
  320. .alg.hash = {
  321. .init = rk_ahash_init,
  322. .update = rk_ahash_update,
  323. .final = rk_ahash_final,
  324. .finup = rk_ahash_finup,
  325. .export = rk_ahash_export,
  326. .import = rk_ahash_import,
  327. .digest = rk_ahash_digest,
  328. .halg = {
  329. .digestsize = MD5_DIGEST_SIZE,
  330. .statesize = sizeof(struct md5_state),
  331. .base = {
  332. .cra_name = "md5",
  333. .cra_driver_name = "rk-md5",
  334. .cra_priority = 300,
  335. .cra_flags = CRYPTO_ALG_ASYNC |
  336. CRYPTO_ALG_NEED_FALLBACK,
  337. .cra_blocksize = SHA1_BLOCK_SIZE,
  338. .cra_ctxsize = sizeof(struct rk_ahash_ctx),
  339. .cra_alignmask = 3,
  340. .cra_init = rk_cra_hash_init,
  341. .cra_exit = rk_cra_hash_exit,
  342. .cra_module = THIS_MODULE,
  343. }
  344. }
  345. }
  346. };