sha.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/device.h>
  6. #include <linux/dma-mapping.h>
  7. #include <linux/interrupt.h>
  8. #include <crypto/internal/hash.h>
  9. #include "common.h"
  10. #include "core.h"
  11. #include "sha.h"
  12. /* crypto hw padding constant for first operation */
  13. #define SHA_PADDING 64
  14. #define SHA_PADDING_MASK (SHA_PADDING - 1)
  15. static LIST_HEAD(ahash_algs);
  16. static const u32 std_iv_sha1[SHA256_DIGEST_SIZE / sizeof(u32)] = {
  17. SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4, 0, 0, 0
  18. };
  19. static const u32 std_iv_sha256[SHA256_DIGEST_SIZE / sizeof(u32)] = {
  20. SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3,
  21. SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7
  22. };
  23. static void qce_ahash_done(void *data)
  24. {
  25. struct crypto_async_request *async_req = data;
  26. struct ahash_request *req = ahash_request_cast(async_req);
  27. struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
  28. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  29. struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
  30. struct qce_device *qce = tmpl->qce;
  31. struct qce_result_dump *result = qce->dma.result_buf;
  32. unsigned int digestsize = crypto_ahash_digestsize(ahash);
  33. int error;
  34. u32 status;
  35. error = qce_dma_terminate_all(&qce->dma);
  36. if (error)
  37. dev_dbg(qce->dev, "ahash dma termination error (%d)\n", error);
  38. dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
  39. dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
  40. memcpy(rctx->digest, result->auth_iv, digestsize);
  41. if (req->result)
  42. memcpy(req->result, result->auth_iv, digestsize);
  43. rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]);
  44. rctx->byte_count[1] = cpu_to_be32(result->auth_byte_count[1]);
  45. error = qce_check_status(qce, &status);
  46. if (error < 0)
  47. dev_dbg(qce->dev, "ahash operation error (%x)\n", status);
  48. req->src = rctx->src_orig;
  49. req->nbytes = rctx->nbytes_orig;
  50. rctx->last_blk = false;
  51. rctx->first_blk = false;
  52. qce->async_req_done(tmpl->qce, error);
  53. }
  54. static int qce_ahash_async_req_handle(struct crypto_async_request *async_req)
  55. {
  56. struct ahash_request *req = ahash_request_cast(async_req);
  57. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  58. struct qce_sha_ctx *ctx = crypto_tfm_ctx(async_req->tfm);
  59. struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
  60. struct qce_device *qce = tmpl->qce;
  61. unsigned long flags = rctx->flags;
  62. int ret;
  63. if (IS_SHA_HMAC(flags)) {
  64. rctx->authkey = ctx->authkey;
  65. rctx->authklen = QCE_SHA_HMAC_KEY_SIZE;
  66. } else if (IS_CMAC(flags)) {
  67. rctx->authkey = ctx->authkey;
  68. rctx->authklen = AES_KEYSIZE_128;
  69. }
  70. rctx->src_nents = sg_nents_for_len(req->src, req->nbytes);
  71. if (rctx->src_nents < 0) {
  72. dev_err(qce->dev, "Invalid numbers of src SG.\n");
  73. return rctx->src_nents;
  74. }
  75. ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
  76. if (ret < 0)
  77. return ret;
  78. sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
  79. ret = dma_map_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
  80. if (ret < 0)
  81. goto error_unmap_src;
  82. ret = qce_dma_prep_sgs(&qce->dma, req->src, rctx->src_nents,
  83. &rctx->result_sg, 1, qce_ahash_done, async_req);
  84. if (ret)
  85. goto error_unmap_dst;
  86. qce_dma_issue_pending(&qce->dma);
  87. ret = qce_start(async_req, tmpl->crypto_alg_type, 0, 0);
  88. if (ret)
  89. goto error_terminate;
  90. return 0;
  91. error_terminate:
  92. qce_dma_terminate_all(&qce->dma);
  93. error_unmap_dst:
  94. dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
  95. error_unmap_src:
  96. dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
  97. return ret;
  98. }
  99. static int qce_ahash_init(struct ahash_request *req)
  100. {
  101. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  102. struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
  103. const u32 *std_iv = tmpl->std_iv;
  104. memset(rctx, 0, sizeof(*rctx));
  105. rctx->first_blk = true;
  106. rctx->last_blk = false;
  107. rctx->flags = tmpl->alg_flags;
  108. memcpy(rctx->digest, std_iv, sizeof(rctx->digest));
  109. return 0;
  110. }
  111. static int qce_ahash_export(struct ahash_request *req, void *out)
  112. {
  113. struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
  114. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  115. unsigned long flags = rctx->flags;
  116. unsigned int digestsize = crypto_ahash_digestsize(ahash);
  117. unsigned int blocksize =
  118. crypto_tfm_alg_blocksize(crypto_ahash_tfm(ahash));
  119. if (IS_SHA1(flags) || IS_SHA1_HMAC(flags)) {
  120. struct sha1_state *out_state = out;
  121. out_state->count = rctx->count;
  122. qce_cpu_to_be32p_array((__be32 *)out_state->state,
  123. rctx->digest, digestsize);
  124. memcpy(out_state->buffer, rctx->buf, blocksize);
  125. } else if (IS_SHA256(flags) || IS_SHA256_HMAC(flags)) {
  126. struct sha256_state *out_state = out;
  127. out_state->count = rctx->count;
  128. qce_cpu_to_be32p_array((__be32 *)out_state->state,
  129. rctx->digest, digestsize);
  130. memcpy(out_state->buf, rctx->buf, blocksize);
  131. } else {
  132. return -EINVAL;
  133. }
  134. return 0;
  135. }
  136. static int qce_import_common(struct ahash_request *req, u64 in_count,
  137. const u32 *state, const u8 *buffer, bool hmac)
  138. {
  139. struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
  140. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  141. unsigned int digestsize = crypto_ahash_digestsize(ahash);
  142. unsigned int blocksize;
  143. u64 count = in_count;
  144. blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(ahash));
  145. rctx->count = in_count;
  146. memcpy(rctx->buf, buffer, blocksize);
  147. if (in_count <= blocksize) {
  148. rctx->first_blk = 1;
  149. } else {
  150. rctx->first_blk = 0;
  151. /*
  152. * For HMAC, there is a hardware padding done when first block
  153. * is set. Therefore the byte_count must be incremened by 64
  154. * after the first block operation.
  155. */
  156. if (hmac)
  157. count += SHA_PADDING;
  158. }
  159. rctx->byte_count[0] = (__force __be32)(count & ~SHA_PADDING_MASK);
  160. rctx->byte_count[1] = (__force __be32)(count >> 32);
  161. qce_cpu_to_be32p_array((__be32 *)rctx->digest, (const u8 *)state,
  162. digestsize);
  163. rctx->buflen = (unsigned int)(in_count & (blocksize - 1));
  164. return 0;
  165. }
  166. static int qce_ahash_import(struct ahash_request *req, const void *in)
  167. {
  168. struct qce_sha_reqctx *rctx;
  169. unsigned long flags;
  170. bool hmac;
  171. int ret;
  172. ret = qce_ahash_init(req);
  173. if (ret)
  174. return ret;
  175. rctx = ahash_request_ctx(req);
  176. flags = rctx->flags;
  177. hmac = IS_SHA_HMAC(flags);
  178. if (IS_SHA1(flags) || IS_SHA1_HMAC(flags)) {
  179. const struct sha1_state *state = in;
  180. ret = qce_import_common(req, state->count, state->state,
  181. state->buffer, hmac);
  182. } else if (IS_SHA256(flags) || IS_SHA256_HMAC(flags)) {
  183. const struct sha256_state *state = in;
  184. ret = qce_import_common(req, state->count, state->state,
  185. state->buf, hmac);
  186. }
  187. return ret;
  188. }
  189. static int qce_ahash_update(struct ahash_request *req)
  190. {
  191. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  192. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  193. struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
  194. struct qce_device *qce = tmpl->qce;
  195. struct scatterlist *sg_last, *sg;
  196. unsigned int total, len;
  197. unsigned int hash_later;
  198. unsigned int nbytes;
  199. unsigned int blocksize;
  200. blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
  201. rctx->count += req->nbytes;
  202. /* check for buffer from previous updates and append it */
  203. total = req->nbytes + rctx->buflen;
  204. if (total <= blocksize) {
  205. scatterwalk_map_and_copy(rctx->buf + rctx->buflen, req->src,
  206. 0, req->nbytes, 0);
  207. rctx->buflen += req->nbytes;
  208. return 0;
  209. }
  210. /* save the original req structure fields */
  211. rctx->src_orig = req->src;
  212. rctx->nbytes_orig = req->nbytes;
  213. /*
  214. * if we have data from previous update copy them on buffer. The old
  215. * data will be combined with current request bytes.
  216. */
  217. if (rctx->buflen)
  218. memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen);
  219. /* calculate how many bytes will be hashed later */
  220. hash_later = total % blocksize;
  221. if (hash_later) {
  222. unsigned int src_offset = req->nbytes - hash_later;
  223. scatterwalk_map_and_copy(rctx->buf, req->src, src_offset,
  224. hash_later, 0);
  225. }
  226. /* here nbytes is multiple of blocksize */
  227. nbytes = total - hash_later;
  228. len = rctx->buflen;
  229. sg = sg_last = req->src;
  230. while (len < nbytes && sg) {
  231. if (len + sg_dma_len(sg) > nbytes)
  232. break;
  233. len += sg_dma_len(sg);
  234. sg_last = sg;
  235. sg = sg_next(sg);
  236. }
  237. if (!sg_last)
  238. return -EINVAL;
  239. if (rctx->buflen) {
  240. sg_init_table(rctx->sg, 2);
  241. sg_set_buf(rctx->sg, rctx->tmpbuf, rctx->buflen);
  242. sg_chain(rctx->sg, 2, req->src);
  243. req->src = rctx->sg;
  244. }
  245. req->nbytes = nbytes;
  246. rctx->buflen = hash_later;
  247. return qce->async_req_enqueue(tmpl->qce, &req->base);
  248. }
  249. static int qce_ahash_final(struct ahash_request *req)
  250. {
  251. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  252. struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
  253. struct qce_device *qce = tmpl->qce;
  254. if (!rctx->buflen) {
  255. if (tmpl->hash_zero)
  256. memcpy(req->result, tmpl->hash_zero,
  257. tmpl->alg.ahash.halg.digestsize);
  258. return 0;
  259. }
  260. rctx->last_blk = true;
  261. rctx->src_orig = req->src;
  262. rctx->nbytes_orig = req->nbytes;
  263. memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen);
  264. sg_init_one(rctx->sg, rctx->tmpbuf, rctx->buflen);
  265. req->src = rctx->sg;
  266. req->nbytes = rctx->buflen;
  267. return qce->async_req_enqueue(tmpl->qce, &req->base);
  268. }
  269. static int qce_ahash_digest(struct ahash_request *req)
  270. {
  271. struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  272. struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
  273. struct qce_device *qce = tmpl->qce;
  274. int ret;
  275. ret = qce_ahash_init(req);
  276. if (ret)
  277. return ret;
  278. rctx->src_orig = req->src;
  279. rctx->nbytes_orig = req->nbytes;
  280. rctx->first_blk = true;
  281. rctx->last_blk = true;
  282. if (!rctx->nbytes_orig) {
  283. if (tmpl->hash_zero)
  284. memcpy(req->result, tmpl->hash_zero,
  285. tmpl->alg.ahash.halg.digestsize);
  286. return 0;
  287. }
  288. return qce->async_req_enqueue(tmpl->qce, &req->base);
  289. }
  290. static int qce_ahash_hmac_setkey(struct crypto_ahash *tfm, const u8 *key,
  291. unsigned int keylen)
  292. {
  293. unsigned int digestsize = crypto_ahash_digestsize(tfm);
  294. struct qce_sha_ctx *ctx = crypto_tfm_ctx(&tfm->base);
  295. struct crypto_wait wait;
  296. struct ahash_request *req;
  297. struct scatterlist sg;
  298. unsigned int blocksize;
  299. struct crypto_ahash *ahash_tfm;
  300. u8 *buf;
  301. int ret;
  302. const char *alg_name;
  303. blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
  304. memset(ctx->authkey, 0, sizeof(ctx->authkey));
  305. if (keylen <= blocksize) {
  306. memcpy(ctx->authkey, key, keylen);
  307. return 0;
  308. }
  309. if (digestsize == SHA1_DIGEST_SIZE)
  310. alg_name = "sha1-qce";
  311. else if (digestsize == SHA256_DIGEST_SIZE)
  312. alg_name = "sha256-qce";
  313. else
  314. return -EINVAL;
  315. ahash_tfm = crypto_alloc_ahash(alg_name, 0, 0);
  316. if (IS_ERR(ahash_tfm))
  317. return PTR_ERR(ahash_tfm);
  318. req = ahash_request_alloc(ahash_tfm, GFP_KERNEL);
  319. if (!req) {
  320. ret = -ENOMEM;
  321. goto err_free_ahash;
  322. }
  323. crypto_init_wait(&wait);
  324. ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
  325. crypto_req_done, &wait);
  326. crypto_ahash_clear_flags(ahash_tfm, ~0);
  327. buf = kzalloc(keylen + QCE_MAX_ALIGN_SIZE, GFP_KERNEL);
  328. if (!buf) {
  329. ret = -ENOMEM;
  330. goto err_free_req;
  331. }
  332. memcpy(buf, key, keylen);
  333. sg_init_one(&sg, buf, keylen);
  334. ahash_request_set_crypt(req, &sg, ctx->authkey, keylen);
  335. ret = crypto_wait_req(crypto_ahash_digest(req), &wait);
  336. kfree(buf);
  337. err_free_req:
  338. ahash_request_free(req);
  339. err_free_ahash:
  340. crypto_free_ahash(ahash_tfm);
  341. return ret;
  342. }
  343. static int qce_ahash_cra_init(struct crypto_tfm *tfm)
  344. {
  345. struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
  346. struct qce_sha_ctx *ctx = crypto_tfm_ctx(tfm);
  347. crypto_ahash_set_reqsize(ahash, sizeof(struct qce_sha_reqctx));
  348. memset(ctx, 0, sizeof(*ctx));
  349. return 0;
  350. }
  351. struct qce_ahash_def {
  352. unsigned long flags;
  353. const char *name;
  354. const char *drv_name;
  355. unsigned int digestsize;
  356. unsigned int blocksize;
  357. unsigned int statesize;
  358. const u32 *std_iv;
  359. };
  360. static const struct qce_ahash_def ahash_def[] = {
  361. {
  362. .flags = QCE_HASH_SHA1,
  363. .name = "sha1",
  364. .drv_name = "sha1-qce",
  365. .digestsize = SHA1_DIGEST_SIZE,
  366. .blocksize = SHA1_BLOCK_SIZE,
  367. .statesize = sizeof(struct sha1_state),
  368. .std_iv = std_iv_sha1,
  369. },
  370. {
  371. .flags = QCE_HASH_SHA256,
  372. .name = "sha256",
  373. .drv_name = "sha256-qce",
  374. .digestsize = SHA256_DIGEST_SIZE,
  375. .blocksize = SHA256_BLOCK_SIZE,
  376. .statesize = sizeof(struct sha256_state),
  377. .std_iv = std_iv_sha256,
  378. },
  379. {
  380. .flags = QCE_HASH_SHA1_HMAC,
  381. .name = "hmac(sha1)",
  382. .drv_name = "hmac-sha1-qce",
  383. .digestsize = SHA1_DIGEST_SIZE,
  384. .blocksize = SHA1_BLOCK_SIZE,
  385. .statesize = sizeof(struct sha1_state),
  386. .std_iv = std_iv_sha1,
  387. },
  388. {
  389. .flags = QCE_HASH_SHA256_HMAC,
  390. .name = "hmac(sha256)",
  391. .drv_name = "hmac-sha256-qce",
  392. .digestsize = SHA256_DIGEST_SIZE,
  393. .blocksize = SHA256_BLOCK_SIZE,
  394. .statesize = sizeof(struct sha256_state),
  395. .std_iv = std_iv_sha256,
  396. },
  397. };
  398. static int qce_ahash_register_one(const struct qce_ahash_def *def,
  399. struct qce_device *qce)
  400. {
  401. struct qce_alg_template *tmpl;
  402. struct ahash_alg *alg;
  403. struct crypto_alg *base;
  404. int ret;
  405. tmpl = kzalloc(sizeof(*tmpl), GFP_KERNEL);
  406. if (!tmpl)
  407. return -ENOMEM;
  408. tmpl->std_iv = def->std_iv;
  409. alg = &tmpl->alg.ahash;
  410. alg->init = qce_ahash_init;
  411. alg->update = qce_ahash_update;
  412. alg->final = qce_ahash_final;
  413. alg->digest = qce_ahash_digest;
  414. alg->export = qce_ahash_export;
  415. alg->import = qce_ahash_import;
  416. if (IS_SHA_HMAC(def->flags))
  417. alg->setkey = qce_ahash_hmac_setkey;
  418. alg->halg.digestsize = def->digestsize;
  419. alg->halg.statesize = def->statesize;
  420. if (IS_SHA1(def->flags))
  421. tmpl->hash_zero = sha1_zero_message_hash;
  422. else if (IS_SHA256(def->flags))
  423. tmpl->hash_zero = sha256_zero_message_hash;
  424. base = &alg->halg.base;
  425. base->cra_blocksize = def->blocksize;
  426. base->cra_priority = 300;
  427. base->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
  428. base->cra_ctxsize = sizeof(struct qce_sha_ctx);
  429. base->cra_alignmask = 0;
  430. base->cra_module = THIS_MODULE;
  431. base->cra_init = qce_ahash_cra_init;
  432. snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name);
  433. snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
  434. def->drv_name);
  435. INIT_LIST_HEAD(&tmpl->entry);
  436. tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_AHASH;
  437. tmpl->alg_flags = def->flags;
  438. tmpl->qce = qce;
  439. ret = crypto_register_ahash(alg);
  440. if (ret) {
  441. dev_err(qce->dev, "%s registration failed\n", base->cra_name);
  442. kfree(tmpl);
  443. return ret;
  444. }
  445. list_add_tail(&tmpl->entry, &ahash_algs);
  446. dev_dbg(qce->dev, "%s is registered\n", base->cra_name);
  447. return 0;
  448. }
  449. static void qce_ahash_unregister(struct qce_device *qce)
  450. {
  451. struct qce_alg_template *tmpl, *n;
  452. list_for_each_entry_safe(tmpl, n, &ahash_algs, entry) {
  453. crypto_unregister_ahash(&tmpl->alg.ahash);
  454. list_del(&tmpl->entry);
  455. kfree(tmpl);
  456. }
  457. }
  458. static int qce_ahash_register(struct qce_device *qce)
  459. {
  460. int ret, i;
  461. for (i = 0; i < ARRAY_SIZE(ahash_def); i++) {
  462. ret = qce_ahash_register_one(&ahash_def[i], qce);
  463. if (ret)
  464. goto err;
  465. }
  466. return 0;
  467. err:
  468. qce_ahash_unregister(qce);
  469. return ret;
  470. }
  471. const struct qce_algo_ops ahash_ops = {
  472. .type = CRYPTO_ALG_TYPE_AHASH,
  473. .register_algs = qce_ahash_register,
  474. .unregister_algs = qce_ahash_unregister,
  475. .async_req_handle = qce_ahash_async_req_handle,
  476. };