regs-v5.h 9.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _REGS_V5_H_
  6. #define _REGS_V5_H_
  7. #include <linux/bitops.h>
  8. #define REG_VERSION 0x000
  9. #define REG_STATUS 0x100
  10. #define REG_STATUS2 0x104
  11. #define REG_ENGINES_AVAIL 0x108
  12. #define REG_FIFO_SIZES 0x10c
  13. #define REG_SEG_SIZE 0x110
  14. #define REG_GOPROC 0x120
  15. #define REG_ENCR_SEG_CFG 0x200
  16. #define REG_ENCR_SEG_SIZE 0x204
  17. #define REG_ENCR_SEG_START 0x208
  18. #define REG_CNTR0_IV0 0x20c
  19. #define REG_CNTR1_IV1 0x210
  20. #define REG_CNTR2_IV2 0x214
  21. #define REG_CNTR3_IV3 0x218
  22. #define REG_CNTR_MASK 0x21C
  23. #define REG_ENCR_CCM_INT_CNTR0 0x220
  24. #define REG_ENCR_CCM_INT_CNTR1 0x224
  25. #define REG_ENCR_CCM_INT_CNTR2 0x228
  26. #define REG_ENCR_CCM_INT_CNTR3 0x22c
  27. #define REG_ENCR_XTS_DU_SIZE 0x230
  28. #define REG_CNTR_MASK2 0x234
  29. #define REG_CNTR_MASK1 0x238
  30. #define REG_CNTR_MASK0 0x23c
  31. #define REG_AUTH_SEG_CFG 0x300
  32. #define REG_AUTH_SEG_SIZE 0x304
  33. #define REG_AUTH_SEG_START 0x308
  34. #define REG_AUTH_IV0 0x310
  35. #define REG_AUTH_IV1 0x314
  36. #define REG_AUTH_IV2 0x318
  37. #define REG_AUTH_IV3 0x31c
  38. #define REG_AUTH_IV4 0x320
  39. #define REG_AUTH_IV5 0x324
  40. #define REG_AUTH_IV6 0x328
  41. #define REG_AUTH_IV7 0x32c
  42. #define REG_AUTH_IV8 0x330
  43. #define REG_AUTH_IV9 0x334
  44. #define REG_AUTH_IV10 0x338
  45. #define REG_AUTH_IV11 0x33c
  46. #define REG_AUTH_IV12 0x340
  47. #define REG_AUTH_IV13 0x344
  48. #define REG_AUTH_IV14 0x348
  49. #define REG_AUTH_IV15 0x34c
  50. #define REG_AUTH_INFO_NONCE0 0x350
  51. #define REG_AUTH_INFO_NONCE1 0x354
  52. #define REG_AUTH_INFO_NONCE2 0x358
  53. #define REG_AUTH_INFO_NONCE3 0x35c
  54. #define REG_AUTH_BYTECNT0 0x390
  55. #define REG_AUTH_BYTECNT1 0x394
  56. #define REG_AUTH_BYTECNT2 0x398
  57. #define REG_AUTH_BYTECNT3 0x39c
  58. #define REG_AUTH_EXP_MAC0 0x3a0
  59. #define REG_AUTH_EXP_MAC1 0x3a4
  60. #define REG_AUTH_EXP_MAC2 0x3a8
  61. #define REG_AUTH_EXP_MAC3 0x3ac
  62. #define REG_AUTH_EXP_MAC4 0x3b0
  63. #define REG_AUTH_EXP_MAC5 0x3b4
  64. #define REG_AUTH_EXP_MAC6 0x3b8
  65. #define REG_AUTH_EXP_MAC7 0x3bc
  66. #define REG_CONFIG 0x400
  67. #define REG_GOPROC_QC_KEY 0x1000
  68. #define REG_GOPROC_OEM_KEY 0x2000
  69. #define REG_ENCR_KEY0 0x3000
  70. #define REG_ENCR_KEY1 0x3004
  71. #define REG_ENCR_KEY2 0x3008
  72. #define REG_ENCR_KEY3 0x300c
  73. #define REG_ENCR_KEY4 0x3010
  74. #define REG_ENCR_KEY5 0x3014
  75. #define REG_ENCR_KEY6 0x3018
  76. #define REG_ENCR_KEY7 0x301c
  77. #define REG_ENCR_XTS_KEY0 0x3020
  78. #define REG_ENCR_XTS_KEY1 0x3024
  79. #define REG_ENCR_XTS_KEY2 0x3028
  80. #define REG_ENCR_XTS_KEY3 0x302c
  81. #define REG_ENCR_XTS_KEY4 0x3030
  82. #define REG_ENCR_XTS_KEY5 0x3034
  83. #define REG_ENCR_XTS_KEY6 0x3038
  84. #define REG_ENCR_XTS_KEY7 0x303c
  85. #define REG_AUTH_KEY0 0x3040
  86. #define REG_AUTH_KEY1 0x3044
  87. #define REG_AUTH_KEY2 0x3048
  88. #define REG_AUTH_KEY3 0x304c
  89. #define REG_AUTH_KEY4 0x3050
  90. #define REG_AUTH_KEY5 0x3054
  91. #define REG_AUTH_KEY6 0x3058
  92. #define REG_AUTH_KEY7 0x305c
  93. #define REG_AUTH_KEY8 0x3060
  94. #define REG_AUTH_KEY9 0x3064
  95. #define REG_AUTH_KEY10 0x3068
  96. #define REG_AUTH_KEY11 0x306c
  97. #define REG_AUTH_KEY12 0x3070
  98. #define REG_AUTH_KEY13 0x3074
  99. #define REG_AUTH_KEY14 0x3078
  100. #define REG_AUTH_KEY15 0x307c
  101. /* Register bits - REG_VERSION */
  102. #define CORE_STEP_REV_SHIFT 0
  103. #define CORE_STEP_REV_MASK GENMASK(15, 0)
  104. #define CORE_MINOR_REV_SHIFT 16
  105. #define CORE_MINOR_REV_MASK GENMASK(23, 16)
  106. #define CORE_MAJOR_REV_SHIFT 24
  107. #define CORE_MAJOR_REV_MASK GENMASK(31, 24)
  108. /* Register bits - REG_STATUS */
  109. #define MAC_FAILED_SHIFT 31
  110. #define DOUT_SIZE_AVAIL_SHIFT 26
  111. #define DOUT_SIZE_AVAIL_MASK GENMASK(30, 26)
  112. #define DIN_SIZE_AVAIL_SHIFT 21
  113. #define DIN_SIZE_AVAIL_MASK GENMASK(25, 21)
  114. #define HSD_ERR_SHIFT 20
  115. #define ACCESS_VIOL_SHIFT 19
  116. #define PIPE_ACTIVE_ERR_SHIFT 18
  117. #define CFG_CHNG_ERR_SHIFT 17
  118. #define DOUT_ERR_SHIFT 16
  119. #define DIN_ERR_SHIFT 15
  120. #define AXI_ERR_SHIFT 14
  121. #define CRYPTO_STATE_SHIFT 10
  122. #define CRYPTO_STATE_MASK GENMASK(13, 10)
  123. #define ENCR_BUSY_SHIFT 9
  124. #define AUTH_BUSY_SHIFT 8
  125. #define DOUT_INTR_SHIFT 7
  126. #define DIN_INTR_SHIFT 6
  127. #define OP_DONE_INTR_SHIFT 5
  128. #define ERR_INTR_SHIFT 4
  129. #define DOUT_RDY_SHIFT 3
  130. #define DIN_RDY_SHIFT 2
  131. #define OPERATION_DONE_SHIFT 1
  132. #define SW_ERR_SHIFT 0
  133. /* Register bits - REG_STATUS2 */
  134. #define AXI_EXTRA_SHIFT 1
  135. #define LOCKED_SHIFT 2
  136. /* Register bits - REG_CONFIG */
  137. #define REQ_SIZE_SHIFT 17
  138. #define REQ_SIZE_MASK GENMASK(20, 17)
  139. #define REQ_SIZE_ENUM_1_BEAT 0
  140. #define REQ_SIZE_ENUM_2_BEAT 1
  141. #define REQ_SIZE_ENUM_3_BEAT 2
  142. #define REQ_SIZE_ENUM_4_BEAT 3
  143. #define REQ_SIZE_ENUM_5_BEAT 4
  144. #define REQ_SIZE_ENUM_6_BEAT 5
  145. #define REQ_SIZE_ENUM_7_BEAT 6
  146. #define REQ_SIZE_ENUM_8_BEAT 7
  147. #define REQ_SIZE_ENUM_9_BEAT 8
  148. #define REQ_SIZE_ENUM_10_BEAT 9
  149. #define REQ_SIZE_ENUM_11_BEAT 10
  150. #define REQ_SIZE_ENUM_12_BEAT 11
  151. #define REQ_SIZE_ENUM_13_BEAT 12
  152. #define REQ_SIZE_ENUM_14_BEAT 13
  153. #define REQ_SIZE_ENUM_15_BEAT 14
  154. #define REQ_SIZE_ENUM_16_BEAT 15
  155. #define MAX_QUEUED_REQ_SHIFT 14
  156. #define MAX_QUEUED_REQ_MASK GENMASK(24, 16)
  157. #define ENUM_1_QUEUED_REQS 0
  158. #define ENUM_2_QUEUED_REQS 1
  159. #define ENUM_3_QUEUED_REQS 2
  160. #define IRQ_ENABLES_SHIFT 10
  161. #define IRQ_ENABLES_MASK GENMASK(13, 10)
  162. #define LITTLE_ENDIAN_MODE_SHIFT 9
  163. #define PIPE_SET_SELECT_SHIFT 5
  164. #define PIPE_SET_SELECT_MASK GENMASK(8, 5)
  165. #define HIGH_SPD_EN_N_SHIFT 4
  166. #define MASK_DOUT_INTR_SHIFT 3
  167. #define MASK_DIN_INTR_SHIFT 2
  168. #define MASK_OP_DONE_INTR_SHIFT 1
  169. #define MASK_ERR_INTR_SHIFT 0
  170. /* Register bits - REG_AUTH_SEG_CFG */
  171. #define COMP_EXP_MAC_SHIFT 24
  172. #define COMP_EXP_MAC_DISABLED 0
  173. #define COMP_EXP_MAC_ENABLED 1
  174. #define F9_DIRECTION_SHIFT 23
  175. #define F9_DIRECTION_UPLINK 0
  176. #define F9_DIRECTION_DOWNLINK 1
  177. #define AUTH_NONCE_NUM_WORDS_SHIFT 20
  178. #define AUTH_NONCE_NUM_WORDS_MASK GENMASK(22, 20)
  179. #define USE_PIPE_KEY_AUTH_SHIFT 19
  180. #define USE_HW_KEY_AUTH_SHIFT 18
  181. #define AUTH_FIRST_SHIFT 17
  182. #define AUTH_LAST_SHIFT 16
  183. #define AUTH_POS_SHIFT 14
  184. #define AUTH_POS_MASK GENMASK(15, 14)
  185. #define AUTH_POS_BEFORE 0
  186. #define AUTH_POS_AFTER 1
  187. #define AUTH_SIZE_SHIFT 9
  188. #define AUTH_SIZE_MASK GENMASK(13, 9)
  189. #define AUTH_SIZE_SHA1 0
  190. #define AUTH_SIZE_SHA256 1
  191. #define AUTH_SIZE_ENUM_1_BYTES 0
  192. #define AUTH_SIZE_ENUM_2_BYTES 1
  193. #define AUTH_SIZE_ENUM_3_BYTES 2
  194. #define AUTH_SIZE_ENUM_4_BYTES 3
  195. #define AUTH_SIZE_ENUM_5_BYTES 4
  196. #define AUTH_SIZE_ENUM_6_BYTES 5
  197. #define AUTH_SIZE_ENUM_7_BYTES 6
  198. #define AUTH_SIZE_ENUM_8_BYTES 7
  199. #define AUTH_SIZE_ENUM_9_BYTES 8
  200. #define AUTH_SIZE_ENUM_10_BYTES 9
  201. #define AUTH_SIZE_ENUM_11_BYTES 10
  202. #define AUTH_SIZE_ENUM_12_BYTES 11
  203. #define AUTH_SIZE_ENUM_13_BYTES 12
  204. #define AUTH_SIZE_ENUM_14_BYTES 13
  205. #define AUTH_SIZE_ENUM_15_BYTES 14
  206. #define AUTH_SIZE_ENUM_16_BYTES 15
  207. #define AUTH_MODE_SHIFT 6
  208. #define AUTH_MODE_MASK GENMASK(8, 6)
  209. #define AUTH_MODE_HASH 0
  210. #define AUTH_MODE_HMAC 1
  211. #define AUTH_MODE_CCM 0
  212. #define AUTH_MODE_CMAC 1
  213. #define AUTH_KEY_SIZE_SHIFT 3
  214. #define AUTH_KEY_SIZE_MASK GENMASK(5, 3)
  215. #define AUTH_KEY_SZ_AES128 0
  216. #define AUTH_KEY_SZ_AES256 2
  217. #define AUTH_ALG_SHIFT 0
  218. #define AUTH_ALG_MASK GENMASK(2, 0)
  219. #define AUTH_ALG_NONE 0
  220. #define AUTH_ALG_SHA 1
  221. #define AUTH_ALG_AES 2
  222. #define AUTH_ALG_KASUMI 3
  223. #define AUTH_ALG_SNOW3G 4
  224. #define AUTH_ALG_ZUC 5
  225. /* Register bits - REG_ENCR_XTS_DU_SIZE */
  226. #define ENCR_XTS_DU_SIZE_SHIFT 0
  227. #define ENCR_XTS_DU_SIZE_MASK GENMASK(19, 0)
  228. /* Register bits - REG_ENCR_SEG_CFG */
  229. #define F8_KEYSTREAM_ENABLE_SHIFT 17
  230. #define F8_KEYSTREAM_DISABLED 0
  231. #define F8_KEYSTREAM_ENABLED 1
  232. #define F8_DIRECTION_SHIFT 16
  233. #define F8_DIRECTION_UPLINK 0
  234. #define F8_DIRECTION_DOWNLINK 1
  235. #define USE_PIPE_KEY_ENCR_SHIFT 15
  236. #define USE_PIPE_KEY_ENCR_ENABLED 1
  237. #define USE_KEY_REGISTERS 0
  238. #define USE_HW_KEY_ENCR_SHIFT 14
  239. #define USE_KEY_REG 0
  240. #define USE_HW_KEY 1
  241. #define LAST_CCM_SHIFT 13
  242. #define LAST_CCM_XFR 1
  243. #define INTERM_CCM_XFR 0
  244. #define CNTR_ALG_SHIFT 11
  245. #define CNTR_ALG_MASK GENMASK(12, 11)
  246. #define CNTR_ALG_NIST 0
  247. #define ENCODE_SHIFT 10
  248. #define ENCR_MODE_SHIFT 6
  249. #define ENCR_MODE_MASK GENMASK(9, 6)
  250. #define ENCR_MODE_ECB 0
  251. #define ENCR_MODE_CBC 1
  252. #define ENCR_MODE_CTR 2
  253. #define ENCR_MODE_XTS 3
  254. #define ENCR_MODE_CCM 4
  255. #define ENCR_KEY_SZ_SHIFT 3
  256. #define ENCR_KEY_SZ_MASK GENMASK(5, 3)
  257. #define ENCR_KEY_SZ_DES 0
  258. #define ENCR_KEY_SZ_3DES 1
  259. #define ENCR_KEY_SZ_AES128 0
  260. #define ENCR_KEY_SZ_AES256 2
  261. #define ENCR_ALG_SHIFT 0
  262. #define ENCR_ALG_MASK GENMASK(2, 0)
  263. #define ENCR_ALG_NONE 0
  264. #define ENCR_ALG_DES 1
  265. #define ENCR_ALG_AES 2
  266. #define ENCR_ALG_KASUMI 4
  267. #define ENCR_ALG_SNOW_3G 5
  268. #define ENCR_ALG_ZUC 6
  269. /* Register bits - REG_GOPROC */
  270. #define GO_SHIFT 0
  271. #define CLR_CNTXT_SHIFT 1
  272. #define RESULTS_DUMP_SHIFT 2
  273. /* Register bits - REG_ENGINES_AVAIL */
  274. #define ENCR_AES_SEL_SHIFT 0
  275. #define DES_SEL_SHIFT 1
  276. #define ENCR_SNOW3G_SEL_SHIFT 2
  277. #define ENCR_KASUMI_SEL_SHIFT 3
  278. #define SHA_SEL_SHIFT 4
  279. #define SHA512_SEL_SHIFT 5
  280. #define AUTH_AES_SEL_SHIFT 6
  281. #define AUTH_SNOW3G_SEL_SHIFT 7
  282. #define AUTH_KASUMI_SEL_SHIFT 8
  283. #define BAM_PIPE_SETS_SHIFT 9
  284. #define BAM_PIPE_SETS_MASK GENMASK(12, 9)
  285. #define AXI_WR_BEATS_SHIFT 13
  286. #define AXI_WR_BEATS_MASK GENMASK(18, 13)
  287. #define AXI_RD_BEATS_SHIFT 19
  288. #define AXI_RD_BEATS_MASK GENMASK(24, 19)
  289. #define ENCR_ZUC_SEL_SHIFT 26
  290. #define AUTH_ZUC_SEL_SHIFT 27
  291. #define ZUC_ENABLE_SHIFT 28
  292. #endif /* _REGS_V5_H_ */