mtk-platform.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for EIP97 cryptographic accelerator.
  4. *
  5. * Copyright (c) 2016 Ryder Lee <ryder.lee@mediatek.com>
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/init.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/mod_devicetable.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/pm_runtime.h>
  14. #include "mtk-platform.h"
  15. #define MTK_BURST_SIZE_MSK GENMASK(7, 4)
  16. #define MTK_BURST_SIZE(x) ((x) << 4)
  17. #define MTK_DESC_SIZE(x) ((x) << 0)
  18. #define MTK_DESC_OFFSET(x) ((x) << 16)
  19. #define MTK_DESC_FETCH_SIZE(x) ((x) << 0)
  20. #define MTK_DESC_FETCH_THRESH(x) ((x) << 16)
  21. #define MTK_DESC_OVL_IRQ_EN BIT(25)
  22. #define MTK_DESC_ATP_PRESENT BIT(30)
  23. #define MTK_DFSE_IDLE GENMASK(3, 0)
  24. #define MTK_DFSE_THR_CTRL_EN BIT(30)
  25. #define MTK_DFSE_THR_CTRL_RESET BIT(31)
  26. #define MTK_DFSE_RING_ID(x) (((x) >> 12) & GENMASK(3, 0))
  27. #define MTK_DFSE_MIN_DATA(x) ((x) << 0)
  28. #define MTK_DFSE_MAX_DATA(x) ((x) << 8)
  29. #define MTK_DFE_MIN_CTRL(x) ((x) << 16)
  30. #define MTK_DFE_MAX_CTRL(x) ((x) << 24)
  31. #define MTK_IN_BUF_MIN_THRESH(x) ((x) << 8)
  32. #define MTK_IN_BUF_MAX_THRESH(x) ((x) << 12)
  33. #define MTK_OUT_BUF_MIN_THRESH(x) ((x) << 0)
  34. #define MTK_OUT_BUF_MAX_THRESH(x) ((x) << 4)
  35. #define MTK_IN_TBUF_SIZE(x) (((x) >> 4) & GENMASK(3, 0))
  36. #define MTK_IN_DBUF_SIZE(x) (((x) >> 8) & GENMASK(3, 0))
  37. #define MTK_OUT_DBUF_SIZE(x) (((x) >> 16) & GENMASK(3, 0))
  38. #define MTK_CMD_FIFO_SIZE(x) (((x) >> 8) & GENMASK(3, 0))
  39. #define MTK_RES_FIFO_SIZE(x) (((x) >> 12) & GENMASK(3, 0))
  40. #define MTK_PE_TK_LOC_AVL BIT(2)
  41. #define MTK_PE_PROC_HELD BIT(14)
  42. #define MTK_PE_TK_TIMEOUT_EN BIT(22)
  43. #define MTK_PE_INPUT_DMA_ERR BIT(0)
  44. #define MTK_PE_OUTPUT_DMA_ERR BIT(1)
  45. #define MTK_PE_PKT_PORC_ERR BIT(2)
  46. #define MTK_PE_PKT_TIMEOUT BIT(3)
  47. #define MTK_PE_FATAL_ERR BIT(14)
  48. #define MTK_PE_INPUT_DMA_ERR_EN BIT(16)
  49. #define MTK_PE_OUTPUT_DMA_ERR_EN BIT(17)
  50. #define MTK_PE_PKT_PORC_ERR_EN BIT(18)
  51. #define MTK_PE_PKT_TIMEOUT_EN BIT(19)
  52. #define MTK_PE_FATAL_ERR_EN BIT(30)
  53. #define MTK_PE_INT_OUT_EN BIT(31)
  54. #define MTK_HIA_SIGNATURE ((u16)0x35ca)
  55. #define MTK_HIA_DATA_WIDTH(x) (((x) >> 25) & GENMASK(1, 0))
  56. #define MTK_HIA_DMA_LENGTH(x) (((x) >> 20) & GENMASK(4, 0))
  57. #define MTK_CDR_STAT_CLR GENMASK(4, 0)
  58. #define MTK_RDR_STAT_CLR GENMASK(7, 0)
  59. #define MTK_AIC_INT_MSK GENMASK(5, 0)
  60. #define MTK_AIC_VER_MSK (GENMASK(15, 0) | GENMASK(27, 20))
  61. #define MTK_AIC_VER11 0x011036c9
  62. #define MTK_AIC_VER12 0x012036c9
  63. #define MTK_AIC_G_CLR GENMASK(30, 20)
  64. /**
  65. * EIP97 is an integrated security subsystem to accelerate cryptographic
  66. * functions and protocols to offload the host processor.
  67. * Some important hardware modules are briefly introduced below:
  68. *
  69. * Host Interface Adapter(HIA) - the main interface between the host
  70. * system and the hardware subsystem. It is responsible for attaching
  71. * processing engine to the specific host bus interface and provides a
  72. * standardized software view for off loading tasks to the engine.
  73. *
  74. * Command Descriptor Ring Manager(CDR Manager) - keeps track of how many
  75. * CD the host has prepared in the CDR. It monitors the fill level of its
  76. * CD-FIFO and if there's sufficient space for the next block of descriptors,
  77. * then it fires off a DMA request to fetch a block of CDs.
  78. *
  79. * Data fetch engine(DFE) - It is responsible for parsing the CD and
  80. * setting up the required control and packet data DMA transfers from
  81. * system memory to the processing engine.
  82. *
  83. * Result Descriptor Ring Manager(RDR Manager) - same as CDR Manager,
  84. * but target is result descriptors, Moreover, it also handles the RD
  85. * updates under control of the DSE. For each packet data segment
  86. * processed, the DSE triggers the RDR Manager to write the updated RD.
  87. * If triggered to update, the RDR Manager sets up a DMA operation to
  88. * copy the RD from the DSE to the correct location in the RDR.
  89. *
  90. * Data Store Engine(DSE) - It is responsible for parsing the prepared RD
  91. * and setting up the required control and packet data DMA transfers from
  92. * the processing engine to system memory.
  93. *
  94. * Advanced Interrupt Controllers(AICs) - receive interrupt request signals
  95. * from various sources and combine them into one interrupt output.
  96. * The AICs are used by:
  97. * - One for the HIA global and processing engine interrupts.
  98. * - The others for the descriptor ring interrupts.
  99. */
  100. /* Cryptographic engine capabilities */
  101. struct mtk_sys_cap {
  102. /* host interface adapter */
  103. u32 hia_ver;
  104. u32 hia_opt;
  105. /* packet engine */
  106. u32 pkt_eng_opt;
  107. /* global hardware */
  108. u32 hw_opt;
  109. };
  110. static void mtk_desc_ring_link(struct mtk_cryp *cryp, u32 mask)
  111. {
  112. /* Assign rings to DFE/DSE thread and enable it */
  113. writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DFE_THR_CTRL);
  114. writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DSE_THR_CTRL);
  115. }
  116. static void mtk_dfe_dse_buf_setup(struct mtk_cryp *cryp,
  117. struct mtk_sys_cap *cap)
  118. {
  119. u32 width = MTK_HIA_DATA_WIDTH(cap->hia_opt) + 2;
  120. u32 len = MTK_HIA_DMA_LENGTH(cap->hia_opt) - 1;
  121. u32 ipbuf = min((u32)MTK_IN_DBUF_SIZE(cap->hw_opt) + width, len);
  122. u32 opbuf = min((u32)MTK_OUT_DBUF_SIZE(cap->hw_opt) + width, len);
  123. u32 itbuf = min((u32)MTK_IN_TBUF_SIZE(cap->hw_opt) + width, len);
  124. writel(MTK_DFSE_MIN_DATA(ipbuf - 1) |
  125. MTK_DFSE_MAX_DATA(ipbuf) |
  126. MTK_DFE_MIN_CTRL(itbuf - 1) |
  127. MTK_DFE_MAX_CTRL(itbuf),
  128. cryp->base + DFE_CFG);
  129. writel(MTK_DFSE_MIN_DATA(opbuf - 1) |
  130. MTK_DFSE_MAX_DATA(opbuf),
  131. cryp->base + DSE_CFG);
  132. writel(MTK_IN_BUF_MIN_THRESH(ipbuf - 1) |
  133. MTK_IN_BUF_MAX_THRESH(ipbuf),
  134. cryp->base + PE_IN_DBUF_THRESH);
  135. writel(MTK_IN_BUF_MIN_THRESH(itbuf - 1) |
  136. MTK_IN_BUF_MAX_THRESH(itbuf),
  137. cryp->base + PE_IN_TBUF_THRESH);
  138. writel(MTK_OUT_BUF_MIN_THRESH(opbuf - 1) |
  139. MTK_OUT_BUF_MAX_THRESH(opbuf),
  140. cryp->base + PE_OUT_DBUF_THRESH);
  141. writel(0, cryp->base + PE_OUT_TBUF_THRESH);
  142. writel(0, cryp->base + PE_OUT_BUF_CTRL);
  143. }
  144. static int mtk_dfe_dse_state_check(struct mtk_cryp *cryp)
  145. {
  146. int ret = -EINVAL;
  147. u32 val;
  148. /* Check for completion of all DMA transfers */
  149. val = readl(cryp->base + DFE_THR_STAT);
  150. if (MTK_DFSE_RING_ID(val) == MTK_DFSE_IDLE) {
  151. val = readl(cryp->base + DSE_THR_STAT);
  152. if (MTK_DFSE_RING_ID(val) == MTK_DFSE_IDLE)
  153. ret = 0;
  154. }
  155. if (!ret) {
  156. /* Take DFE/DSE thread out of reset */
  157. writel(0, cryp->base + DFE_THR_CTRL);
  158. writel(0, cryp->base + DSE_THR_CTRL);
  159. } else {
  160. return -EBUSY;
  161. }
  162. return 0;
  163. }
  164. static int mtk_dfe_dse_reset(struct mtk_cryp *cryp)
  165. {
  166. /* Reset DSE/DFE and correct system priorities for all rings. */
  167. writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DFE_THR_CTRL);
  168. writel(0, cryp->base + DFE_PRIO_0);
  169. writel(0, cryp->base + DFE_PRIO_1);
  170. writel(0, cryp->base + DFE_PRIO_2);
  171. writel(0, cryp->base + DFE_PRIO_3);
  172. writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DSE_THR_CTRL);
  173. writel(0, cryp->base + DSE_PRIO_0);
  174. writel(0, cryp->base + DSE_PRIO_1);
  175. writel(0, cryp->base + DSE_PRIO_2);
  176. writel(0, cryp->base + DSE_PRIO_3);
  177. return mtk_dfe_dse_state_check(cryp);
  178. }
  179. static void mtk_cmd_desc_ring_setup(struct mtk_cryp *cryp,
  180. int i, struct mtk_sys_cap *cap)
  181. {
  182. /* Full descriptor that fits FIFO minus one */
  183. u32 count =
  184. ((1 << MTK_CMD_FIFO_SIZE(cap->hia_opt)) / MTK_DESC_SZ) - 1;
  185. /* Temporarily disable external triggering */
  186. writel(0, cryp->base + CDR_CFG(i));
  187. /* Clear CDR count */
  188. writel(MTK_CNT_RST, cryp->base + CDR_PREP_COUNT(i));
  189. writel(MTK_CNT_RST, cryp->base + CDR_PROC_COUNT(i));
  190. writel(0, cryp->base + CDR_PREP_PNTR(i));
  191. writel(0, cryp->base + CDR_PROC_PNTR(i));
  192. writel(0, cryp->base + CDR_DMA_CFG(i));
  193. /* Configure CDR host address space */
  194. writel(0, cryp->base + CDR_BASE_ADDR_HI(i));
  195. writel(cryp->ring[i]->cmd_dma, cryp->base + CDR_BASE_ADDR_LO(i));
  196. writel(MTK_DESC_RING_SZ, cryp->base + CDR_RING_SIZE(i));
  197. /* Clear and disable all CDR interrupts */
  198. writel(MTK_CDR_STAT_CLR, cryp->base + CDR_STAT(i));
  199. /*
  200. * Set command descriptor offset and enable additional
  201. * token present in descriptor.
  202. */
  203. writel(MTK_DESC_SIZE(MTK_DESC_SZ) |
  204. MTK_DESC_OFFSET(MTK_DESC_OFF) |
  205. MTK_DESC_ATP_PRESENT,
  206. cryp->base + CDR_DESC_SIZE(i));
  207. writel(MTK_DESC_FETCH_SIZE(count * MTK_DESC_OFF) |
  208. MTK_DESC_FETCH_THRESH(count * MTK_DESC_SZ),
  209. cryp->base + CDR_CFG(i));
  210. }
  211. static void mtk_res_desc_ring_setup(struct mtk_cryp *cryp,
  212. int i, struct mtk_sys_cap *cap)
  213. {
  214. u32 rndup = 2;
  215. u32 count = ((1 << MTK_RES_FIFO_SIZE(cap->hia_opt)) / rndup) - 1;
  216. /* Temporarily disable external triggering */
  217. writel(0, cryp->base + RDR_CFG(i));
  218. /* Clear RDR count */
  219. writel(MTK_CNT_RST, cryp->base + RDR_PREP_COUNT(i));
  220. writel(MTK_CNT_RST, cryp->base + RDR_PROC_COUNT(i));
  221. writel(0, cryp->base + RDR_PREP_PNTR(i));
  222. writel(0, cryp->base + RDR_PROC_PNTR(i));
  223. writel(0, cryp->base + RDR_DMA_CFG(i));
  224. /* Configure RDR host address space */
  225. writel(0, cryp->base + RDR_BASE_ADDR_HI(i));
  226. writel(cryp->ring[i]->res_dma, cryp->base + RDR_BASE_ADDR_LO(i));
  227. writel(MTK_DESC_RING_SZ, cryp->base + RDR_RING_SIZE(i));
  228. writel(MTK_RDR_STAT_CLR, cryp->base + RDR_STAT(i));
  229. /*
  230. * RDR manager generates update interrupts on a per-completed-packet,
  231. * and the rd_proc_thresh_irq interrupt is fired when proc_pkt_count
  232. * for the RDR exceeds the number of packets.
  233. */
  234. writel(MTK_RDR_PROC_THRESH | MTK_RDR_PROC_MODE,
  235. cryp->base + RDR_THRESH(i));
  236. /*
  237. * Configure a threshold and time-out value for the processed
  238. * result descriptors (or complete packets) that are written to
  239. * the RDR.
  240. */
  241. writel(MTK_DESC_SIZE(MTK_DESC_SZ) | MTK_DESC_OFFSET(MTK_DESC_OFF),
  242. cryp->base + RDR_DESC_SIZE(i));
  243. /*
  244. * Configure HIA fetch size and fetch threshold that are used to
  245. * fetch blocks of multiple descriptors.
  246. */
  247. writel(MTK_DESC_FETCH_SIZE(count * MTK_DESC_OFF) |
  248. MTK_DESC_FETCH_THRESH(count * rndup) |
  249. MTK_DESC_OVL_IRQ_EN,
  250. cryp->base + RDR_CFG(i));
  251. }
  252. static int mtk_packet_engine_setup(struct mtk_cryp *cryp)
  253. {
  254. struct mtk_sys_cap cap;
  255. int i, err;
  256. u32 val;
  257. cap.hia_ver = readl(cryp->base + HIA_VERSION);
  258. cap.hia_opt = readl(cryp->base + HIA_OPTIONS);
  259. cap.hw_opt = readl(cryp->base + EIP97_OPTIONS);
  260. if (!(((u16)cap.hia_ver) == MTK_HIA_SIGNATURE))
  261. return -EINVAL;
  262. /* Configure endianness conversion method for master (DMA) interface */
  263. writel(0, cryp->base + EIP97_MST_CTRL);
  264. /* Set HIA burst size */
  265. val = readl(cryp->base + HIA_MST_CTRL);
  266. val &= ~MTK_BURST_SIZE_MSK;
  267. val |= MTK_BURST_SIZE(5);
  268. writel(val, cryp->base + HIA_MST_CTRL);
  269. err = mtk_dfe_dse_reset(cryp);
  270. if (err) {
  271. dev_err(cryp->dev, "Failed to reset DFE and DSE.\n");
  272. return err;
  273. }
  274. mtk_dfe_dse_buf_setup(cryp, &cap);
  275. /* Enable the 4 rings for the packet engines. */
  276. mtk_desc_ring_link(cryp, 0xf);
  277. for (i = 0; i < MTK_RING_MAX; i++) {
  278. mtk_cmd_desc_ring_setup(cryp, i, &cap);
  279. mtk_res_desc_ring_setup(cryp, i, &cap);
  280. }
  281. writel(MTK_PE_TK_LOC_AVL | MTK_PE_PROC_HELD | MTK_PE_TK_TIMEOUT_EN,
  282. cryp->base + PE_TOKEN_CTRL_STAT);
  283. /* Clear all pending interrupts */
  284. writel(MTK_AIC_G_CLR, cryp->base + AIC_G_ACK);
  285. writel(MTK_PE_INPUT_DMA_ERR | MTK_PE_OUTPUT_DMA_ERR |
  286. MTK_PE_PKT_PORC_ERR | MTK_PE_PKT_TIMEOUT |
  287. MTK_PE_FATAL_ERR | MTK_PE_INPUT_DMA_ERR_EN |
  288. MTK_PE_OUTPUT_DMA_ERR_EN | MTK_PE_PKT_PORC_ERR_EN |
  289. MTK_PE_PKT_TIMEOUT_EN | MTK_PE_FATAL_ERR_EN |
  290. MTK_PE_INT_OUT_EN,
  291. cryp->base + PE_INTERRUPT_CTRL_STAT);
  292. return 0;
  293. }
  294. static int mtk_aic_cap_check(struct mtk_cryp *cryp, int hw)
  295. {
  296. u32 val;
  297. if (hw == MTK_RING_MAX)
  298. val = readl(cryp->base + AIC_G_VERSION);
  299. else
  300. val = readl(cryp->base + AIC_VERSION(hw));
  301. val &= MTK_AIC_VER_MSK;
  302. if (val != MTK_AIC_VER11 && val != MTK_AIC_VER12)
  303. return -ENXIO;
  304. if (hw == MTK_RING_MAX)
  305. val = readl(cryp->base + AIC_G_OPTIONS);
  306. else
  307. val = readl(cryp->base + AIC_OPTIONS(hw));
  308. val &= MTK_AIC_INT_MSK;
  309. if (!val || val > 32)
  310. return -ENXIO;
  311. return 0;
  312. }
  313. static int mtk_aic_init(struct mtk_cryp *cryp, int hw)
  314. {
  315. int err;
  316. err = mtk_aic_cap_check(cryp, hw);
  317. if (err)
  318. return err;
  319. /* Disable all interrupts and set initial configuration */
  320. if (hw == MTK_RING_MAX) {
  321. writel(0, cryp->base + AIC_G_ENABLE_CTRL);
  322. writel(0, cryp->base + AIC_G_POL_CTRL);
  323. writel(0, cryp->base + AIC_G_TYPE_CTRL);
  324. writel(0, cryp->base + AIC_G_ENABLE_SET);
  325. } else {
  326. writel(0, cryp->base + AIC_ENABLE_CTRL(hw));
  327. writel(0, cryp->base + AIC_POL_CTRL(hw));
  328. writel(0, cryp->base + AIC_TYPE_CTRL(hw));
  329. writel(0, cryp->base + AIC_ENABLE_SET(hw));
  330. }
  331. return 0;
  332. }
  333. static int mtk_accelerator_init(struct mtk_cryp *cryp)
  334. {
  335. int i, err;
  336. /* Initialize advanced interrupt controller(AIC) */
  337. for (i = 0; i < MTK_IRQ_NUM; i++) {
  338. err = mtk_aic_init(cryp, i);
  339. if (err) {
  340. dev_err(cryp->dev, "Failed to initialize AIC.\n");
  341. return err;
  342. }
  343. }
  344. /* Initialize packet engine */
  345. err = mtk_packet_engine_setup(cryp);
  346. if (err) {
  347. dev_err(cryp->dev, "Failed to configure packet engine.\n");
  348. return err;
  349. }
  350. return 0;
  351. }
  352. static void mtk_desc_dma_free(struct mtk_cryp *cryp)
  353. {
  354. int i;
  355. for (i = 0; i < MTK_RING_MAX; i++) {
  356. dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
  357. cryp->ring[i]->res_base,
  358. cryp->ring[i]->res_dma);
  359. dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
  360. cryp->ring[i]->cmd_base,
  361. cryp->ring[i]->cmd_dma);
  362. kfree(cryp->ring[i]);
  363. }
  364. }
  365. static int mtk_desc_ring_alloc(struct mtk_cryp *cryp)
  366. {
  367. struct mtk_ring **ring = cryp->ring;
  368. int i;
  369. for (i = 0; i < MTK_RING_MAX; i++) {
  370. ring[i] = kzalloc(sizeof(**ring), GFP_KERNEL);
  371. if (!ring[i])
  372. goto err_cleanup;
  373. ring[i]->cmd_base = dma_alloc_coherent(cryp->dev,
  374. MTK_DESC_RING_SZ,
  375. &ring[i]->cmd_dma,
  376. GFP_KERNEL);
  377. if (!ring[i]->cmd_base)
  378. goto err_cleanup;
  379. ring[i]->res_base = dma_alloc_coherent(cryp->dev,
  380. MTK_DESC_RING_SZ,
  381. &ring[i]->res_dma,
  382. GFP_KERNEL);
  383. if (!ring[i]->res_base)
  384. goto err_cleanup;
  385. ring[i]->cmd_next = ring[i]->cmd_base;
  386. ring[i]->res_next = ring[i]->res_base;
  387. }
  388. return 0;
  389. err_cleanup:
  390. do {
  391. dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
  392. ring[i]->res_base, ring[i]->res_dma);
  393. dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
  394. ring[i]->cmd_base, ring[i]->cmd_dma);
  395. kfree(ring[i]);
  396. } while (i--);
  397. return -ENOMEM;
  398. }
  399. static int mtk_crypto_probe(struct platform_device *pdev)
  400. {
  401. struct mtk_cryp *cryp;
  402. int i, err;
  403. cryp = devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL);
  404. if (!cryp)
  405. return -ENOMEM;
  406. cryp->base = devm_platform_ioremap_resource(pdev, 0);
  407. if (IS_ERR(cryp->base))
  408. return PTR_ERR(cryp->base);
  409. for (i = 0; i < MTK_IRQ_NUM; i++) {
  410. cryp->irq[i] = platform_get_irq(pdev, i);
  411. if (cryp->irq[i] < 0)
  412. return cryp->irq[i];
  413. }
  414. cryp->clk_cryp = devm_clk_get(&pdev->dev, "cryp");
  415. if (IS_ERR(cryp->clk_cryp))
  416. return -EPROBE_DEFER;
  417. cryp->dev = &pdev->dev;
  418. pm_runtime_enable(cryp->dev);
  419. pm_runtime_get_sync(cryp->dev);
  420. err = clk_prepare_enable(cryp->clk_cryp);
  421. if (err)
  422. goto err_clk_cryp;
  423. /* Allocate four command/result descriptor rings */
  424. err = mtk_desc_ring_alloc(cryp);
  425. if (err) {
  426. dev_err(cryp->dev, "Unable to allocate descriptor rings.\n");
  427. goto err_resource;
  428. }
  429. /* Initialize hardware modules */
  430. err = mtk_accelerator_init(cryp);
  431. if (err) {
  432. dev_err(cryp->dev, "Failed to initialize cryptographic engine.\n");
  433. goto err_engine;
  434. }
  435. err = mtk_cipher_alg_register(cryp);
  436. if (err) {
  437. dev_err(cryp->dev, "Unable to register cipher algorithm.\n");
  438. goto err_cipher;
  439. }
  440. err = mtk_hash_alg_register(cryp);
  441. if (err) {
  442. dev_err(cryp->dev, "Unable to register hash algorithm.\n");
  443. goto err_hash;
  444. }
  445. platform_set_drvdata(pdev, cryp);
  446. return 0;
  447. err_hash:
  448. mtk_cipher_alg_release(cryp);
  449. err_cipher:
  450. mtk_dfe_dse_reset(cryp);
  451. err_engine:
  452. mtk_desc_dma_free(cryp);
  453. err_resource:
  454. clk_disable_unprepare(cryp->clk_cryp);
  455. err_clk_cryp:
  456. pm_runtime_put_sync(cryp->dev);
  457. pm_runtime_disable(cryp->dev);
  458. return err;
  459. }
  460. static int mtk_crypto_remove(struct platform_device *pdev)
  461. {
  462. struct mtk_cryp *cryp = platform_get_drvdata(pdev);
  463. mtk_hash_alg_release(cryp);
  464. mtk_cipher_alg_release(cryp);
  465. mtk_desc_dma_free(cryp);
  466. clk_disable_unprepare(cryp->clk_cryp);
  467. pm_runtime_put_sync(cryp->dev);
  468. pm_runtime_disable(cryp->dev);
  469. platform_set_drvdata(pdev, NULL);
  470. return 0;
  471. }
  472. static const struct of_device_id of_crypto_id[] = {
  473. { .compatible = "mediatek,eip97-crypto" },
  474. {},
  475. };
  476. MODULE_DEVICE_TABLE(of, of_crypto_id);
  477. static struct platform_driver mtk_crypto_driver = {
  478. .probe = mtk_crypto_probe,
  479. .remove = mtk_crypto_remove,
  480. .driver = {
  481. .name = "mtk-crypto",
  482. .of_match_table = of_crypto_id,
  483. },
  484. };
  485. module_platform_driver(mtk_crypto_driver);
  486. MODULE_LICENSE("GPL");
  487. MODULE_AUTHOR("Ryder Lee <ryder.lee@mediatek.com>");
  488. MODULE_DESCRIPTION("Cryptographic accelerator driver for EIP97");