cpuidle-zynq.c 1.5 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2012-2013 Xilinx
  4. *
  5. * CPU idle support for Xilinx Zynq
  6. *
  7. * based on arch/arm/mach-at91/cpuidle.c
  8. *
  9. * The cpu idle uses wait-for-interrupt and RAM self refresh in order
  10. * to implement two idle states -
  11. * #1 wait-for-interrupt
  12. * #2 wait-for-interrupt and RAM self refresh
  13. *
  14. * Maintainer: Michal Simek <michal.simek@xilinx.com>
  15. */
  16. #include <linux/init.h>
  17. #include <linux/cpuidle.h>
  18. #include <linux/platform_device.h>
  19. #include <asm/cpuidle.h>
  20. #define ZYNQ_MAX_STATES 2
  21. /* Actual code that puts the SoC in different idle states */
  22. static int zynq_enter_idle(struct cpuidle_device *dev,
  23. struct cpuidle_driver *drv, int index)
  24. {
  25. /* Add code for DDR self refresh start */
  26. cpu_do_idle();
  27. return index;
  28. }
  29. static struct cpuidle_driver zynq_idle_driver = {
  30. .name = "zynq_idle",
  31. .owner = THIS_MODULE,
  32. .states = {
  33. ARM_CPUIDLE_WFI_STATE,
  34. {
  35. .enter = zynq_enter_idle,
  36. .exit_latency = 10,
  37. .target_residency = 10000,
  38. .name = "RAM_SR",
  39. .desc = "WFI and RAM Self Refresh",
  40. },
  41. },
  42. .safe_state_index = 0,
  43. .state_count = ZYNQ_MAX_STATES,
  44. };
  45. /* Initialize CPU idle by registering the idle states */
  46. static int zynq_cpuidle_probe(struct platform_device *pdev)
  47. {
  48. pr_info("Xilinx Zynq CpuIdle Driver started\n");
  49. return cpuidle_register(&zynq_idle_driver, NULL);
  50. }
  51. static struct platform_driver zynq_cpuidle_driver = {
  52. .driver = {
  53. .name = "cpuidle-zynq",
  54. },
  55. .probe = zynq_cpuidle_probe,
  56. };
  57. builtin_platform_driver(zynq_cpuidle_driver);