cpuidle-tegra.c 9.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * CPU idle driver for Tegra CPUs
  4. *
  5. * Copyright (c) 2010-2013, NVIDIA Corporation.
  6. * Copyright (c) 2011 Google, Inc.
  7. * Author: Colin Cross <ccross@android.com>
  8. * Gary King <gking@nvidia.com>
  9. *
  10. * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
  11. *
  12. * Tegra20/124 driver unification by Dmitry Osipenko <digetx@gmail.com>
  13. */
  14. #define pr_fmt(fmt) "tegra-cpuidle: " fmt
  15. #include <linux/atomic.h>
  16. #include <linux/cpuidle.h>
  17. #include <linux/cpumask.h>
  18. #include <linux/cpu_pm.h>
  19. #include <linux/delay.h>
  20. #include <linux/errno.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/types.h>
  23. #include <linux/clk/tegra.h>
  24. #include <linux/firmware/trusted_foundations.h>
  25. #include <soc/tegra/cpuidle.h>
  26. #include <soc/tegra/flowctrl.h>
  27. #include <soc/tegra/fuse.h>
  28. #include <soc/tegra/irq.h>
  29. #include <soc/tegra/pm.h>
  30. #include <soc/tegra/pmc.h>
  31. #include <asm/cpuidle.h>
  32. #include <asm/firmware.h>
  33. #include <asm/smp_plat.h>
  34. #include <asm/suspend.h>
  35. enum tegra_state {
  36. TEGRA_C1,
  37. TEGRA_C7,
  38. TEGRA_CC6,
  39. TEGRA_STATE_COUNT,
  40. };
  41. static atomic_t tegra_idle_barrier;
  42. static atomic_t tegra_abort_flag;
  43. static inline bool tegra_cpuidle_using_firmware(void)
  44. {
  45. return firmware_ops->prepare_idle && firmware_ops->do_idle;
  46. }
  47. static void tegra_cpuidle_report_cpus_state(void)
  48. {
  49. unsigned long cpu, lcpu, csr;
  50. for_each_cpu(lcpu, cpu_possible_mask) {
  51. cpu = cpu_logical_map(lcpu);
  52. csr = flowctrl_read_cpu_csr(cpu);
  53. pr_err("cpu%lu: online=%d flowctrl_csr=0x%08lx\n",
  54. cpu, cpu_online(lcpu), csr);
  55. }
  56. }
  57. static int tegra_cpuidle_wait_for_secondary_cpus_parking(void)
  58. {
  59. unsigned int retries = 3;
  60. while (retries--) {
  61. unsigned int delay_us = 10;
  62. unsigned int timeout_us = 500 * 1000 / delay_us;
  63. /*
  64. * The primary CPU0 core shall wait for the secondaries
  65. * shutdown in order to power-off CPU's cluster safely.
  66. * The timeout value depends on the current CPU frequency,
  67. * it takes about 40-150us in average and over 1000us in
  68. * a worst case scenario.
  69. */
  70. do {
  71. if (tegra_cpu_rail_off_ready())
  72. return 0;
  73. udelay(delay_us);
  74. } while (timeout_us--);
  75. pr_err("secondary CPU taking too long to park\n");
  76. tegra_cpuidle_report_cpus_state();
  77. }
  78. pr_err("timed out waiting secondaries to park\n");
  79. return -ETIMEDOUT;
  80. }
  81. static void tegra_cpuidle_unpark_secondary_cpus(void)
  82. {
  83. unsigned int cpu, lcpu;
  84. for_each_cpu(lcpu, cpu_online_mask) {
  85. cpu = cpu_logical_map(lcpu);
  86. if (cpu > 0) {
  87. tegra_enable_cpu_clock(cpu);
  88. tegra_cpu_out_of_reset(cpu);
  89. flowctrl_write_cpu_halt(cpu, 0);
  90. }
  91. }
  92. }
  93. static int tegra_cpuidle_cc6_enter(unsigned int cpu)
  94. {
  95. int ret;
  96. if (cpu > 0) {
  97. ret = cpu_suspend(cpu, tegra_pm_park_secondary_cpu);
  98. } else {
  99. ret = tegra_cpuidle_wait_for_secondary_cpus_parking();
  100. if (!ret)
  101. ret = tegra_pm_enter_lp2();
  102. tegra_cpuidle_unpark_secondary_cpus();
  103. }
  104. return ret;
  105. }
  106. static int tegra_cpuidle_c7_enter(void)
  107. {
  108. int err;
  109. err = call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2);
  110. if (err && err != -ENOSYS)
  111. return err;
  112. err = call_firmware_op(do_idle, 0);
  113. if (err != -ENOSYS)
  114. return err;
  115. return cpu_suspend(0, tegra30_pm_secondary_cpu_suspend);
  116. }
  117. static int tegra_cpuidle_coupled_barrier(struct cpuidle_device *dev)
  118. {
  119. if (tegra_pending_sgi()) {
  120. /*
  121. * CPU got local interrupt that will be lost after GIC's
  122. * shutdown because GIC driver doesn't save/restore the
  123. * pending SGI state across CPU cluster PM. Abort and retry
  124. * next time.
  125. */
  126. atomic_set(&tegra_abort_flag, 1);
  127. }
  128. cpuidle_coupled_parallel_barrier(dev, &tegra_idle_barrier);
  129. if (atomic_read(&tegra_abort_flag)) {
  130. cpuidle_coupled_parallel_barrier(dev, &tegra_idle_barrier);
  131. atomic_set(&tegra_abort_flag, 0);
  132. return -EINTR;
  133. }
  134. return 0;
  135. }
  136. static int tegra_cpuidle_state_enter(struct cpuidle_device *dev,
  137. int index, unsigned int cpu)
  138. {
  139. int err;
  140. /*
  141. * CC6 state is the "CPU cluster power-off" state. In order to
  142. * enter this state, at first the secondary CPU cores need to be
  143. * parked into offline mode, then the last CPU should clean out
  144. * remaining dirty cache lines into DRAM and trigger Flow Controller
  145. * logic that turns off the cluster's power domain (which includes
  146. * CPU cores, GIC and L2 cache).
  147. */
  148. if (index == TEGRA_CC6) {
  149. err = tegra_cpuidle_coupled_barrier(dev);
  150. if (err)
  151. return err;
  152. }
  153. local_fiq_disable();
  154. RCU_NONIDLE(tegra_pm_set_cpu_in_lp2());
  155. cpu_pm_enter();
  156. switch (index) {
  157. case TEGRA_C7:
  158. err = tegra_cpuidle_c7_enter();
  159. break;
  160. case TEGRA_CC6:
  161. err = tegra_cpuidle_cc6_enter(cpu);
  162. break;
  163. default:
  164. err = -EINVAL;
  165. break;
  166. }
  167. cpu_pm_exit();
  168. RCU_NONIDLE(tegra_pm_clear_cpu_in_lp2());
  169. local_fiq_enable();
  170. return err ?: index;
  171. }
  172. static int tegra_cpuidle_adjust_state_index(int index, unsigned int cpu)
  173. {
  174. /*
  175. * On Tegra30 CPU0 can't be power-gated separately from secondary
  176. * cores because it gates the whole CPU cluster.
  177. */
  178. if (cpu > 0 || index != TEGRA_C7 || tegra_get_chip_id() != TEGRA30)
  179. return index;
  180. /* put CPU0 into C1 if C7 is requested and secondaries are online */
  181. if (!IS_ENABLED(CONFIG_PM_SLEEP) || num_online_cpus() > 1)
  182. index = TEGRA_C1;
  183. else
  184. index = TEGRA_CC6;
  185. return index;
  186. }
  187. static int tegra_cpuidle_enter(struct cpuidle_device *dev,
  188. struct cpuidle_driver *drv,
  189. int index)
  190. {
  191. unsigned int cpu = cpu_logical_map(dev->cpu);
  192. int ret;
  193. index = tegra_cpuidle_adjust_state_index(index, cpu);
  194. if (dev->states_usage[index].disable)
  195. return -1;
  196. if (index == TEGRA_C1)
  197. ret = arm_cpuidle_simple_enter(dev, drv, index);
  198. else
  199. ret = tegra_cpuidle_state_enter(dev, index, cpu);
  200. if (ret < 0) {
  201. if (ret != -EINTR || index != TEGRA_CC6)
  202. pr_err_once("failed to enter state %d err: %d\n",
  203. index, ret);
  204. index = -1;
  205. } else {
  206. index = ret;
  207. }
  208. return index;
  209. }
  210. static int tegra114_enter_s2idle(struct cpuidle_device *dev,
  211. struct cpuidle_driver *drv,
  212. int index)
  213. {
  214. tegra_cpuidle_enter(dev, drv, index);
  215. return 0;
  216. }
  217. /*
  218. * The previous versions of Tegra CPUIDLE driver used a different "legacy"
  219. * terminology for naming of the idling states, while this driver uses the
  220. * new terminology.
  221. *
  222. * Mapping of the old terms into the new ones:
  223. *
  224. * Old | New
  225. * ---------
  226. * LP3 | C1 (CPU core clock gating)
  227. * LP2 | C7 (CPU core power gating)
  228. * LP2 | CC6 (CPU cluster power gating)
  229. *
  230. * Note that that the older CPUIDLE driver versions didn't explicitly
  231. * differentiate the LP2 states because these states either used the same
  232. * code path or because CC6 wasn't supported.
  233. */
  234. static struct cpuidle_driver tegra_idle_driver = {
  235. .name = "tegra_idle",
  236. .states = {
  237. [TEGRA_C1] = ARM_CPUIDLE_WFI_STATE_PWR(600),
  238. [TEGRA_C7] = {
  239. .enter = tegra_cpuidle_enter,
  240. .exit_latency = 2000,
  241. .target_residency = 2200,
  242. .power_usage = 100,
  243. .flags = CPUIDLE_FLAG_TIMER_STOP,
  244. .name = "C7",
  245. .desc = "CPU core powered off",
  246. },
  247. [TEGRA_CC6] = {
  248. .enter = tegra_cpuidle_enter,
  249. .exit_latency = 5000,
  250. .target_residency = 10000,
  251. .power_usage = 0,
  252. .flags = CPUIDLE_FLAG_TIMER_STOP |
  253. CPUIDLE_FLAG_COUPLED,
  254. .name = "CC6",
  255. .desc = "CPU cluster powered off",
  256. },
  257. },
  258. .state_count = TEGRA_STATE_COUNT,
  259. .safe_state_index = TEGRA_C1,
  260. };
  261. static inline void tegra_cpuidle_disable_state(enum tegra_state state)
  262. {
  263. cpuidle_driver_state_disabled(&tegra_idle_driver, state, true);
  264. }
  265. /*
  266. * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
  267. * they are legacy IRQs or MSI, are lost when CC6 is enabled. To work around
  268. * this, simply disable CC6 if the PCI driver and DT node are both enabled.
  269. */
  270. void tegra_cpuidle_pcie_irqs_in_use(void)
  271. {
  272. struct cpuidle_state *state_cc6 = &tegra_idle_driver.states[TEGRA_CC6];
  273. if ((state_cc6->flags & CPUIDLE_FLAG_UNUSABLE) ||
  274. tegra_get_chip_id() != TEGRA20)
  275. return;
  276. pr_info("disabling CC6 state, since PCIe IRQs are in use\n");
  277. tegra_cpuidle_disable_state(TEGRA_CC6);
  278. }
  279. static void tegra_cpuidle_setup_tegra114_c7_state(void)
  280. {
  281. struct cpuidle_state *s = &tegra_idle_driver.states[TEGRA_C7];
  282. s->enter_s2idle = tegra114_enter_s2idle;
  283. s->target_residency = 1000;
  284. s->exit_latency = 500;
  285. }
  286. static int tegra_cpuidle_probe(struct platform_device *pdev)
  287. {
  288. /* LP2 could be disabled in device-tree */
  289. if (tegra_pmc_get_suspend_mode() < TEGRA_SUSPEND_LP2)
  290. tegra_cpuidle_disable_state(TEGRA_CC6);
  291. /*
  292. * Required suspend-resume functionality, which is provided by the
  293. * Tegra-arch core and PMC driver, is unavailable if PM-sleep option
  294. * is disabled.
  295. */
  296. if (!IS_ENABLED(CONFIG_PM_SLEEP)) {
  297. if (!tegra_cpuidle_using_firmware())
  298. tegra_cpuidle_disable_state(TEGRA_C7);
  299. tegra_cpuidle_disable_state(TEGRA_CC6);
  300. }
  301. /*
  302. * Generic WFI state (also known as C1 or LP3) and the coupled CPU
  303. * cluster power-off (CC6 or LP2) states are common for all Tegra SoCs.
  304. */
  305. switch (tegra_get_chip_id()) {
  306. case TEGRA20:
  307. /* Tegra20 isn't capable to power-off individual CPU cores */
  308. tegra_cpuidle_disable_state(TEGRA_C7);
  309. break;
  310. case TEGRA30:
  311. break;
  312. case TEGRA114:
  313. case TEGRA124:
  314. tegra_cpuidle_setup_tegra114_c7_state();
  315. /* coupled CC6 (LP2) state isn't implemented yet */
  316. tegra_cpuidle_disable_state(TEGRA_CC6);
  317. break;
  318. default:
  319. return -EINVAL;
  320. }
  321. return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
  322. }
  323. static struct platform_driver tegra_cpuidle_driver = {
  324. .probe = tegra_cpuidle_probe,
  325. .driver = {
  326. .name = "tegra-cpuidle",
  327. },
  328. };
  329. builtin_platform_driver(tegra_cpuidle_driver);