cpuidle-qcom-spm.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2014,2015, Linaro Ltd.
  5. *
  6. * SAW power controller driver
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/init.h>
  10. #include <linux/io.h>
  11. #include <linux/slab.h>
  12. #include <linux/of.h>
  13. #include <linux/of_address.h>
  14. #include <linux/of_device.h>
  15. #include <linux/err.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/cpuidle.h>
  18. #include <linux/cpu_pm.h>
  19. #include <linux/qcom_scm.h>
  20. #include <asm/proc-fns.h>
  21. #include <asm/suspend.h>
  22. #include "dt_idle_states.h"
  23. #define MAX_PMIC_DATA 2
  24. #define MAX_SEQ_DATA 64
  25. #define SPM_CTL_INDEX 0x7f
  26. #define SPM_CTL_INDEX_SHIFT 4
  27. #define SPM_CTL_EN BIT(0)
  28. enum pm_sleep_mode {
  29. PM_SLEEP_MODE_STBY,
  30. PM_SLEEP_MODE_RET,
  31. PM_SLEEP_MODE_SPC,
  32. PM_SLEEP_MODE_PC,
  33. PM_SLEEP_MODE_NR,
  34. };
  35. enum spm_reg {
  36. SPM_REG_CFG,
  37. SPM_REG_SPM_CTL,
  38. SPM_REG_DLY,
  39. SPM_REG_PMIC_DLY,
  40. SPM_REG_PMIC_DATA_0,
  41. SPM_REG_PMIC_DATA_1,
  42. SPM_REG_VCTL,
  43. SPM_REG_SEQ_ENTRY,
  44. SPM_REG_SPM_STS,
  45. SPM_REG_PMIC_STS,
  46. SPM_REG_NR,
  47. };
  48. struct spm_reg_data {
  49. const u8 *reg_offset;
  50. u32 spm_cfg;
  51. u32 spm_dly;
  52. u32 pmic_dly;
  53. u32 pmic_data[MAX_PMIC_DATA];
  54. u8 seq[MAX_SEQ_DATA];
  55. u8 start_index[PM_SLEEP_MODE_NR];
  56. };
  57. struct spm_driver_data {
  58. struct cpuidle_driver cpuidle_driver;
  59. void __iomem *reg_base;
  60. const struct spm_reg_data *reg_data;
  61. };
  62. static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = {
  63. [SPM_REG_CFG] = 0x08,
  64. [SPM_REG_SPM_CTL] = 0x30,
  65. [SPM_REG_DLY] = 0x34,
  66. [SPM_REG_SEQ_ENTRY] = 0x80,
  67. };
  68. /* SPM register data for 8974, 8084 */
  69. static const struct spm_reg_data spm_reg_8974_8084_cpu = {
  70. .reg_offset = spm_reg_offset_v2_1,
  71. .spm_cfg = 0x1,
  72. .spm_dly = 0x3C102800,
  73. .seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
  74. 0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
  75. 0x0F },
  76. .start_index[PM_SLEEP_MODE_STBY] = 0,
  77. .start_index[PM_SLEEP_MODE_SPC] = 3,
  78. };
  79. static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = {
  80. [SPM_REG_CFG] = 0x08,
  81. [SPM_REG_SPM_CTL] = 0x20,
  82. [SPM_REG_PMIC_DLY] = 0x24,
  83. [SPM_REG_PMIC_DATA_0] = 0x28,
  84. [SPM_REG_PMIC_DATA_1] = 0x2C,
  85. [SPM_REG_SEQ_ENTRY] = 0x80,
  86. };
  87. /* SPM register data for 8064 */
  88. static const struct spm_reg_data spm_reg_8064_cpu = {
  89. .reg_offset = spm_reg_offset_v1_1,
  90. .spm_cfg = 0x1F,
  91. .pmic_dly = 0x02020004,
  92. .pmic_data[0] = 0x0084009C,
  93. .pmic_data[1] = 0x00A4001C,
  94. .seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
  95. 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
  96. .start_index[PM_SLEEP_MODE_STBY] = 0,
  97. .start_index[PM_SLEEP_MODE_SPC] = 2,
  98. };
  99. static inline void spm_register_write(struct spm_driver_data *drv,
  100. enum spm_reg reg, u32 val)
  101. {
  102. if (drv->reg_data->reg_offset[reg])
  103. writel_relaxed(val, drv->reg_base +
  104. drv->reg_data->reg_offset[reg]);
  105. }
  106. /* Ensure a guaranteed write, before return */
  107. static inline void spm_register_write_sync(struct spm_driver_data *drv,
  108. enum spm_reg reg, u32 val)
  109. {
  110. u32 ret;
  111. if (!drv->reg_data->reg_offset[reg])
  112. return;
  113. do {
  114. writel_relaxed(val, drv->reg_base +
  115. drv->reg_data->reg_offset[reg]);
  116. ret = readl_relaxed(drv->reg_base +
  117. drv->reg_data->reg_offset[reg]);
  118. if (ret == val)
  119. break;
  120. cpu_relax();
  121. } while (1);
  122. }
  123. static inline u32 spm_register_read(struct spm_driver_data *drv,
  124. enum spm_reg reg)
  125. {
  126. return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
  127. }
  128. static void spm_set_low_power_mode(struct spm_driver_data *drv,
  129. enum pm_sleep_mode mode)
  130. {
  131. u32 start_index;
  132. u32 ctl_val;
  133. start_index = drv->reg_data->start_index[mode];
  134. ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
  135. ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
  136. ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
  137. ctl_val |= SPM_CTL_EN;
  138. spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
  139. }
  140. static int qcom_pm_collapse(unsigned long int unused)
  141. {
  142. qcom_scm_cpu_power_down(QCOM_SCM_CPU_PWR_DOWN_L2_ON);
  143. /*
  144. * Returns here only if there was a pending interrupt and we did not
  145. * power down as a result.
  146. */
  147. return -1;
  148. }
  149. static int qcom_cpu_spc(struct spm_driver_data *drv)
  150. {
  151. int ret;
  152. spm_set_low_power_mode(drv, PM_SLEEP_MODE_SPC);
  153. ret = cpu_suspend(0, qcom_pm_collapse);
  154. /*
  155. * ARM common code executes WFI without calling into our driver and
  156. * if the SPM mode is not reset, then we may accidently power down the
  157. * cpu when we intended only to gate the cpu clock.
  158. * Ensure the state is set to standby before returning.
  159. */
  160. spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
  161. return ret;
  162. }
  163. static int spm_enter_idle_state(struct cpuidle_device *dev,
  164. struct cpuidle_driver *drv, int idx)
  165. {
  166. struct spm_driver_data *data = container_of(drv, struct spm_driver_data,
  167. cpuidle_driver);
  168. return CPU_PM_CPU_IDLE_ENTER_PARAM(qcom_cpu_spc, idx, data);
  169. }
  170. static struct cpuidle_driver qcom_spm_idle_driver = {
  171. .name = "qcom_spm",
  172. .owner = THIS_MODULE,
  173. .states[0] = {
  174. .enter = spm_enter_idle_state,
  175. .exit_latency = 1,
  176. .target_residency = 1,
  177. .power_usage = UINT_MAX,
  178. .name = "WFI",
  179. .desc = "ARM WFI",
  180. }
  181. };
  182. static const struct of_device_id qcom_idle_state_match[] = {
  183. { .compatible = "qcom,idle-state-spc", .data = spm_enter_idle_state },
  184. { },
  185. };
  186. static int spm_cpuidle_init(struct cpuidle_driver *drv, int cpu)
  187. {
  188. int ret;
  189. memcpy(drv, &qcom_spm_idle_driver, sizeof(*drv));
  190. drv->cpumask = (struct cpumask *)cpumask_of(cpu);
  191. /* Parse idle states from device tree */
  192. ret = dt_init_idle_driver(drv, qcom_idle_state_match, 1);
  193. if (ret <= 0)
  194. return ret ? : -ENODEV;
  195. /* We have atleast one power down mode */
  196. return qcom_scm_set_warm_boot_addr(cpu_resume_arm, drv->cpumask);
  197. }
  198. static struct spm_driver_data *spm_get_drv(struct platform_device *pdev,
  199. int *spm_cpu)
  200. {
  201. struct spm_driver_data *drv = NULL;
  202. struct device_node *cpu_node, *saw_node;
  203. int cpu;
  204. bool found = 0;
  205. for_each_possible_cpu(cpu) {
  206. cpu_node = of_cpu_device_node_get(cpu);
  207. if (!cpu_node)
  208. continue;
  209. saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
  210. found = (saw_node == pdev->dev.of_node);
  211. of_node_put(saw_node);
  212. of_node_put(cpu_node);
  213. if (found)
  214. break;
  215. }
  216. if (found) {
  217. drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
  218. if (drv)
  219. *spm_cpu = cpu;
  220. }
  221. return drv;
  222. }
  223. static const struct of_device_id spm_match_table[] = {
  224. { .compatible = "qcom,msm8974-saw2-v2.1-cpu",
  225. .data = &spm_reg_8974_8084_cpu },
  226. { .compatible = "qcom,apq8084-saw2-v2.1-cpu",
  227. .data = &spm_reg_8974_8084_cpu },
  228. { .compatible = "qcom,apq8064-saw2-v1.1-cpu",
  229. .data = &spm_reg_8064_cpu },
  230. { },
  231. };
  232. static int spm_dev_probe(struct platform_device *pdev)
  233. {
  234. struct spm_driver_data *drv;
  235. struct resource *res;
  236. const struct of_device_id *match_id;
  237. void __iomem *addr;
  238. int cpu, ret;
  239. if (!qcom_scm_is_available())
  240. return -EPROBE_DEFER;
  241. drv = spm_get_drv(pdev, &cpu);
  242. if (!drv)
  243. return -EINVAL;
  244. platform_set_drvdata(pdev, drv);
  245. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  246. drv->reg_base = devm_ioremap_resource(&pdev->dev, res);
  247. if (IS_ERR(drv->reg_base))
  248. return PTR_ERR(drv->reg_base);
  249. match_id = of_match_node(spm_match_table, pdev->dev.of_node);
  250. if (!match_id)
  251. return -ENODEV;
  252. drv->reg_data = match_id->data;
  253. ret = spm_cpuidle_init(&drv->cpuidle_driver, cpu);
  254. if (ret)
  255. return ret;
  256. /* Write the SPM sequences first.. */
  257. addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
  258. __iowrite32_copy(addr, drv->reg_data->seq,
  259. ARRAY_SIZE(drv->reg_data->seq) / 4);
  260. /*
  261. * ..and then the control registers.
  262. * On some SoC if the control registers are written first and if the
  263. * CPU was held in reset, the reset signal could trigger the SPM state
  264. * machine, before the sequences are completely written.
  265. */
  266. spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
  267. spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
  268. spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
  269. spm_register_write(drv, SPM_REG_PMIC_DATA_0,
  270. drv->reg_data->pmic_data[0]);
  271. spm_register_write(drv, SPM_REG_PMIC_DATA_1,
  272. drv->reg_data->pmic_data[1]);
  273. /* Set up Standby as the default low power mode */
  274. spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
  275. return cpuidle_register(&drv->cpuidle_driver, NULL);
  276. }
  277. static int spm_dev_remove(struct platform_device *pdev)
  278. {
  279. struct spm_driver_data *drv = platform_get_drvdata(pdev);
  280. cpuidle_unregister(&drv->cpuidle_driver);
  281. return 0;
  282. }
  283. static struct platform_driver spm_driver = {
  284. .probe = spm_dev_probe,
  285. .remove = spm_dev_remove,
  286. .driver = {
  287. .name = "saw",
  288. .of_match_table = spm_match_table,
  289. },
  290. };
  291. builtin_platform_driver(spm_driver);