cpuidle-exynos.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Coupled cpuidle support based on the work of:
  7. * Colin Cross <ccross@android.com>
  8. * Daniel Lezcano <daniel.lezcano@linaro.org>
  9. */
  10. #include <linux/cpuidle.h>
  11. #include <linux/cpu_pm.h>
  12. #include <linux/export.h>
  13. #include <linux/init.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_data/cpuidle-exynos.h>
  17. #include <asm/suspend.h>
  18. #include <asm/cpuidle.h>
  19. static atomic_t exynos_idle_barrier;
  20. static struct cpuidle_exynos_data *exynos_cpuidle_pdata;
  21. static void (*exynos_enter_aftr)(void);
  22. static int exynos_enter_coupled_lowpower(struct cpuidle_device *dev,
  23. struct cpuidle_driver *drv,
  24. int index)
  25. {
  26. int ret;
  27. exynos_cpuidle_pdata->pre_enter_aftr();
  28. /*
  29. * Waiting all cpus to reach this point at the same moment
  30. */
  31. cpuidle_coupled_parallel_barrier(dev, &exynos_idle_barrier);
  32. /*
  33. * Both cpus will reach this point at the same time
  34. */
  35. ret = dev->cpu ? exynos_cpuidle_pdata->cpu1_powerdown()
  36. : exynos_cpuidle_pdata->cpu0_enter_aftr();
  37. if (ret)
  38. index = ret;
  39. /*
  40. * Waiting all cpus to finish the power sequence before going further
  41. */
  42. cpuidle_coupled_parallel_barrier(dev, &exynos_idle_barrier);
  43. exynos_cpuidle_pdata->post_enter_aftr();
  44. return index;
  45. }
  46. static int exynos_enter_lowpower(struct cpuidle_device *dev,
  47. struct cpuidle_driver *drv,
  48. int index)
  49. {
  50. int new_index = index;
  51. /* AFTR can only be entered when cores other than CPU0 are offline */
  52. if (num_online_cpus() > 1 || dev->cpu != 0)
  53. new_index = drv->safe_state_index;
  54. if (new_index == 0)
  55. return arm_cpuidle_simple_enter(dev, drv, new_index);
  56. exynos_enter_aftr();
  57. return new_index;
  58. }
  59. static struct cpuidle_driver exynos_idle_driver = {
  60. .name = "exynos_idle",
  61. .owner = THIS_MODULE,
  62. .states = {
  63. [0] = ARM_CPUIDLE_WFI_STATE,
  64. [1] = {
  65. .enter = exynos_enter_lowpower,
  66. .exit_latency = 300,
  67. .target_residency = 10000,
  68. .name = "C1",
  69. .desc = "ARM power down",
  70. },
  71. },
  72. .state_count = 2,
  73. .safe_state_index = 0,
  74. };
  75. static struct cpuidle_driver exynos_coupled_idle_driver = {
  76. .name = "exynos_coupled_idle",
  77. .owner = THIS_MODULE,
  78. .states = {
  79. [0] = ARM_CPUIDLE_WFI_STATE,
  80. [1] = {
  81. .enter = exynos_enter_coupled_lowpower,
  82. .exit_latency = 5000,
  83. .target_residency = 10000,
  84. .flags = CPUIDLE_FLAG_COUPLED |
  85. CPUIDLE_FLAG_TIMER_STOP,
  86. .name = "C1",
  87. .desc = "ARM power down",
  88. },
  89. },
  90. .state_count = 2,
  91. .safe_state_index = 0,
  92. };
  93. static int exynos_cpuidle_probe(struct platform_device *pdev)
  94. {
  95. int ret;
  96. if (IS_ENABLED(CONFIG_SMP) &&
  97. (of_machine_is_compatible("samsung,exynos4210") ||
  98. of_machine_is_compatible("samsung,exynos3250"))) {
  99. exynos_cpuidle_pdata = pdev->dev.platform_data;
  100. ret = cpuidle_register(&exynos_coupled_idle_driver,
  101. cpu_possible_mask);
  102. } else {
  103. exynos_enter_aftr = (void *)(pdev->dev.platform_data);
  104. ret = cpuidle_register(&exynos_idle_driver, NULL);
  105. }
  106. if (ret) {
  107. dev_err(&pdev->dev, "failed to register cpuidle driver\n");
  108. return ret;
  109. }
  110. return 0;
  111. }
  112. static struct platform_driver exynos_cpuidle_driver = {
  113. .probe = exynos_cpuidle_probe,
  114. .driver = {
  115. .name = "exynos_cpuidle",
  116. },
  117. };
  118. builtin_platform_driver(exynos_cpuidle_driver);