ti-cpufreq.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * TI CPUFreq/OPP hw-supported driver
  4. *
  5. * Copyright (C) 2016-2017 Texas Instruments, Inc.
  6. * Dave Gerlach <d-gerlach@ti.com>
  7. */
  8. #include <linux/cpu.h>
  9. #include <linux/io.h>
  10. #include <linux/mfd/syscon.h>
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/of.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/pm_opp.h>
  16. #include <linux/regmap.h>
  17. #include <linux/slab.h>
  18. #define REVISION_MASK 0xF
  19. #define REVISION_SHIFT 28
  20. #define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F
  21. #define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA
  22. #define DRA7_EFUSE_HAS_OD_MPU_OPP 11
  23. #define DRA7_EFUSE_HAS_HIGH_MPU_OPP 15
  24. #define DRA76_EFUSE_HAS_PLUS_MPU_OPP 18
  25. #define DRA7_EFUSE_HAS_ALL_MPU_OPP 23
  26. #define DRA76_EFUSE_HAS_ALL_MPU_OPP 24
  27. #define DRA7_EFUSE_NOM_MPU_OPP BIT(0)
  28. #define DRA7_EFUSE_OD_MPU_OPP BIT(1)
  29. #define DRA7_EFUSE_HIGH_MPU_OPP BIT(2)
  30. #define DRA76_EFUSE_PLUS_MPU_OPP BIT(3)
  31. #define OMAP3_CONTROL_DEVICE_STATUS 0x4800244C
  32. #define OMAP3_CONTROL_IDCODE 0x4830A204
  33. #define OMAP34xx_ProdID_SKUID 0x4830A20C
  34. #define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270)
  35. #define VERSION_COUNT 2
  36. struct ti_cpufreq_data;
  37. struct ti_cpufreq_soc_data {
  38. const char * const *reg_names;
  39. unsigned long (*efuse_xlate)(struct ti_cpufreq_data *opp_data,
  40. unsigned long efuse);
  41. unsigned long efuse_fallback;
  42. unsigned long efuse_offset;
  43. unsigned long efuse_mask;
  44. unsigned long efuse_shift;
  45. unsigned long rev_offset;
  46. bool multi_regulator;
  47. };
  48. struct ti_cpufreq_data {
  49. struct device *cpu_dev;
  50. struct device_node *opp_node;
  51. struct regmap *syscon;
  52. const struct ti_cpufreq_soc_data *soc_data;
  53. struct opp_table *opp_table;
  54. };
  55. static unsigned long amx3_efuse_xlate(struct ti_cpufreq_data *opp_data,
  56. unsigned long efuse)
  57. {
  58. if (!efuse)
  59. efuse = opp_data->soc_data->efuse_fallback;
  60. /* AM335x and AM437x use "OPP disable" bits, so invert */
  61. return ~efuse;
  62. }
  63. static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data,
  64. unsigned long efuse)
  65. {
  66. unsigned long calculated_efuse = DRA7_EFUSE_NOM_MPU_OPP;
  67. /*
  68. * The efuse on dra7 and am57 parts contains a specific
  69. * value indicating the highest available OPP.
  70. */
  71. switch (efuse) {
  72. case DRA76_EFUSE_HAS_PLUS_MPU_OPP:
  73. case DRA76_EFUSE_HAS_ALL_MPU_OPP:
  74. calculated_efuse |= DRA76_EFUSE_PLUS_MPU_OPP;
  75. fallthrough;
  76. case DRA7_EFUSE_HAS_ALL_MPU_OPP:
  77. case DRA7_EFUSE_HAS_HIGH_MPU_OPP:
  78. calculated_efuse |= DRA7_EFUSE_HIGH_MPU_OPP;
  79. fallthrough;
  80. case DRA7_EFUSE_HAS_OD_MPU_OPP:
  81. calculated_efuse |= DRA7_EFUSE_OD_MPU_OPP;
  82. }
  83. return calculated_efuse;
  84. }
  85. static unsigned long omap3_efuse_xlate(struct ti_cpufreq_data *opp_data,
  86. unsigned long efuse)
  87. {
  88. /* OPP enable bit ("Speed Binned") */
  89. return BIT(efuse);
  90. }
  91. static struct ti_cpufreq_soc_data am3x_soc_data = {
  92. .efuse_xlate = amx3_efuse_xlate,
  93. .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
  94. .efuse_offset = 0x07fc,
  95. .efuse_mask = 0x1fff,
  96. .rev_offset = 0x600,
  97. .multi_regulator = false,
  98. };
  99. static struct ti_cpufreq_soc_data am4x_soc_data = {
  100. .efuse_xlate = amx3_efuse_xlate,
  101. .efuse_fallback = AM43XX_600M_ARM_MPU_MAX_FREQ,
  102. .efuse_offset = 0x0610,
  103. .efuse_mask = 0x3f,
  104. .rev_offset = 0x600,
  105. .multi_regulator = false,
  106. };
  107. static struct ti_cpufreq_soc_data dra7_soc_data = {
  108. .efuse_xlate = dra7_efuse_xlate,
  109. .efuse_offset = 0x020c,
  110. .efuse_mask = 0xf80000,
  111. .efuse_shift = 19,
  112. .rev_offset = 0x204,
  113. .multi_regulator = true,
  114. };
  115. /*
  116. * OMAP35x TRM (SPRUF98K):
  117. * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
  118. * Control OMAP Status Register 15:0 (Address 0x4800 244C)
  119. * to separate between omap3503, omap3515, omap3525, omap3530
  120. * and feature presence.
  121. * There are encodings for versions limited to 400/266MHz
  122. * but we ignore.
  123. * Not clear if this also holds for omap34xx.
  124. * some eFuse values e.g. CONTROL_FUSE_OPP1_VDD1
  125. * are stored in the SYSCON register range
  126. * Register 0x4830A20C [ProdID.SKUID] [0:3]
  127. * 0x0 for normal 600/430MHz device.
  128. * 0x8 for 720/520MHz device.
  129. * Not clear what omap34xx value is.
  130. */
  131. static struct ti_cpufreq_soc_data omap34xx_soc_data = {
  132. .efuse_xlate = omap3_efuse_xlate,
  133. .efuse_offset = OMAP34xx_ProdID_SKUID - OMAP3_SYSCON_BASE,
  134. .efuse_shift = 3,
  135. .efuse_mask = BIT(3),
  136. .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
  137. .multi_regulator = false,
  138. };
  139. /*
  140. * AM/DM37x TRM (SPRUGN4M)
  141. * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
  142. * Control Device Status Register 15:0 (Address 0x4800 244C)
  143. * to separate between am3703, am3715, dm3725, dm3730
  144. * and feature presence.
  145. * Speed Binned = Bit 9
  146. * 0 800/600 MHz
  147. * 1 1000/800 MHz
  148. * some eFuse values e.g. CONTROL_FUSE_OPP 1G_VDD1
  149. * are stored in the SYSCON register range.
  150. * There is no 0x4830A20C [ProdID.SKUID] register (exists but
  151. * seems to always read as 0).
  152. */
  153. static const char * const omap3_reg_names[] = {"cpu0", "vbb"};
  154. static struct ti_cpufreq_soc_data omap36xx_soc_data = {
  155. .reg_names = omap3_reg_names,
  156. .efuse_xlate = omap3_efuse_xlate,
  157. .efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE,
  158. .efuse_shift = 9,
  159. .efuse_mask = BIT(9),
  160. .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
  161. .multi_regulator = true,
  162. };
  163. /*
  164. * AM3517 is quite similar to AM/DM37x except that it has no
  165. * high speed grade eFuse and no abb ldo
  166. */
  167. static struct ti_cpufreq_soc_data am3517_soc_data = {
  168. .efuse_xlate = omap3_efuse_xlate,
  169. .efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE,
  170. .efuse_shift = 0,
  171. .efuse_mask = 0,
  172. .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
  173. .multi_regulator = false,
  174. };
  175. /**
  176. * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC
  177. * @opp_data: pointer to ti_cpufreq_data context
  178. * @efuse_value: Set to the value parsed from efuse
  179. *
  180. * Returns error code if efuse not read properly.
  181. */
  182. static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data,
  183. u32 *efuse_value)
  184. {
  185. struct device *dev = opp_data->cpu_dev;
  186. u32 efuse;
  187. int ret;
  188. ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset,
  189. &efuse);
  190. if (ret == -EIO) {
  191. /* not a syscon register! */
  192. void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +
  193. opp_data->soc_data->efuse_offset, 4);
  194. if (!regs)
  195. return -ENOMEM;
  196. efuse = readl(regs);
  197. iounmap(regs);
  198. }
  199. else if (ret) {
  200. dev_err(dev,
  201. "Failed to read the efuse value from syscon: %d\n",
  202. ret);
  203. return ret;
  204. }
  205. efuse = (efuse & opp_data->soc_data->efuse_mask);
  206. efuse >>= opp_data->soc_data->efuse_shift;
  207. *efuse_value = opp_data->soc_data->efuse_xlate(opp_data, efuse);
  208. return 0;
  209. }
  210. /**
  211. * ti_cpufreq_get_rev() - Parse and return rev value present on SoC
  212. * @opp_data: pointer to ti_cpufreq_data context
  213. * @revision_value: Set to the value parsed from revision register
  214. *
  215. * Returns error code if revision not read properly.
  216. */
  217. static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data,
  218. u32 *revision_value)
  219. {
  220. struct device *dev = opp_data->cpu_dev;
  221. u32 revision;
  222. int ret;
  223. ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset,
  224. &revision);
  225. if (ret == -EIO) {
  226. /* not a syscon register! */
  227. void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +
  228. opp_data->soc_data->rev_offset, 4);
  229. if (!regs)
  230. return -ENOMEM;
  231. revision = readl(regs);
  232. iounmap(regs);
  233. }
  234. else if (ret) {
  235. dev_err(dev,
  236. "Failed to read the revision number from syscon: %d\n",
  237. ret);
  238. return ret;
  239. }
  240. *revision_value = BIT((revision >> REVISION_SHIFT) & REVISION_MASK);
  241. return 0;
  242. }
  243. static int ti_cpufreq_setup_syscon_register(struct ti_cpufreq_data *opp_data)
  244. {
  245. struct device *dev = opp_data->cpu_dev;
  246. struct device_node *np = opp_data->opp_node;
  247. opp_data->syscon = syscon_regmap_lookup_by_phandle(np,
  248. "syscon");
  249. if (IS_ERR(opp_data->syscon)) {
  250. dev_err(dev,
  251. "\"syscon\" is missing, cannot use OPPv2 table.\n");
  252. return PTR_ERR(opp_data->syscon);
  253. }
  254. return 0;
  255. }
  256. static const struct of_device_id ti_cpufreq_of_match[] = {
  257. { .compatible = "ti,am33xx", .data = &am3x_soc_data, },
  258. { .compatible = "ti,am3517", .data = &am3517_soc_data, },
  259. { .compatible = "ti,am43", .data = &am4x_soc_data, },
  260. { .compatible = "ti,dra7", .data = &dra7_soc_data },
  261. { .compatible = "ti,omap34xx", .data = &omap34xx_soc_data, },
  262. { .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, },
  263. /* legacy */
  264. { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, },
  265. { .compatible = "ti,omap3630", .data = &omap36xx_soc_data, },
  266. {},
  267. };
  268. static const struct of_device_id *ti_cpufreq_match_node(void)
  269. {
  270. struct device_node *np;
  271. const struct of_device_id *match;
  272. np = of_find_node_by_path("/");
  273. match = of_match_node(ti_cpufreq_of_match, np);
  274. of_node_put(np);
  275. return match;
  276. }
  277. static int ti_cpufreq_probe(struct platform_device *pdev)
  278. {
  279. u32 version[VERSION_COUNT];
  280. const struct of_device_id *match;
  281. struct opp_table *ti_opp_table;
  282. struct ti_cpufreq_data *opp_data;
  283. const char * const default_reg_names[] = {"vdd", "vbb"};
  284. int ret;
  285. match = dev_get_platdata(&pdev->dev);
  286. if (!match)
  287. return -ENODEV;
  288. opp_data = devm_kzalloc(&pdev->dev, sizeof(*opp_data), GFP_KERNEL);
  289. if (!opp_data)
  290. return -ENOMEM;
  291. opp_data->soc_data = match->data;
  292. opp_data->cpu_dev = get_cpu_device(0);
  293. if (!opp_data->cpu_dev) {
  294. pr_err("%s: Failed to get device for CPU0\n", __func__);
  295. return -ENODEV;
  296. }
  297. opp_data->opp_node = dev_pm_opp_of_get_opp_desc_node(opp_data->cpu_dev);
  298. if (!opp_data->opp_node) {
  299. dev_info(opp_data->cpu_dev,
  300. "OPP-v2 not supported, cpufreq-dt will attempt to use legacy tables.\n");
  301. goto register_cpufreq_dt;
  302. }
  303. ret = ti_cpufreq_setup_syscon_register(opp_data);
  304. if (ret)
  305. goto fail_put_node;
  306. /*
  307. * OPPs determine whether or not they are supported based on
  308. * two metrics:
  309. * 0 - SoC Revision
  310. * 1 - eFuse value
  311. */
  312. ret = ti_cpufreq_get_rev(opp_data, &version[0]);
  313. if (ret)
  314. goto fail_put_node;
  315. ret = ti_cpufreq_get_efuse(opp_data, &version[1]);
  316. if (ret)
  317. goto fail_put_node;
  318. ti_opp_table = dev_pm_opp_set_supported_hw(opp_data->cpu_dev,
  319. version, VERSION_COUNT);
  320. if (IS_ERR(ti_opp_table)) {
  321. dev_err(opp_data->cpu_dev,
  322. "Failed to set supported hardware\n");
  323. ret = PTR_ERR(ti_opp_table);
  324. goto fail_put_node;
  325. }
  326. opp_data->opp_table = ti_opp_table;
  327. if (opp_data->soc_data->multi_regulator) {
  328. const char * const *reg_names = default_reg_names;
  329. if (opp_data->soc_data->reg_names)
  330. reg_names = opp_data->soc_data->reg_names;
  331. ti_opp_table = dev_pm_opp_set_regulators(opp_data->cpu_dev,
  332. reg_names,
  333. ARRAY_SIZE(default_reg_names));
  334. if (IS_ERR(ti_opp_table)) {
  335. dev_pm_opp_put_supported_hw(opp_data->opp_table);
  336. ret = PTR_ERR(ti_opp_table);
  337. goto fail_put_node;
  338. }
  339. }
  340. of_node_put(opp_data->opp_node);
  341. register_cpufreq_dt:
  342. platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
  343. return 0;
  344. fail_put_node:
  345. of_node_put(opp_data->opp_node);
  346. return ret;
  347. }
  348. static int ti_cpufreq_init(void)
  349. {
  350. const struct of_device_id *match;
  351. /* Check to ensure we are on a compatible platform */
  352. match = ti_cpufreq_match_node();
  353. if (match)
  354. platform_device_register_data(NULL, "ti-cpufreq", -1, match,
  355. sizeof(*match));
  356. return 0;
  357. }
  358. module_init(ti_cpufreq_init);
  359. static struct platform_driver ti_cpufreq_driver = {
  360. .probe = ti_cpufreq_probe,
  361. .driver = {
  362. .name = "ti-cpufreq",
  363. },
  364. };
  365. builtin_platform_driver(ti_cpufreq_driver);
  366. MODULE_DESCRIPTION("TI CPUFreq/OPP hw-supported driver");
  367. MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");
  368. MODULE_LICENSE("GPL v2");