speedstep-lib.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
  4. *
  5. * Library for common functions for Intel SpeedStep v.1 and v.2 support
  6. *
  7. * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
  8. */
  9. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/init.h>
  14. #include <linux/cpufreq.h>
  15. #include <asm/msr.h>
  16. #include <asm/tsc.h>
  17. #include "speedstep-lib.h"
  18. #define PFX "speedstep-lib: "
  19. #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
  20. static int relaxed_check;
  21. #else
  22. #define relaxed_check 0
  23. #endif
  24. /*********************************************************************
  25. * GET PROCESSOR CORE SPEED IN KHZ *
  26. *********************************************************************/
  27. static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
  28. {
  29. /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
  30. static const struct {
  31. unsigned int ratio; /* Frequency Multiplier (x10) */
  32. u8 bitmap; /* power on configuration bits
  33. [27, 25:22] (in MSR 0x2a) */
  34. } msr_decode_mult[] = {
  35. { 30, 0x01 },
  36. { 35, 0x05 },
  37. { 40, 0x02 },
  38. { 45, 0x06 },
  39. { 50, 0x00 },
  40. { 55, 0x04 },
  41. { 60, 0x0b },
  42. { 65, 0x0f },
  43. { 70, 0x09 },
  44. { 75, 0x0d },
  45. { 80, 0x0a },
  46. { 85, 0x26 },
  47. { 90, 0x20 },
  48. { 100, 0x2b },
  49. { 0, 0xff } /* error or unknown value */
  50. };
  51. /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
  52. static const struct {
  53. unsigned int value; /* Front Side Bus speed in MHz */
  54. u8 bitmap; /* power on configuration bits [18: 19]
  55. (in MSR 0x2a) */
  56. } msr_decode_fsb[] = {
  57. { 66, 0x0 },
  58. { 100, 0x2 },
  59. { 133, 0x1 },
  60. { 0, 0xff}
  61. };
  62. u32 msr_lo, msr_tmp;
  63. int i = 0, j = 0;
  64. /* read MSR 0x2a - we only need the low 32 bits */
  65. rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
  66. pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
  67. msr_tmp = msr_lo;
  68. /* decode the FSB */
  69. msr_tmp &= 0x00c0000;
  70. msr_tmp >>= 18;
  71. while (msr_tmp != msr_decode_fsb[i].bitmap) {
  72. if (msr_decode_fsb[i].bitmap == 0xff)
  73. return 0;
  74. i++;
  75. }
  76. /* decode the multiplier */
  77. if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) {
  78. pr_debug("workaround for early PIIIs\n");
  79. msr_lo &= 0x03c00000;
  80. } else
  81. msr_lo &= 0x0bc00000;
  82. msr_lo >>= 22;
  83. while (msr_lo != msr_decode_mult[j].bitmap) {
  84. if (msr_decode_mult[j].bitmap == 0xff)
  85. return 0;
  86. j++;
  87. }
  88. pr_debug("speed is %u\n",
  89. (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
  90. return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100;
  91. }
  92. static unsigned int pentiumM_get_frequency(void)
  93. {
  94. u32 msr_lo, msr_tmp;
  95. rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
  96. pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
  97. /* see table B-2 of 24547212.pdf */
  98. if (msr_lo & 0x00040000) {
  99. printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n",
  100. msr_lo, msr_tmp);
  101. return 0;
  102. }
  103. msr_tmp = (msr_lo >> 22) & 0x1f;
  104. pr_debug("bits 22-26 are 0x%x, speed is %u\n",
  105. msr_tmp, (msr_tmp * 100 * 1000));
  106. return msr_tmp * 100 * 1000;
  107. }
  108. static unsigned int pentium_core_get_frequency(void)
  109. {
  110. u32 fsb = 0;
  111. u32 msr_lo, msr_tmp;
  112. int ret;
  113. rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
  114. /* see table B-2 of 25366920.pdf */
  115. switch (msr_lo & 0x07) {
  116. case 5:
  117. fsb = 100000;
  118. break;
  119. case 1:
  120. fsb = 133333;
  121. break;
  122. case 3:
  123. fsb = 166667;
  124. break;
  125. case 2:
  126. fsb = 200000;
  127. break;
  128. case 0:
  129. fsb = 266667;
  130. break;
  131. case 4:
  132. fsb = 333333;
  133. break;
  134. default:
  135. pr_err("PCORE - MSR_FSB_FREQ undefined value\n");
  136. }
  137. rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
  138. pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
  139. msr_lo, msr_tmp);
  140. msr_tmp = (msr_lo >> 22) & 0x1f;
  141. pr_debug("bits 22-26 are 0x%x, speed is %u\n",
  142. msr_tmp, (msr_tmp * fsb));
  143. ret = (msr_tmp * fsb);
  144. return ret;
  145. }
  146. static unsigned int pentium4_get_frequency(void)
  147. {
  148. struct cpuinfo_x86 *c = &boot_cpu_data;
  149. u32 msr_lo, msr_hi, mult;
  150. unsigned int fsb = 0;
  151. unsigned int ret;
  152. u8 fsb_code;
  153. /* Pentium 4 Model 0 and 1 do not have the Core Clock Frequency
  154. * to System Bus Frequency Ratio Field in the Processor Frequency
  155. * Configuration Register of the MSR. Therefore the current
  156. * frequency cannot be calculated and has to be measured.
  157. */
  158. if (c->x86_model < 2)
  159. return cpu_khz;
  160. rdmsr(0x2c, msr_lo, msr_hi);
  161. pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
  162. /* decode the FSB: see IA-32 Intel (C) Architecture Software
  163. * Developer's Manual, Volume 3: System Prgramming Guide,
  164. * revision #12 in Table B-1: MSRs in the Pentium 4 and
  165. * Intel Xeon Processors, on page B-4 and B-5.
  166. */
  167. fsb_code = (msr_lo >> 16) & 0x7;
  168. switch (fsb_code) {
  169. case 0:
  170. fsb = 100 * 1000;
  171. break;
  172. case 1:
  173. fsb = 13333 * 10;
  174. break;
  175. case 2:
  176. fsb = 200 * 1000;
  177. break;
  178. }
  179. if (!fsb)
  180. printk(KERN_DEBUG PFX "couldn't detect FSB speed. "
  181. "Please send an e-mail to <linux@brodo.de>\n");
  182. /* Multiplier. */
  183. mult = msr_lo >> 24;
  184. pr_debug("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n",
  185. fsb, mult, (fsb * mult));
  186. ret = (fsb * mult);
  187. return ret;
  188. }
  189. /* Warning: may get called from smp_call_function_single. */
  190. unsigned int speedstep_get_frequency(enum speedstep_processor processor)
  191. {
  192. switch (processor) {
  193. case SPEEDSTEP_CPU_PCORE:
  194. return pentium_core_get_frequency();
  195. case SPEEDSTEP_CPU_PM:
  196. return pentiumM_get_frequency();
  197. case SPEEDSTEP_CPU_P4D:
  198. case SPEEDSTEP_CPU_P4M:
  199. return pentium4_get_frequency();
  200. case SPEEDSTEP_CPU_PIII_T:
  201. case SPEEDSTEP_CPU_PIII_C:
  202. case SPEEDSTEP_CPU_PIII_C_EARLY:
  203. return pentium3_get_frequency(processor);
  204. default:
  205. return 0;
  206. }
  207. return 0;
  208. }
  209. EXPORT_SYMBOL_GPL(speedstep_get_frequency);
  210. /*********************************************************************
  211. * DETECT SPEEDSTEP-CAPABLE PROCESSOR *
  212. *********************************************************************/
  213. /* Keep in sync with the x86_cpu_id tables in the different modules */
  214. enum speedstep_processor speedstep_detect_processor(void)
  215. {
  216. struct cpuinfo_x86 *c = &cpu_data(0);
  217. u32 ebx, msr_lo, msr_hi;
  218. pr_debug("x86: %x, model: %x\n", c->x86, c->x86_model);
  219. if ((c->x86_vendor != X86_VENDOR_INTEL) ||
  220. ((c->x86 != 6) && (c->x86 != 0xF)))
  221. return 0;
  222. if (c->x86 == 0xF) {
  223. /* Intel Mobile Pentium 4-M
  224. * or Intel Mobile Pentium 4 with 533 MHz FSB */
  225. if (c->x86_model != 2)
  226. return 0;
  227. ebx = cpuid_ebx(0x00000001);
  228. ebx &= 0x000000FF;
  229. pr_debug("ebx value is %x, x86_stepping is %x\n", ebx, c->x86_stepping);
  230. switch (c->x86_stepping) {
  231. case 4:
  232. /*
  233. * B-stepping [M-P4-M]
  234. * sample has ebx = 0x0f, production has 0x0e.
  235. */
  236. if ((ebx == 0x0e) || (ebx == 0x0f))
  237. return SPEEDSTEP_CPU_P4M;
  238. break;
  239. case 7:
  240. /*
  241. * C-stepping [M-P4-M]
  242. * needs to have ebx=0x0e, else it's a celeron:
  243. * cf. 25130917.pdf / page 7, footnote 5 even
  244. * though 25072120.pdf / page 7 doesn't say
  245. * samples are only of B-stepping...
  246. */
  247. if (ebx == 0x0e)
  248. return SPEEDSTEP_CPU_P4M;
  249. break;
  250. case 9:
  251. /*
  252. * D-stepping [M-P4-M or M-P4/533]
  253. *
  254. * this is totally strange: CPUID 0x0F29 is
  255. * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
  256. * The latter need to be sorted out as they don't
  257. * support speedstep.
  258. * Celerons with CPUID 0x0F29 may have either
  259. * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
  260. * specific.
  261. * M-P4-Ms may have either ebx=0xe or 0xf [see above]
  262. * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
  263. * also, M-P4M HTs have ebx=0x8, too
  264. * For now, they are distinguished by the model_id
  265. * string
  266. */
  267. if ((ebx == 0x0e) ||
  268. (strstr(c->x86_model_id,
  269. "Mobile Intel(R) Pentium(R) 4") != NULL))
  270. return SPEEDSTEP_CPU_P4M;
  271. break;
  272. default:
  273. break;
  274. }
  275. return 0;
  276. }
  277. switch (c->x86_model) {
  278. case 0x0B: /* Intel PIII [Tualatin] */
  279. /* cpuid_ebx(1) is 0x04 for desktop PIII,
  280. * 0x06 for mobile PIII-M */
  281. ebx = cpuid_ebx(0x00000001);
  282. pr_debug("ebx is %x\n", ebx);
  283. ebx &= 0x000000FF;
  284. if (ebx != 0x06)
  285. return 0;
  286. /* So far all PIII-M processors support SpeedStep. See
  287. * Intel's 24540640.pdf of June 2003
  288. */
  289. return SPEEDSTEP_CPU_PIII_T;
  290. case 0x08: /* Intel PIII [Coppermine] */
  291. /* all mobile PIII Coppermines have FSB 100 MHz
  292. * ==> sort out a few desktop PIIIs. */
  293. rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
  294. pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
  295. msr_lo, msr_hi);
  296. msr_lo &= 0x00c0000;
  297. if (msr_lo != 0x0080000)
  298. return 0;
  299. /*
  300. * If the processor is a mobile version,
  301. * platform ID has bit 50 set
  302. * it has SpeedStep technology if either
  303. * bit 56 or 57 is set
  304. */
  305. rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
  306. pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
  307. msr_lo, msr_hi);
  308. if ((msr_hi & (1<<18)) &&
  309. (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
  310. if (c->x86_stepping == 0x01) {
  311. pr_debug("early PIII version\n");
  312. return SPEEDSTEP_CPU_PIII_C_EARLY;
  313. } else
  314. return SPEEDSTEP_CPU_PIII_C;
  315. }
  316. fallthrough;
  317. default:
  318. return 0;
  319. }
  320. }
  321. EXPORT_SYMBOL_GPL(speedstep_detect_processor);
  322. /*********************************************************************
  323. * DETECT SPEEDSTEP SPEEDS *
  324. *********************************************************************/
  325. unsigned int speedstep_get_freqs(enum speedstep_processor processor,
  326. unsigned int *low_speed,
  327. unsigned int *high_speed,
  328. unsigned int *transition_latency,
  329. void (*set_state) (unsigned int state))
  330. {
  331. unsigned int prev_speed;
  332. unsigned int ret = 0;
  333. unsigned long flags;
  334. ktime_t tv1, tv2;
  335. if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
  336. return -EINVAL;
  337. pr_debug("trying to determine both speeds\n");
  338. /* get current speed */
  339. prev_speed = speedstep_get_frequency(processor);
  340. if (!prev_speed)
  341. return -EIO;
  342. pr_debug("previous speed is %u\n", prev_speed);
  343. preempt_disable();
  344. local_irq_save(flags);
  345. /* switch to low state */
  346. set_state(SPEEDSTEP_LOW);
  347. *low_speed = speedstep_get_frequency(processor);
  348. if (!*low_speed) {
  349. ret = -EIO;
  350. goto out;
  351. }
  352. pr_debug("low speed is %u\n", *low_speed);
  353. /* start latency measurement */
  354. if (transition_latency)
  355. tv1 = ktime_get();
  356. /* switch to high state */
  357. set_state(SPEEDSTEP_HIGH);
  358. /* end latency measurement */
  359. if (transition_latency)
  360. tv2 = ktime_get();
  361. *high_speed = speedstep_get_frequency(processor);
  362. if (!*high_speed) {
  363. ret = -EIO;
  364. goto out;
  365. }
  366. pr_debug("high speed is %u\n", *high_speed);
  367. if (*low_speed == *high_speed) {
  368. ret = -ENODEV;
  369. goto out;
  370. }
  371. /* switch to previous state, if necessary */
  372. if (*high_speed != prev_speed)
  373. set_state(SPEEDSTEP_LOW);
  374. if (transition_latency) {
  375. *transition_latency = ktime_to_us(ktime_sub(tv2, tv1));
  376. pr_debug("transition latency is %u uSec\n", *transition_latency);
  377. /* convert uSec to nSec and add 20% for safety reasons */
  378. *transition_latency *= 1200;
  379. /* check if the latency measurement is too high or too low
  380. * and set it to a safe value (500uSec) in that case
  381. */
  382. if (*transition_latency > 10000000 ||
  383. *transition_latency < 50000) {
  384. pr_warn("frequency transition measured seems out of range (%u nSec), falling back to a safe one of %u nSec\n",
  385. *transition_latency, 500000);
  386. *transition_latency = 500000;
  387. }
  388. }
  389. out:
  390. local_irq_restore(flags);
  391. preempt_enable();
  392. return ret;
  393. }
  394. EXPORT_SYMBOL_GPL(speedstep_get_freqs);
  395. #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
  396. module_param(relaxed_check, int, 0444);
  397. MODULE_PARM_DESC(relaxed_check,
  398. "Don't do all checks for speedstep capability.");
  399. #endif
  400. MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>");
  401. MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
  402. MODULE_LICENSE("GPL");