speedstep-centrino.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
  4. * M (part of the Centrino chipset).
  5. *
  6. * Since the original Pentium M, most new Intel CPUs support Enhanced
  7. * SpeedStep.
  8. *
  9. * Despite the "SpeedStep" in the name, this is almost entirely unlike
  10. * traditional SpeedStep.
  11. *
  12. * Modelled on speedstep.c
  13. *
  14. * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
  15. */
  16. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/init.h>
  20. #include <linux/cpufreq.h>
  21. #include <linux/sched.h> /* current */
  22. #include <linux/delay.h>
  23. #include <linux/compiler.h>
  24. #include <linux/gfp.h>
  25. #include <asm/msr.h>
  26. #include <asm/processor.h>
  27. #include <asm/cpufeature.h>
  28. #include <asm/cpu_device_id.h>
  29. #define MAINTAINER "linux-pm@vger.kernel.org"
  30. #define INTEL_MSR_RANGE (0xffff)
  31. struct cpu_id
  32. {
  33. __u8 x86; /* CPU family */
  34. __u8 x86_model; /* model */
  35. __u8 x86_stepping; /* stepping */
  36. };
  37. enum {
  38. CPU_BANIAS,
  39. CPU_DOTHAN_A1,
  40. CPU_DOTHAN_A2,
  41. CPU_DOTHAN_B0,
  42. CPU_MP4HT_D0,
  43. CPU_MP4HT_E0,
  44. };
  45. static const struct cpu_id cpu_ids[] = {
  46. [CPU_BANIAS] = { 6, 9, 5 },
  47. [CPU_DOTHAN_A1] = { 6, 13, 1 },
  48. [CPU_DOTHAN_A2] = { 6, 13, 2 },
  49. [CPU_DOTHAN_B0] = { 6, 13, 6 },
  50. [CPU_MP4HT_D0] = {15, 3, 4 },
  51. [CPU_MP4HT_E0] = {15, 4, 1 },
  52. };
  53. #define N_IDS ARRAY_SIZE(cpu_ids)
  54. struct cpu_model
  55. {
  56. const struct cpu_id *cpu_id;
  57. const char *model_name;
  58. unsigned max_freq; /* max clock in kHz */
  59. struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
  60. };
  61. static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
  62. const struct cpu_id *x);
  63. /* Operating points for current CPU */
  64. static DEFINE_PER_CPU(struct cpu_model *, centrino_model);
  65. static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu);
  66. static struct cpufreq_driver centrino_driver;
  67. #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
  68. /* Computes the correct form for IA32_PERF_CTL MSR for a particular
  69. frequency/voltage operating point; frequency in MHz, volts in mV.
  70. This is stored as "driver_data" in the structure. */
  71. #define OP(mhz, mv) \
  72. { \
  73. .frequency = (mhz) * 1000, \
  74. .driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16) \
  75. }
  76. /*
  77. * These voltage tables were derived from the Intel Pentium M
  78. * datasheet, document 25261202.pdf, Table 5. I have verified they
  79. * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
  80. * M.
  81. */
  82. /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
  83. static struct cpufreq_frequency_table banias_900[] =
  84. {
  85. OP(600, 844),
  86. OP(800, 988),
  87. OP(900, 1004),
  88. { .frequency = CPUFREQ_TABLE_END }
  89. };
  90. /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
  91. static struct cpufreq_frequency_table banias_1000[] =
  92. {
  93. OP(600, 844),
  94. OP(800, 972),
  95. OP(900, 988),
  96. OP(1000, 1004),
  97. { .frequency = CPUFREQ_TABLE_END }
  98. };
  99. /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
  100. static struct cpufreq_frequency_table banias_1100[] =
  101. {
  102. OP( 600, 956),
  103. OP( 800, 1020),
  104. OP( 900, 1100),
  105. OP(1000, 1164),
  106. OP(1100, 1180),
  107. { .frequency = CPUFREQ_TABLE_END }
  108. };
  109. /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
  110. static struct cpufreq_frequency_table banias_1200[] =
  111. {
  112. OP( 600, 956),
  113. OP( 800, 1004),
  114. OP( 900, 1020),
  115. OP(1000, 1100),
  116. OP(1100, 1164),
  117. OP(1200, 1180),
  118. { .frequency = CPUFREQ_TABLE_END }
  119. };
  120. /* Intel Pentium M processor 1.30GHz (Banias) */
  121. static struct cpufreq_frequency_table banias_1300[] =
  122. {
  123. OP( 600, 956),
  124. OP( 800, 1260),
  125. OP(1000, 1292),
  126. OP(1200, 1356),
  127. OP(1300, 1388),
  128. { .frequency = CPUFREQ_TABLE_END }
  129. };
  130. /* Intel Pentium M processor 1.40GHz (Banias) */
  131. static struct cpufreq_frequency_table banias_1400[] =
  132. {
  133. OP( 600, 956),
  134. OP( 800, 1180),
  135. OP(1000, 1308),
  136. OP(1200, 1436),
  137. OP(1400, 1484),
  138. { .frequency = CPUFREQ_TABLE_END }
  139. };
  140. /* Intel Pentium M processor 1.50GHz (Banias) */
  141. static struct cpufreq_frequency_table banias_1500[] =
  142. {
  143. OP( 600, 956),
  144. OP( 800, 1116),
  145. OP(1000, 1228),
  146. OP(1200, 1356),
  147. OP(1400, 1452),
  148. OP(1500, 1484),
  149. { .frequency = CPUFREQ_TABLE_END }
  150. };
  151. /* Intel Pentium M processor 1.60GHz (Banias) */
  152. static struct cpufreq_frequency_table banias_1600[] =
  153. {
  154. OP( 600, 956),
  155. OP( 800, 1036),
  156. OP(1000, 1164),
  157. OP(1200, 1276),
  158. OP(1400, 1420),
  159. OP(1600, 1484),
  160. { .frequency = CPUFREQ_TABLE_END }
  161. };
  162. /* Intel Pentium M processor 1.70GHz (Banias) */
  163. static struct cpufreq_frequency_table banias_1700[] =
  164. {
  165. OP( 600, 956),
  166. OP( 800, 1004),
  167. OP(1000, 1116),
  168. OP(1200, 1228),
  169. OP(1400, 1308),
  170. OP(1700, 1484),
  171. { .frequency = CPUFREQ_TABLE_END }
  172. };
  173. #undef OP
  174. #define _BANIAS(cpuid, max, name) \
  175. { .cpu_id = cpuid, \
  176. .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
  177. .max_freq = (max)*1000, \
  178. .op_points = banias_##max, \
  179. }
  180. #define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
  181. /* CPU models, their operating frequency range, and freq/voltage
  182. operating points */
  183. static struct cpu_model models[] =
  184. {
  185. _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
  186. BANIAS(1000),
  187. BANIAS(1100),
  188. BANIAS(1200),
  189. BANIAS(1300),
  190. BANIAS(1400),
  191. BANIAS(1500),
  192. BANIAS(1600),
  193. BANIAS(1700),
  194. /* NULL model_name is a wildcard */
  195. { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
  196. { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
  197. { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
  198. { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
  199. { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
  200. { NULL, }
  201. };
  202. #undef _BANIAS
  203. #undef BANIAS
  204. static int centrino_cpu_init_table(struct cpufreq_policy *policy)
  205. {
  206. struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
  207. struct cpu_model *model;
  208. for(model = models; model->cpu_id != NULL; model++)
  209. if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
  210. (model->model_name == NULL ||
  211. strcmp(cpu->x86_model_id, model->model_name) == 0))
  212. break;
  213. if (model->cpu_id == NULL) {
  214. /* No match at all */
  215. pr_debug("no support for CPU model \"%s\": "
  216. "send /proc/cpuinfo to " MAINTAINER "\n",
  217. cpu->x86_model_id);
  218. return -ENOENT;
  219. }
  220. if (model->op_points == NULL) {
  221. /* Matched a non-match */
  222. pr_debug("no table support for CPU model \"%s\"\n",
  223. cpu->x86_model_id);
  224. pr_debug("try using the acpi-cpufreq driver\n");
  225. return -ENOENT;
  226. }
  227. per_cpu(centrino_model, policy->cpu) = model;
  228. pr_debug("found \"%s\": max frequency: %dkHz\n",
  229. model->model_name, model->max_freq);
  230. return 0;
  231. }
  232. #else
  233. static inline int centrino_cpu_init_table(struct cpufreq_policy *policy)
  234. {
  235. return -ENODEV;
  236. }
  237. #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
  238. static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
  239. const struct cpu_id *x)
  240. {
  241. if ((c->x86 == x->x86) &&
  242. (c->x86_model == x->x86_model) &&
  243. (c->x86_stepping == x->x86_stepping))
  244. return 1;
  245. return 0;
  246. }
  247. /* To be called only after centrino_model is initialized */
  248. static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
  249. {
  250. int i;
  251. /*
  252. * Extract clock in kHz from PERF_CTL value
  253. * for centrino, as some DSDTs are buggy.
  254. * Ideally, this can be done using the acpi_data structure.
  255. */
  256. if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) ||
  257. (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) ||
  258. (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) {
  259. msr = (msr >> 8) & 0xff;
  260. return msr * 100000;
  261. }
  262. if ((!per_cpu(centrino_model, cpu)) ||
  263. (!per_cpu(centrino_model, cpu)->op_points))
  264. return 0;
  265. msr &= 0xffff;
  266. for (i = 0;
  267. per_cpu(centrino_model, cpu)->op_points[i].frequency
  268. != CPUFREQ_TABLE_END;
  269. i++) {
  270. if (msr == per_cpu(centrino_model, cpu)->op_points[i].driver_data)
  271. return per_cpu(centrino_model, cpu)->
  272. op_points[i].frequency;
  273. }
  274. if (failsafe)
  275. return per_cpu(centrino_model, cpu)->op_points[i-1].frequency;
  276. else
  277. return 0;
  278. }
  279. /* Return the current CPU frequency in kHz */
  280. static unsigned int get_cur_freq(unsigned int cpu)
  281. {
  282. unsigned l, h;
  283. unsigned clock_freq;
  284. rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &l, &h);
  285. clock_freq = extract_clock(l, cpu, 0);
  286. if (unlikely(clock_freq == 0)) {
  287. /*
  288. * On some CPUs, we can see transient MSR values (which are
  289. * not present in _PSS), while CPU is doing some automatic
  290. * P-state transition (like TM2). Get the last freq set
  291. * in PERF_CTL.
  292. */
  293. rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &l, &h);
  294. clock_freq = extract_clock(l, cpu, 1);
  295. }
  296. return clock_freq;
  297. }
  298. static int centrino_cpu_init(struct cpufreq_policy *policy)
  299. {
  300. struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
  301. unsigned l, h;
  302. int i;
  303. /* Only Intel makes Enhanced Speedstep-capable CPUs */
  304. if (cpu->x86_vendor != X86_VENDOR_INTEL ||
  305. !cpu_has(cpu, X86_FEATURE_EST))
  306. return -ENODEV;
  307. if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
  308. centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
  309. if (policy->cpu != 0)
  310. return -ENODEV;
  311. for (i = 0; i < N_IDS; i++)
  312. if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
  313. break;
  314. if (i != N_IDS)
  315. per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i];
  316. if (!per_cpu(centrino_cpu, policy->cpu)) {
  317. pr_debug("found unsupported CPU with "
  318. "Enhanced SpeedStep: send /proc/cpuinfo to "
  319. MAINTAINER "\n");
  320. return -ENODEV;
  321. }
  322. if (centrino_cpu_init_table(policy))
  323. return -ENODEV;
  324. /* Check to see if Enhanced SpeedStep is enabled, and try to
  325. enable it if not. */
  326. rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  327. if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
  328. l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
  329. pr_debug("trying to enable Enhanced SpeedStep (%x)\n", l);
  330. wrmsr(MSR_IA32_MISC_ENABLE, l, h);
  331. /* check to see if it stuck */
  332. rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  333. if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
  334. pr_info("couldn't enable Enhanced SpeedStep\n");
  335. return -ENODEV;
  336. }
  337. }
  338. policy->cpuinfo.transition_latency = 10000;
  339. /* 10uS transition latency */
  340. policy->freq_table = per_cpu(centrino_model, policy->cpu)->op_points;
  341. return 0;
  342. }
  343. static int centrino_cpu_exit(struct cpufreq_policy *policy)
  344. {
  345. unsigned int cpu = policy->cpu;
  346. if (!per_cpu(centrino_model, cpu))
  347. return -ENODEV;
  348. per_cpu(centrino_model, cpu) = NULL;
  349. return 0;
  350. }
  351. /**
  352. * centrino_target - set a new CPUFreq policy
  353. * @policy: new policy
  354. * @index: index of target frequency
  355. *
  356. * Sets a new CPUFreq policy.
  357. */
  358. static int centrino_target(struct cpufreq_policy *policy, unsigned int index)
  359. {
  360. unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
  361. int retval = 0;
  362. unsigned int j, first_cpu;
  363. struct cpufreq_frequency_table *op_points;
  364. cpumask_var_t covered_cpus;
  365. if (unlikely(!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)))
  366. return -ENOMEM;
  367. if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
  368. retval = -ENODEV;
  369. goto out;
  370. }
  371. first_cpu = 1;
  372. op_points = &per_cpu(centrino_model, cpu)->op_points[index];
  373. for_each_cpu(j, policy->cpus) {
  374. int good_cpu;
  375. /*
  376. * Support for SMP systems.
  377. * Make sure we are running on CPU that wants to change freq
  378. */
  379. if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
  380. good_cpu = cpumask_any_and(policy->cpus,
  381. cpu_online_mask);
  382. else
  383. good_cpu = j;
  384. if (good_cpu >= nr_cpu_ids) {
  385. pr_debug("couldn't limit to CPUs in this domain\n");
  386. retval = -EAGAIN;
  387. if (first_cpu) {
  388. /* We haven't started the transition yet. */
  389. goto out;
  390. }
  391. break;
  392. }
  393. msr = op_points->driver_data;
  394. if (first_cpu) {
  395. rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h);
  396. if (msr == (oldmsr & 0xffff)) {
  397. pr_debug("no change needed - msr was and needs "
  398. "to be %x\n", oldmsr);
  399. retval = 0;
  400. goto out;
  401. }
  402. first_cpu = 0;
  403. /* all but 16 LSB are reserved, treat them with care */
  404. oldmsr &= ~0xffff;
  405. msr &= 0xffff;
  406. oldmsr |= msr;
  407. }
  408. wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr, h);
  409. if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
  410. break;
  411. cpumask_set_cpu(j, covered_cpus);
  412. }
  413. if (unlikely(retval)) {
  414. /*
  415. * We have failed halfway through the frequency change.
  416. * We have sent callbacks to policy->cpus and
  417. * MSRs have already been written on coverd_cpus.
  418. * Best effort undo..
  419. */
  420. for_each_cpu(j, covered_cpus)
  421. wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr, h);
  422. }
  423. retval = 0;
  424. out:
  425. free_cpumask_var(covered_cpus);
  426. return retval;
  427. }
  428. static struct cpufreq_driver centrino_driver = {
  429. .name = "centrino", /* should be speedstep-centrino,
  430. but there's a 16 char limit */
  431. .init = centrino_cpu_init,
  432. .exit = centrino_cpu_exit,
  433. .verify = cpufreq_generic_frequency_table_verify,
  434. .target_index = centrino_target,
  435. .get = get_cur_freq,
  436. .attr = cpufreq_generic_attr,
  437. };
  438. /*
  439. * This doesn't replace the detailed checks above because
  440. * the generic CPU IDs don't have a way to match for steppings
  441. * or ASCII model IDs.
  442. */
  443. static const struct x86_cpu_id centrino_ids[] = {
  444. X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, 9, X86_FEATURE_EST, NULL),
  445. X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, 13, X86_FEATURE_EST, NULL),
  446. X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 15, 3, X86_FEATURE_EST, NULL),
  447. X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 15, 4, X86_FEATURE_EST, NULL),
  448. {}
  449. };
  450. /**
  451. * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
  452. *
  453. * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
  454. * unsupported devices, -ENOENT if there's no voltage table for this
  455. * particular CPU model, -EINVAL on problems during initiatization,
  456. * and zero on success.
  457. *
  458. * This is quite picky. Not only does the CPU have to advertise the
  459. * "est" flag in the cpuid capability flags, we look for a specific
  460. * CPU model and stepping, and we need to have the exact model name in
  461. * our voltage tables. That is, be paranoid about not releasing
  462. * someone's valuable magic smoke.
  463. */
  464. static int __init centrino_init(void)
  465. {
  466. if (!x86_match_cpu(centrino_ids))
  467. return -ENODEV;
  468. return cpufreq_register_driver(&centrino_driver);
  469. }
  470. static void __exit centrino_exit(void)
  471. {
  472. cpufreq_unregister_driver(&centrino_driver);
  473. }
  474. MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
  475. MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
  476. MODULE_LICENSE ("GPL");
  477. late_initcall(centrino_init);
  478. module_exit(centrino_exit);