sparc-us2e-cpufreq.c 8.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* us2e_cpufreq.c: UltraSPARC-IIe cpu frequency support
  3. *
  4. * Copyright (C) 2003 David S. Miller (davem@redhat.com)
  5. *
  6. * Many thanks to Dominik Brodowski for fixing up the cpufreq
  7. * infrastructure in order to make this driver easier to implement.
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/sched.h>
  12. #include <linux/smp.h>
  13. #include <linux/cpufreq.h>
  14. #include <linux/threads.h>
  15. #include <linux/slab.h>
  16. #include <linux/delay.h>
  17. #include <linux/init.h>
  18. #include <asm/asi.h>
  19. #include <asm/timer.h>
  20. static struct cpufreq_driver *cpufreq_us2e_driver;
  21. struct us2e_freq_percpu_info {
  22. struct cpufreq_frequency_table table[6];
  23. };
  24. /* Indexed by cpu number. */
  25. static struct us2e_freq_percpu_info *us2e_freq_table;
  26. #define HBIRD_MEM_CNTL0_ADDR 0x1fe0000f010UL
  27. #define HBIRD_ESTAR_MODE_ADDR 0x1fe0000f080UL
  28. /* UltraSPARC-IIe has five dividers: 1, 2, 4, 6, and 8. These are controlled
  29. * in the ESTAR mode control register.
  30. */
  31. #define ESTAR_MODE_DIV_1 0x0000000000000000UL
  32. #define ESTAR_MODE_DIV_2 0x0000000000000001UL
  33. #define ESTAR_MODE_DIV_4 0x0000000000000003UL
  34. #define ESTAR_MODE_DIV_6 0x0000000000000002UL
  35. #define ESTAR_MODE_DIV_8 0x0000000000000004UL
  36. #define ESTAR_MODE_DIV_MASK 0x0000000000000007UL
  37. #define MCTRL0_SREFRESH_ENAB 0x0000000000010000UL
  38. #define MCTRL0_REFR_COUNT_MASK 0x0000000000007f00UL
  39. #define MCTRL0_REFR_COUNT_SHIFT 8
  40. #define MCTRL0_REFR_INTERVAL 7800
  41. #define MCTRL0_REFR_CLKS_P_CNT 64
  42. static unsigned long read_hbreg(unsigned long addr)
  43. {
  44. unsigned long ret;
  45. __asm__ __volatile__("ldxa [%1] %2, %0"
  46. : "=&r" (ret)
  47. : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
  48. return ret;
  49. }
  50. static void write_hbreg(unsigned long addr, unsigned long val)
  51. {
  52. __asm__ __volatile__("stxa %0, [%1] %2\n\t"
  53. "membar #Sync"
  54. : /* no outputs */
  55. : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
  56. : "memory");
  57. if (addr == HBIRD_ESTAR_MODE_ADDR) {
  58. /* Need to wait 16 clock cycles for the PLL to lock. */
  59. udelay(1);
  60. }
  61. }
  62. static void self_refresh_ctl(int enable)
  63. {
  64. unsigned long mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);
  65. if (enable)
  66. mctrl |= MCTRL0_SREFRESH_ENAB;
  67. else
  68. mctrl &= ~MCTRL0_SREFRESH_ENAB;
  69. write_hbreg(HBIRD_MEM_CNTL0_ADDR, mctrl);
  70. (void) read_hbreg(HBIRD_MEM_CNTL0_ADDR);
  71. }
  72. static void frob_mem_refresh(int cpu_slowing_down,
  73. unsigned long clock_tick,
  74. unsigned long old_divisor, unsigned long divisor)
  75. {
  76. unsigned long old_refr_count, refr_count, mctrl;
  77. refr_count = (clock_tick * MCTRL0_REFR_INTERVAL);
  78. refr_count /= (MCTRL0_REFR_CLKS_P_CNT * divisor * 1000000000UL);
  79. mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);
  80. old_refr_count = (mctrl & MCTRL0_REFR_COUNT_MASK)
  81. >> MCTRL0_REFR_COUNT_SHIFT;
  82. mctrl &= ~MCTRL0_REFR_COUNT_MASK;
  83. mctrl |= refr_count << MCTRL0_REFR_COUNT_SHIFT;
  84. write_hbreg(HBIRD_MEM_CNTL0_ADDR, mctrl);
  85. mctrl = read_hbreg(HBIRD_MEM_CNTL0_ADDR);
  86. if (cpu_slowing_down && !(mctrl & MCTRL0_SREFRESH_ENAB)) {
  87. unsigned long usecs;
  88. /* We have to wait for both refresh counts (old
  89. * and new) to go to zero.
  90. */
  91. usecs = (MCTRL0_REFR_CLKS_P_CNT *
  92. (refr_count + old_refr_count) *
  93. 1000000UL *
  94. old_divisor) / clock_tick;
  95. udelay(usecs + 1UL);
  96. }
  97. }
  98. static void us2e_transition(unsigned long estar, unsigned long new_bits,
  99. unsigned long clock_tick,
  100. unsigned long old_divisor, unsigned long divisor)
  101. {
  102. estar &= ~ESTAR_MODE_DIV_MASK;
  103. /* This is based upon the state transition diagram in the IIe manual. */
  104. if (old_divisor == 2 && divisor == 1) {
  105. self_refresh_ctl(0);
  106. write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
  107. frob_mem_refresh(0, clock_tick, old_divisor, divisor);
  108. } else if (old_divisor == 1 && divisor == 2) {
  109. frob_mem_refresh(1, clock_tick, old_divisor, divisor);
  110. write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
  111. self_refresh_ctl(1);
  112. } else if (old_divisor == 1 && divisor > 2) {
  113. us2e_transition(estar, ESTAR_MODE_DIV_2, clock_tick,
  114. 1, 2);
  115. us2e_transition(estar, new_bits, clock_tick,
  116. 2, divisor);
  117. } else if (old_divisor > 2 && divisor == 1) {
  118. us2e_transition(estar, ESTAR_MODE_DIV_2, clock_tick,
  119. old_divisor, 2);
  120. us2e_transition(estar, new_bits, clock_tick,
  121. 2, divisor);
  122. } else if (old_divisor < divisor) {
  123. frob_mem_refresh(0, clock_tick, old_divisor, divisor);
  124. write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
  125. } else if (old_divisor > divisor) {
  126. write_hbreg(HBIRD_ESTAR_MODE_ADDR, estar | new_bits);
  127. frob_mem_refresh(1, clock_tick, old_divisor, divisor);
  128. } else {
  129. BUG();
  130. }
  131. }
  132. static unsigned long index_to_estar_mode(unsigned int index)
  133. {
  134. switch (index) {
  135. case 0:
  136. return ESTAR_MODE_DIV_1;
  137. case 1:
  138. return ESTAR_MODE_DIV_2;
  139. case 2:
  140. return ESTAR_MODE_DIV_4;
  141. case 3:
  142. return ESTAR_MODE_DIV_6;
  143. case 4:
  144. return ESTAR_MODE_DIV_8;
  145. default:
  146. BUG();
  147. }
  148. }
  149. static unsigned long index_to_divisor(unsigned int index)
  150. {
  151. switch (index) {
  152. case 0:
  153. return 1;
  154. case 1:
  155. return 2;
  156. case 2:
  157. return 4;
  158. case 3:
  159. return 6;
  160. case 4:
  161. return 8;
  162. default:
  163. BUG();
  164. }
  165. }
  166. static unsigned long estar_to_divisor(unsigned long estar)
  167. {
  168. unsigned long ret;
  169. switch (estar & ESTAR_MODE_DIV_MASK) {
  170. case ESTAR_MODE_DIV_1:
  171. ret = 1;
  172. break;
  173. case ESTAR_MODE_DIV_2:
  174. ret = 2;
  175. break;
  176. case ESTAR_MODE_DIV_4:
  177. ret = 4;
  178. break;
  179. case ESTAR_MODE_DIV_6:
  180. ret = 6;
  181. break;
  182. case ESTAR_MODE_DIV_8:
  183. ret = 8;
  184. break;
  185. default:
  186. BUG();
  187. }
  188. return ret;
  189. }
  190. static void __us2e_freq_get(void *arg)
  191. {
  192. unsigned long *estar = arg;
  193. *estar = read_hbreg(HBIRD_ESTAR_MODE_ADDR);
  194. }
  195. static unsigned int us2e_freq_get(unsigned int cpu)
  196. {
  197. unsigned long clock_tick, estar;
  198. clock_tick = sparc64_get_clock_tick(cpu) / 1000;
  199. if (smp_call_function_single(cpu, __us2e_freq_get, &estar, 1))
  200. return 0;
  201. return clock_tick / estar_to_divisor(estar);
  202. }
  203. static void __us2e_freq_target(void *arg)
  204. {
  205. unsigned int cpu = smp_processor_id();
  206. unsigned int *index = arg;
  207. unsigned long new_bits, new_freq;
  208. unsigned long clock_tick, divisor, old_divisor, estar;
  209. new_freq = clock_tick = sparc64_get_clock_tick(cpu) / 1000;
  210. new_bits = index_to_estar_mode(*index);
  211. divisor = index_to_divisor(*index);
  212. new_freq /= divisor;
  213. estar = read_hbreg(HBIRD_ESTAR_MODE_ADDR);
  214. old_divisor = estar_to_divisor(estar);
  215. if (old_divisor != divisor) {
  216. us2e_transition(estar, new_bits, clock_tick * 1000,
  217. old_divisor, divisor);
  218. }
  219. }
  220. static int us2e_freq_target(struct cpufreq_policy *policy, unsigned int index)
  221. {
  222. unsigned int cpu = policy->cpu;
  223. return smp_call_function_single(cpu, __us2e_freq_target, &index, 1);
  224. }
  225. static int __init us2e_freq_cpu_init(struct cpufreq_policy *policy)
  226. {
  227. unsigned int cpu = policy->cpu;
  228. unsigned long clock_tick = sparc64_get_clock_tick(cpu) / 1000;
  229. struct cpufreq_frequency_table *table =
  230. &us2e_freq_table[cpu].table[0];
  231. table[0].driver_data = 0;
  232. table[0].frequency = clock_tick / 1;
  233. table[1].driver_data = 1;
  234. table[1].frequency = clock_tick / 2;
  235. table[2].driver_data = 2;
  236. table[2].frequency = clock_tick / 4;
  237. table[2].driver_data = 3;
  238. table[2].frequency = clock_tick / 6;
  239. table[2].driver_data = 4;
  240. table[2].frequency = clock_tick / 8;
  241. table[2].driver_data = 5;
  242. table[3].frequency = CPUFREQ_TABLE_END;
  243. policy->cpuinfo.transition_latency = 0;
  244. policy->cur = clock_tick;
  245. policy->freq_table = table;
  246. return 0;
  247. }
  248. static int us2e_freq_cpu_exit(struct cpufreq_policy *policy)
  249. {
  250. if (cpufreq_us2e_driver)
  251. us2e_freq_target(policy, 0);
  252. return 0;
  253. }
  254. static int __init us2e_freq_init(void)
  255. {
  256. unsigned long manuf, impl, ver;
  257. int ret;
  258. if (tlb_type != spitfire)
  259. return -ENODEV;
  260. __asm__("rdpr %%ver, %0" : "=r" (ver));
  261. manuf = ((ver >> 48) & 0xffff);
  262. impl = ((ver >> 32) & 0xffff);
  263. if (manuf == 0x17 && impl == 0x13) {
  264. struct cpufreq_driver *driver;
  265. ret = -ENOMEM;
  266. driver = kzalloc(sizeof(*driver), GFP_KERNEL);
  267. if (!driver)
  268. goto err_out;
  269. us2e_freq_table = kzalloc((NR_CPUS * sizeof(*us2e_freq_table)),
  270. GFP_KERNEL);
  271. if (!us2e_freq_table)
  272. goto err_out;
  273. driver->init = us2e_freq_cpu_init;
  274. driver->verify = cpufreq_generic_frequency_table_verify;
  275. driver->target_index = us2e_freq_target;
  276. driver->get = us2e_freq_get;
  277. driver->exit = us2e_freq_cpu_exit;
  278. strcpy(driver->name, "UltraSPARC-IIe");
  279. cpufreq_us2e_driver = driver;
  280. ret = cpufreq_register_driver(driver);
  281. if (ret)
  282. goto err_out;
  283. return 0;
  284. err_out:
  285. if (driver) {
  286. kfree(driver);
  287. cpufreq_us2e_driver = NULL;
  288. }
  289. kfree(us2e_freq_table);
  290. us2e_freq_table = NULL;
  291. return ret;
  292. }
  293. return -ENODEV;
  294. }
  295. static void __exit us2e_freq_exit(void)
  296. {
  297. if (cpufreq_us2e_driver) {
  298. cpufreq_unregister_driver(cpufreq_us2e_driver);
  299. kfree(cpufreq_us2e_driver);
  300. cpufreq_us2e_driver = NULL;
  301. kfree(us2e_freq_table);
  302. us2e_freq_table = NULL;
  303. }
  304. }
  305. MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
  306. MODULE_DESCRIPTION("cpufreq driver for UltraSPARC-IIe");
  307. MODULE_LICENSE("GPL");
  308. module_init(us2e_freq_init);
  309. module_exit(us2e_freq_exit);