s3c64xx-cpufreq.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2009 Wolfson Microelectronics plc
  4. *
  5. * S3C64xx CPUfreq Support
  6. */
  7. #define pr_fmt(fmt) "cpufreq: " fmt
  8. #include <linux/kernel.h>
  9. #include <linux/types.h>
  10. #include <linux/init.h>
  11. #include <linux/cpufreq.h>
  12. #include <linux/clk.h>
  13. #include <linux/err.h>
  14. #include <linux/regulator/consumer.h>
  15. #include <linux/module.h>
  16. static struct regulator *vddarm;
  17. static unsigned long regulator_latency;
  18. struct s3c64xx_dvfs {
  19. unsigned int vddarm_min;
  20. unsigned int vddarm_max;
  21. };
  22. static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
  23. [0] = { 1000000, 1150000 },
  24. [1] = { 1050000, 1150000 },
  25. [2] = { 1100000, 1150000 },
  26. [3] = { 1200000, 1350000 },
  27. [4] = { 1300000, 1350000 },
  28. };
  29. static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
  30. { 0, 0, 66000 },
  31. { 0, 0, 100000 },
  32. { 0, 0, 133000 },
  33. { 0, 1, 200000 },
  34. { 0, 1, 222000 },
  35. { 0, 1, 266000 },
  36. { 0, 2, 333000 },
  37. { 0, 2, 400000 },
  38. { 0, 2, 532000 },
  39. { 0, 2, 533000 },
  40. { 0, 3, 667000 },
  41. { 0, 4, 800000 },
  42. { 0, 0, CPUFREQ_TABLE_END },
  43. };
  44. static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
  45. unsigned int index)
  46. {
  47. struct s3c64xx_dvfs *dvfs;
  48. unsigned int old_freq, new_freq;
  49. int ret;
  50. old_freq = clk_get_rate(policy->clk) / 1000;
  51. new_freq = s3c64xx_freq_table[index].frequency;
  52. dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[index].driver_data];
  53. #ifdef CONFIG_REGULATOR
  54. if (vddarm && new_freq > old_freq) {
  55. ret = regulator_set_voltage(vddarm,
  56. dvfs->vddarm_min,
  57. dvfs->vddarm_max);
  58. if (ret != 0) {
  59. pr_err("Failed to set VDDARM for %dkHz: %d\n",
  60. new_freq, ret);
  61. return ret;
  62. }
  63. }
  64. #endif
  65. ret = clk_set_rate(policy->clk, new_freq * 1000);
  66. if (ret < 0) {
  67. pr_err("Failed to set rate %dkHz: %d\n",
  68. new_freq, ret);
  69. return ret;
  70. }
  71. #ifdef CONFIG_REGULATOR
  72. if (vddarm && new_freq < old_freq) {
  73. ret = regulator_set_voltage(vddarm,
  74. dvfs->vddarm_min,
  75. dvfs->vddarm_max);
  76. if (ret != 0) {
  77. pr_err("Failed to set VDDARM for %dkHz: %d\n",
  78. new_freq, ret);
  79. if (clk_set_rate(policy->clk, old_freq * 1000) < 0)
  80. pr_err("Failed to restore original clock rate\n");
  81. return ret;
  82. }
  83. }
  84. #endif
  85. pr_debug("Set actual frequency %lukHz\n",
  86. clk_get_rate(policy->clk) / 1000);
  87. return 0;
  88. }
  89. #ifdef CONFIG_REGULATOR
  90. static void s3c64xx_cpufreq_config_regulator(void)
  91. {
  92. int count, v, i, found;
  93. struct cpufreq_frequency_table *freq;
  94. struct s3c64xx_dvfs *dvfs;
  95. count = regulator_count_voltages(vddarm);
  96. if (count < 0) {
  97. pr_err("Unable to check supported voltages\n");
  98. }
  99. if (!count)
  100. goto out;
  101. cpufreq_for_each_valid_entry(freq, s3c64xx_freq_table) {
  102. dvfs = &s3c64xx_dvfs_table[freq->driver_data];
  103. found = 0;
  104. for (i = 0; i < count; i++) {
  105. v = regulator_list_voltage(vddarm, i);
  106. if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
  107. found = 1;
  108. }
  109. if (!found) {
  110. pr_debug("%dkHz unsupported by regulator\n",
  111. freq->frequency);
  112. freq->frequency = CPUFREQ_ENTRY_INVALID;
  113. }
  114. }
  115. out:
  116. /* Guess based on having to do an I2C/SPI write; in future we
  117. * will be able to query the regulator performance here. */
  118. regulator_latency = 1 * 1000 * 1000;
  119. }
  120. #endif
  121. static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
  122. {
  123. struct cpufreq_frequency_table *freq;
  124. if (policy->cpu != 0)
  125. return -EINVAL;
  126. policy->clk = clk_get(NULL, "armclk");
  127. if (IS_ERR(policy->clk)) {
  128. pr_err("Unable to obtain ARMCLK: %ld\n",
  129. PTR_ERR(policy->clk));
  130. return PTR_ERR(policy->clk);
  131. }
  132. #ifdef CONFIG_REGULATOR
  133. vddarm = regulator_get(NULL, "vddarm");
  134. if (IS_ERR(vddarm)) {
  135. pr_err("Failed to obtain VDDARM: %ld\n", PTR_ERR(vddarm));
  136. pr_err("Only frequency scaling available\n");
  137. vddarm = NULL;
  138. } else {
  139. s3c64xx_cpufreq_config_regulator();
  140. }
  141. #endif
  142. cpufreq_for_each_entry(freq, s3c64xx_freq_table) {
  143. unsigned long r;
  144. /* Check for frequencies we can generate */
  145. r = clk_round_rate(policy->clk, freq->frequency * 1000);
  146. r /= 1000;
  147. if (r != freq->frequency) {
  148. pr_debug("%dkHz unsupported by clock\n",
  149. freq->frequency);
  150. freq->frequency = CPUFREQ_ENTRY_INVALID;
  151. }
  152. /* If we have no regulator then assume startup
  153. * frequency is the maximum we can support. */
  154. if (!vddarm && freq->frequency > clk_get_rate(policy->clk) / 1000)
  155. freq->frequency = CPUFREQ_ENTRY_INVALID;
  156. }
  157. /* Datasheet says PLL stabalisation time (if we were to use
  158. * the PLLs, which we don't currently) is ~300us worst case,
  159. * but add some fudge.
  160. */
  161. cpufreq_generic_init(policy, s3c64xx_freq_table,
  162. (500 * 1000) + regulator_latency);
  163. return 0;
  164. }
  165. static struct cpufreq_driver s3c64xx_cpufreq_driver = {
  166. .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
  167. .verify = cpufreq_generic_frequency_table_verify,
  168. .target_index = s3c64xx_cpufreq_set_target,
  169. .get = cpufreq_generic_get,
  170. .init = s3c64xx_cpufreq_driver_init,
  171. .name = "s3c",
  172. };
  173. static int __init s3c64xx_cpufreq_init(void)
  174. {
  175. return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
  176. }
  177. module_init(s3c64xx_cpufreq_init);