s3c24xx-cpufreq.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2006-2008 Simtec Electronics
  4. * http://armlinux.simtec.co.uk/
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * S3C24XX CPU Frequency scaling
  8. */
  9. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10. #include <linux/init.h>
  11. #include <linux/module.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/ioport.h>
  14. #include <linux/cpufreq.h>
  15. #include <linux/cpu.h>
  16. #include <linux/clk.h>
  17. #include <linux/err.h>
  18. #include <linux/io.h>
  19. #include <linux/device.h>
  20. #include <linux/sysfs.h>
  21. #include <linux/slab.h>
  22. #include <linux/soc/samsung/s3c-cpufreq-core.h>
  23. #include <linux/soc/samsung/s3c-pm.h>
  24. #include <asm/mach/arch.h>
  25. #include <asm/mach/map.h>
  26. /* note, cpufreq support deals in kHz, no Hz */
  27. static struct cpufreq_driver s3c24xx_driver;
  28. static struct s3c_cpufreq_config cpu_cur;
  29. static struct s3c_iotimings s3c24xx_iotiming;
  30. static struct cpufreq_frequency_table *pll_reg;
  31. static unsigned int last_target = ~0;
  32. static unsigned int ftab_size;
  33. static struct cpufreq_frequency_table *ftab;
  34. static struct clk *_clk_mpll;
  35. static struct clk *_clk_xtal;
  36. static struct clk *clk_fclk;
  37. static struct clk *clk_hclk;
  38. static struct clk *clk_pclk;
  39. static struct clk *clk_arm;
  40. #ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS
  41. struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void)
  42. {
  43. return &cpu_cur;
  44. }
  45. struct s3c_iotimings *s3c_cpufreq_getiotimings(void)
  46. {
  47. return &s3c24xx_iotiming;
  48. }
  49. #endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS */
  50. static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg)
  51. {
  52. unsigned long fclk, pclk, hclk, armclk;
  53. cfg->freq.fclk = fclk = clk_get_rate(clk_fclk);
  54. cfg->freq.hclk = hclk = clk_get_rate(clk_hclk);
  55. cfg->freq.pclk = pclk = clk_get_rate(clk_pclk);
  56. cfg->freq.armclk = armclk = clk_get_rate(clk_arm);
  57. cfg->pll.driver_data = s3c24xx_read_mpllcon();
  58. cfg->pll.frequency = fclk;
  59. cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
  60. cfg->divs.h_divisor = fclk / hclk;
  61. cfg->divs.p_divisor = fclk / pclk;
  62. }
  63. static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg)
  64. {
  65. unsigned long pll = cfg->pll.frequency;
  66. cfg->freq.fclk = pll;
  67. cfg->freq.hclk = pll / cfg->divs.h_divisor;
  68. cfg->freq.pclk = pll / cfg->divs.p_divisor;
  69. /* convert hclk into 10ths of nanoseconds for io calcs */
  70. cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
  71. }
  72. static inline int closer(unsigned int target, unsigned int n, unsigned int c)
  73. {
  74. int diff_cur = abs(target - c);
  75. int diff_new = abs(target - n);
  76. return (diff_new < diff_cur);
  77. }
  78. static void s3c_cpufreq_show(const char *pfx,
  79. struct s3c_cpufreq_config *cfg)
  80. {
  81. s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n",
  82. pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk,
  83. cfg->freq.hclk, cfg->divs.h_divisor,
  84. cfg->freq.pclk, cfg->divs.p_divisor);
  85. }
  86. /* functions to wrapper the driver info calls to do the cpu specific work */
  87. static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg)
  88. {
  89. if (cfg->info->set_iotiming)
  90. (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming);
  91. }
  92. static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg)
  93. {
  94. if (cfg->info->calc_iotiming)
  95. return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming);
  96. return 0;
  97. }
  98. static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
  99. {
  100. (cfg->info->set_refresh)(cfg);
  101. }
  102. static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
  103. {
  104. (cfg->info->set_divs)(cfg);
  105. }
  106. static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
  107. {
  108. return (cfg->info->calc_divs)(cfg);
  109. }
  110. static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg)
  111. {
  112. cfg->mpll = _clk_mpll;
  113. (cfg->info->set_fvco)(cfg);
  114. }
  115. static inline void s3c_cpufreq_updateclk(struct clk *clk,
  116. unsigned int freq)
  117. {
  118. clk_set_rate(clk, freq);
  119. }
  120. static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
  121. unsigned int target_freq,
  122. struct cpufreq_frequency_table *pll)
  123. {
  124. struct s3c_cpufreq_freqs freqs;
  125. struct s3c_cpufreq_config cpu_new;
  126. unsigned long flags;
  127. cpu_new = cpu_cur; /* copy new from current */
  128. s3c_cpufreq_show("cur", &cpu_cur);
  129. /* TODO - check for DMA currently outstanding */
  130. cpu_new.pll = pll ? *pll : cpu_cur.pll;
  131. if (pll)
  132. freqs.pll_changing = 1;
  133. /* update our frequencies */
  134. cpu_new.freq.armclk = target_freq;
  135. cpu_new.freq.fclk = cpu_new.pll.frequency;
  136. if (s3c_cpufreq_calcdivs(&cpu_new) < 0) {
  137. pr_err("no divisors for %d\n", target_freq);
  138. goto err_notpossible;
  139. }
  140. s3c_freq_dbg("%s: got divs\n", __func__);
  141. s3c_cpufreq_calc(&cpu_new);
  142. s3c_freq_dbg("%s: calculated frequencies for new\n", __func__);
  143. if (cpu_new.freq.hclk != cpu_cur.freq.hclk) {
  144. if (s3c_cpufreq_calcio(&cpu_new) < 0) {
  145. pr_err("%s: no IO timings\n", __func__);
  146. goto err_notpossible;
  147. }
  148. }
  149. s3c_cpufreq_show("new", &cpu_new);
  150. /* setup our cpufreq parameters */
  151. freqs.old = cpu_cur.freq;
  152. freqs.new = cpu_new.freq;
  153. freqs.freqs.old = cpu_cur.freq.armclk / 1000;
  154. freqs.freqs.new = cpu_new.freq.armclk / 1000;
  155. /* update f/h/p clock settings before we issue the change
  156. * notification, so that drivers do not need to do anything
  157. * special if they want to recalculate on CPUFREQ_PRECHANGE. */
  158. s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency);
  159. s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk);
  160. s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk);
  161. s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk);
  162. /* start the frequency change */
  163. cpufreq_freq_transition_begin(policy, &freqs.freqs);
  164. /* If hclk is staying the same, then we do not need to
  165. * re-write the IO or the refresh timings whilst we are changing
  166. * speed. */
  167. local_irq_save(flags);
  168. /* is our memory clock slowing down? */
  169. if (cpu_new.freq.hclk < cpu_cur.freq.hclk) {
  170. s3c_cpufreq_setrefresh(&cpu_new);
  171. s3c_cpufreq_setio(&cpu_new);
  172. }
  173. if (cpu_new.freq.fclk == cpu_cur.freq.fclk) {
  174. /* not changing PLL, just set the divisors */
  175. s3c_cpufreq_setdivs(&cpu_new);
  176. } else {
  177. if (cpu_new.freq.fclk < cpu_cur.freq.fclk) {
  178. /* slow the cpu down, then set divisors */
  179. s3c_cpufreq_setfvco(&cpu_new);
  180. s3c_cpufreq_setdivs(&cpu_new);
  181. } else {
  182. /* set the divisors, then speed up */
  183. s3c_cpufreq_setdivs(&cpu_new);
  184. s3c_cpufreq_setfvco(&cpu_new);
  185. }
  186. }
  187. /* did our memory clock speed up */
  188. if (cpu_new.freq.hclk > cpu_cur.freq.hclk) {
  189. s3c_cpufreq_setrefresh(&cpu_new);
  190. s3c_cpufreq_setio(&cpu_new);
  191. }
  192. /* update our current settings */
  193. cpu_cur = cpu_new;
  194. local_irq_restore(flags);
  195. /* notify everyone we've done this */
  196. cpufreq_freq_transition_end(policy, &freqs.freqs, 0);
  197. s3c_freq_dbg("%s: finished\n", __func__);
  198. return 0;
  199. err_notpossible:
  200. pr_err("no compatible settings for %d\n", target_freq);
  201. return -EINVAL;
  202. }
  203. /* s3c_cpufreq_target
  204. *
  205. * called by the cpufreq core to adjust the frequency that the CPU
  206. * is currently running at.
  207. */
  208. static int s3c_cpufreq_target(struct cpufreq_policy *policy,
  209. unsigned int target_freq,
  210. unsigned int relation)
  211. {
  212. struct cpufreq_frequency_table *pll;
  213. unsigned int index;
  214. /* avoid repeated calls which cause a needless amout of duplicated
  215. * logging output (and CPU time as the calculation process is
  216. * done) */
  217. if (target_freq == last_target)
  218. return 0;
  219. last_target = target_freq;
  220. s3c_freq_dbg("%s: policy %p, target %u, relation %u\n",
  221. __func__, policy, target_freq, relation);
  222. if (ftab) {
  223. index = cpufreq_frequency_table_target(policy, target_freq,
  224. relation);
  225. s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__,
  226. target_freq, index, ftab[index].frequency);
  227. target_freq = ftab[index].frequency;
  228. }
  229. target_freq *= 1000; /* convert target to Hz */
  230. /* find the settings for our new frequency */
  231. if (!pll_reg || cpu_cur.lock_pll) {
  232. /* either we've not got any PLL values, or we've locked
  233. * to the current one. */
  234. pll = NULL;
  235. } else {
  236. struct cpufreq_policy tmp_policy;
  237. /* we keep the cpu pll table in Hz, to ensure we get an
  238. * accurate value for the PLL output. */
  239. tmp_policy.min = policy->min * 1000;
  240. tmp_policy.max = policy->max * 1000;
  241. tmp_policy.cpu = policy->cpu;
  242. tmp_policy.freq_table = pll_reg;
  243. /* cpufreq_frequency_table_target returns the index
  244. * of the table entry, not the value of
  245. * the table entry's index field. */
  246. index = cpufreq_frequency_table_target(&tmp_policy, target_freq,
  247. relation);
  248. pll = pll_reg + index;
  249. s3c_freq_dbg("%s: target %u => %u\n",
  250. __func__, target_freq, pll->frequency);
  251. target_freq = pll->frequency;
  252. }
  253. return s3c_cpufreq_settarget(policy, target_freq, pll);
  254. }
  255. struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name)
  256. {
  257. struct clk *clk;
  258. clk = clk_get(dev, name);
  259. if (IS_ERR(clk))
  260. pr_err("failed to get clock '%s'\n", name);
  261. return clk;
  262. }
  263. static int s3c_cpufreq_init(struct cpufreq_policy *policy)
  264. {
  265. policy->clk = clk_arm;
  266. policy->cpuinfo.transition_latency = cpu_cur.info->latency;
  267. policy->freq_table = ftab;
  268. return 0;
  269. }
  270. static int __init s3c_cpufreq_initclks(void)
  271. {
  272. _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll");
  273. _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal");
  274. clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk");
  275. clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk");
  276. clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk");
  277. clk_arm = s3c_cpufreq_clk_get(NULL, "armclk");
  278. if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) ||
  279. IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) {
  280. pr_err("%s: could not get clock(s)\n", __func__);
  281. return -ENOENT;
  282. }
  283. pr_info("%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n",
  284. __func__,
  285. clk_get_rate(clk_fclk) / 1000,
  286. clk_get_rate(clk_hclk) / 1000,
  287. clk_get_rate(clk_pclk) / 1000,
  288. clk_get_rate(clk_arm) / 1000);
  289. return 0;
  290. }
  291. #ifdef CONFIG_PM
  292. static struct cpufreq_frequency_table suspend_pll;
  293. static unsigned int suspend_freq;
  294. static int s3c_cpufreq_suspend(struct cpufreq_policy *policy)
  295. {
  296. suspend_pll.frequency = clk_get_rate(_clk_mpll);
  297. suspend_pll.driver_data = s3c24xx_read_mpllcon();
  298. suspend_freq = clk_get_rate(clk_arm);
  299. return 0;
  300. }
  301. static int s3c_cpufreq_resume(struct cpufreq_policy *policy)
  302. {
  303. int ret;
  304. s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy);
  305. last_target = ~0; /* invalidate last_target setting */
  306. /* whilst we will be called later on, we try and re-set the
  307. * cpu frequencies as soon as possible so that we do not end
  308. * up resuming devices and then immediately having to re-set
  309. * a number of settings once these devices have restarted.
  310. *
  311. * as a note, it is expected devices are not used until they
  312. * have been un-suspended and at that time they should have
  313. * used the updated clock settings.
  314. */
  315. ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll);
  316. if (ret) {
  317. pr_err("%s: failed to reset pll/freq\n", __func__);
  318. return ret;
  319. }
  320. return 0;
  321. }
  322. #else
  323. #define s3c_cpufreq_resume NULL
  324. #define s3c_cpufreq_suspend NULL
  325. #endif
  326. static struct cpufreq_driver s3c24xx_driver = {
  327. .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
  328. .target = s3c_cpufreq_target,
  329. .get = cpufreq_generic_get,
  330. .init = s3c_cpufreq_init,
  331. .suspend = s3c_cpufreq_suspend,
  332. .resume = s3c_cpufreq_resume,
  333. .name = "s3c24xx",
  334. };
  335. int s3c_cpufreq_register(struct s3c_cpufreq_info *info)
  336. {
  337. if (!info || !info->name) {
  338. pr_err("%s: failed to pass valid information\n", __func__);
  339. return -EINVAL;
  340. }
  341. pr_info("S3C24XX CPU Frequency driver, %s cpu support\n",
  342. info->name);
  343. /* check our driver info has valid data */
  344. BUG_ON(info->set_refresh == NULL);
  345. BUG_ON(info->set_divs == NULL);
  346. BUG_ON(info->calc_divs == NULL);
  347. /* info->set_fvco is optional, depending on whether there
  348. * is a need to set the clock code. */
  349. cpu_cur.info = info;
  350. /* Note, driver registering should probably update locktime */
  351. return 0;
  352. }
  353. int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
  354. {
  355. struct s3c_cpufreq_board *ours;
  356. if (!board) {
  357. pr_info("%s: no board data\n", __func__);
  358. return -EINVAL;
  359. }
  360. /* Copy the board information so that each board can make this
  361. * initdata. */
  362. ours = kzalloc(sizeof(*ours), GFP_KERNEL);
  363. if (!ours)
  364. return -ENOMEM;
  365. *ours = *board;
  366. cpu_cur.board = ours;
  367. return 0;
  368. }
  369. static int __init s3c_cpufreq_auto_io(void)
  370. {
  371. int ret;
  372. if (!cpu_cur.info->get_iotiming) {
  373. pr_err("%s: get_iotiming undefined\n", __func__);
  374. return -ENOENT;
  375. }
  376. pr_info("%s: working out IO settings\n", __func__);
  377. ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming);
  378. if (ret)
  379. pr_err("%s: failed to get timings\n", __func__);
  380. return ret;
  381. }
  382. /* if one or is zero, then return the other, otherwise return the min */
  383. #define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b))
  384. /**
  385. * s3c_cpufreq_freq_min - find the minimum settings for the given freq.
  386. * @dst: The destination structure
  387. * @a: One argument.
  388. * @b: The other argument.
  389. *
  390. * Create a minimum of each frequency entry in the 'struct s3c_freq',
  391. * unless the entry is zero when it is ignored and the non-zero argument
  392. * used.
  393. */
  394. static void s3c_cpufreq_freq_min(struct s3c_freq *dst,
  395. struct s3c_freq *a, struct s3c_freq *b)
  396. {
  397. dst->fclk = do_min(a->fclk, b->fclk);
  398. dst->hclk = do_min(a->hclk, b->hclk);
  399. dst->pclk = do_min(a->pclk, b->pclk);
  400. dst->armclk = do_min(a->armclk, b->armclk);
  401. }
  402. static inline u32 calc_locktime(u32 freq, u32 time_us)
  403. {
  404. u32 result;
  405. result = freq * time_us;
  406. result = DIV_ROUND_UP(result, 1000 * 1000);
  407. return result;
  408. }
  409. static void s3c_cpufreq_update_loctkime(void)
  410. {
  411. unsigned int bits = cpu_cur.info->locktime_bits;
  412. u32 rate = (u32)clk_get_rate(_clk_xtal);
  413. u32 val;
  414. if (bits == 0) {
  415. WARN_ON(1);
  416. return;
  417. }
  418. val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits;
  419. val |= calc_locktime(rate, cpu_cur.info->locktime_m);
  420. pr_info("%s: new locktime is 0x%08x\n", __func__, val);
  421. s3c24xx_write_locktime(val);
  422. }
  423. static int s3c_cpufreq_build_freq(void)
  424. {
  425. int size, ret;
  426. kfree(ftab);
  427. size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0);
  428. size++;
  429. ftab = kcalloc(size, sizeof(*ftab), GFP_KERNEL);
  430. if (!ftab)
  431. return -ENOMEM;
  432. ftab_size = size;
  433. ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size);
  434. s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END);
  435. return 0;
  436. }
  437. static int __init s3c_cpufreq_initcall(void)
  438. {
  439. int ret = 0;
  440. if (cpu_cur.info && cpu_cur.board) {
  441. ret = s3c_cpufreq_initclks();
  442. if (ret)
  443. goto out;
  444. /* get current settings */
  445. s3c_cpufreq_getcur(&cpu_cur);
  446. s3c_cpufreq_show("cur", &cpu_cur);
  447. if (cpu_cur.board->auto_io) {
  448. ret = s3c_cpufreq_auto_io();
  449. if (ret) {
  450. pr_err("%s: failed to get io timing\n",
  451. __func__);
  452. goto out;
  453. }
  454. }
  455. if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) {
  456. pr_err("%s: no IO support registered\n", __func__);
  457. ret = -EINVAL;
  458. goto out;
  459. }
  460. if (!cpu_cur.info->need_pll)
  461. cpu_cur.lock_pll = 1;
  462. s3c_cpufreq_update_loctkime();
  463. s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max,
  464. &cpu_cur.info->max);
  465. if (cpu_cur.info->calc_freqtable)
  466. s3c_cpufreq_build_freq();
  467. ret = cpufreq_register_driver(&s3c24xx_driver);
  468. }
  469. out:
  470. return ret;
  471. }
  472. late_initcall(s3c_cpufreq_initcall);
  473. /**
  474. * s3c_plltab_register - register CPU PLL table.
  475. * @plls: The list of PLL entries.
  476. * @plls_no: The size of the PLL entries @plls.
  477. *
  478. * Register the given set of PLLs with the system.
  479. */
  480. int s3c_plltab_register(struct cpufreq_frequency_table *plls,
  481. unsigned int plls_no)
  482. {
  483. struct cpufreq_frequency_table *vals;
  484. unsigned int size;
  485. size = sizeof(*vals) * (plls_no + 1);
  486. vals = kzalloc(size, GFP_KERNEL);
  487. if (vals) {
  488. memcpy(vals, plls, size);
  489. pll_reg = vals;
  490. /* write a terminating entry, we don't store it in the
  491. * table that is stored in the kernel */
  492. vals += plls_no;
  493. vals->frequency = CPUFREQ_TABLE_END;
  494. pr_info("%d PLL entries\n", plls_no);
  495. } else
  496. pr_err("no memory for PLL tables\n");
  497. return vals ? 0 : -ENOMEM;
  498. }