s3c2412-cpufreq.c 5.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2008 Simtec Electronics
  4. * http://armlinux.simtec.co.uk/
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * S3C2412 CPU Frequency scalling
  8. */
  9. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10. #include <linux/init.h>
  11. #include <linux/module.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/ioport.h>
  14. #include <linux/cpufreq.h>
  15. #include <linux/device.h>
  16. #include <linux/delay.h>
  17. #include <linux/clk.h>
  18. #include <linux/err.h>
  19. #include <linux/io.h>
  20. #include <linux/soc/samsung/s3c-cpufreq-core.h>
  21. #include <linux/soc/samsung/s3c-pm.h>
  22. #include <asm/mach/arch.h>
  23. #include <asm/mach/map.h>
  24. #define S3C2412_CLKDIVN_PDIVN (1<<2)
  25. #define S3C2412_CLKDIVN_HDIVN_MASK (3<<0)
  26. #define S3C2412_CLKDIVN_ARMDIVN (1<<3)
  27. #define S3C2412_CLKDIVN_DVSEN (1<<4)
  28. #define S3C2412_CLKDIVN_HALFHCLK (1<<5)
  29. #define S3C2412_CLKDIVN_USB48DIV (1<<6)
  30. #define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8)
  31. #define S3C2412_CLKDIVN_UARTDIV_SHIFT (8)
  32. #define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12)
  33. #define S3C2412_CLKDIVN_I2SDIV_SHIFT (12)
  34. #define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16)
  35. #define S3C2412_CLKDIVN_CAMDIV_SHIFT (16)
  36. /* our clock resources. */
  37. static struct clk *xtal;
  38. static struct clk *fclk;
  39. static struct clk *hclk;
  40. static struct clk *armclk;
  41. /* HDIV: 1, 2, 3, 4, 6, 8 */
  42. static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
  43. {
  44. unsigned int hdiv, pdiv, armdiv, dvs;
  45. unsigned long hclk, fclk, armclk, armdiv_clk;
  46. unsigned long hclk_max;
  47. fclk = cfg->freq.fclk;
  48. armclk = cfg->freq.armclk;
  49. hclk_max = cfg->max.hclk;
  50. /* We can't run hclk above armclk as at the best we have to
  51. * have armclk and hclk in dvs mode. */
  52. if (hclk_max > armclk)
  53. hclk_max = armclk;
  54. s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n",
  55. __func__, fclk, armclk, hclk_max);
  56. s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n",
  57. __func__, cfg->freq.fclk, cfg->freq.armclk,
  58. cfg->freq.hclk, cfg->freq.pclk);
  59. armdiv = fclk / armclk;
  60. if (armdiv < 1)
  61. armdiv = 1;
  62. if (armdiv > 2)
  63. armdiv = 2;
  64. cfg->divs.arm_divisor = armdiv;
  65. armdiv_clk = fclk / armdiv;
  66. hdiv = armdiv_clk / hclk_max;
  67. if (hdiv < 1)
  68. hdiv = 1;
  69. cfg->freq.hclk = hclk = armdiv_clk / hdiv;
  70. /* set dvs depending on whether we reached armclk or not. */
  71. cfg->divs.dvs = dvs = armclk < armdiv_clk;
  72. /* update the actual armclk we achieved. */
  73. cfg->freq.armclk = dvs ? hclk : armdiv_clk;
  74. s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n",
  75. __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs);
  76. if (hdiv > 4)
  77. goto invalid;
  78. pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
  79. if ((hclk / pdiv) > cfg->max.pclk)
  80. pdiv++;
  81. cfg->freq.pclk = hclk / pdiv;
  82. s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
  83. if (pdiv > 2)
  84. goto invalid;
  85. pdiv *= hdiv;
  86. /* store the result, and then return */
  87. cfg->divs.h_divisor = hdiv * armdiv;
  88. cfg->divs.p_divisor = pdiv * armdiv;
  89. return 0;
  90. invalid:
  91. return -EINVAL;
  92. }
  93. static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
  94. {
  95. unsigned long clkdiv;
  96. unsigned long olddiv;
  97. olddiv = clkdiv = s3c24xx_read_clkdivn();
  98. /* clear off current clock info */
  99. clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN;
  100. clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK;
  101. clkdiv &= ~S3C2412_CLKDIVN_PDIVN;
  102. if (cfg->divs.arm_divisor == 2)
  103. clkdiv |= S3C2412_CLKDIVN_ARMDIVN;
  104. clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1);
  105. if (cfg->divs.p_divisor != cfg->divs.h_divisor)
  106. clkdiv |= S3C2412_CLKDIVN_PDIVN;
  107. s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);
  108. s3c24xx_write_clkdivn(clkdiv);
  109. clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
  110. }
  111. /* set the default cpu frequency information, based on an 200MHz part
  112. * as we have no other way of detecting the speed rating in software.
  113. */
  114. static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
  115. .max = {
  116. .fclk = 200000000,
  117. .hclk = 100000000,
  118. .pclk = 50000000,
  119. },
  120. .latency = 5000000, /* 5ms */
  121. .locktime_m = 150,
  122. .locktime_u = 150,
  123. .locktime_bits = 16,
  124. .name = "s3c2412",
  125. .set_refresh = s3c2412_cpufreq_setrefresh,
  126. .set_divs = s3c2412_cpufreq_setdivs,
  127. .calc_divs = s3c2412_cpufreq_calcdivs,
  128. .calc_iotiming = s3c2412_iotiming_calc,
  129. .set_iotiming = s3c2412_iotiming_set,
  130. .get_iotiming = s3c2412_iotiming_get,
  131. .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
  132. };
  133. static int s3c2412_cpufreq_add(struct device *dev,
  134. struct subsys_interface *sif)
  135. {
  136. unsigned long fclk_rate;
  137. hclk = clk_get(NULL, "hclk");
  138. if (IS_ERR(hclk)) {
  139. pr_err("cannot find hclk clock\n");
  140. return -ENOENT;
  141. }
  142. fclk = clk_get(NULL, "fclk");
  143. if (IS_ERR(fclk)) {
  144. pr_err("cannot find fclk clock\n");
  145. goto err_fclk;
  146. }
  147. fclk_rate = clk_get_rate(fclk);
  148. if (fclk_rate > 200000000) {
  149. pr_info("fclk %ld MHz, assuming 266MHz capable part\n",
  150. fclk_rate / 1000000);
  151. s3c2412_cpufreq_info.max.fclk = 266000000;
  152. s3c2412_cpufreq_info.max.hclk = 133000000;
  153. s3c2412_cpufreq_info.max.pclk = 66000000;
  154. }
  155. armclk = clk_get(NULL, "armclk");
  156. if (IS_ERR(armclk)) {
  157. pr_err("cannot find arm clock\n");
  158. goto err_armclk;
  159. }
  160. xtal = clk_get(NULL, "xtal");
  161. if (IS_ERR(xtal)) {
  162. pr_err("cannot find xtal clock\n");
  163. goto err_xtal;
  164. }
  165. return s3c_cpufreq_register(&s3c2412_cpufreq_info);
  166. err_xtal:
  167. clk_put(armclk);
  168. err_armclk:
  169. clk_put(fclk);
  170. err_fclk:
  171. clk_put(hclk);
  172. return -ENOENT;
  173. }
  174. static struct subsys_interface s3c2412_cpufreq_interface = {
  175. .name = "s3c2412_cpufreq",
  176. .subsys = &s3c2412_subsys,
  177. .add_dev = s3c2412_cpufreq_add,
  178. };
  179. static int s3c2412_cpufreq_init(void)
  180. {
  181. return subsys_interface_register(&s3c2412_cpufreq_interface);
  182. }
  183. arch_initcall(s3c2412_cpufreq_init);