qcom-cpufreq-nvmem.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  4. */
  5. /*
  6. * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
  7. * the CPU frequency subset and voltage value of each OPP varies
  8. * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
  9. * defines the voltage and frequency value based on the msm-id in SMEM
  10. * and speedbin blown in the efuse combination.
  11. * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
  12. * to provide the OPP framework with required information.
  13. * This is used to determine the voltage and frequency value for each OPP of
  14. * operating-points-v2 table when it is parsed by the OPP framework.
  15. */
  16. #include <linux/cpu.h>
  17. #include <linux/err.h>
  18. #include <linux/init.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/nvmem-consumer.h>
  22. #include <linux/of.h>
  23. #include <linux/of_device.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/pm_domain.h>
  26. #include <linux/pm_opp.h>
  27. #include <linux/slab.h>
  28. #include <linux/soc/qcom/smem.h>
  29. #define MSM_ID_SMEM 137
  30. enum _msm_id {
  31. MSM8996V3 = 0xF6ul,
  32. APQ8096V3 = 0x123ul,
  33. MSM8996SG = 0x131ul,
  34. APQ8096SG = 0x138ul,
  35. };
  36. enum _msm8996_version {
  37. MSM8996_V3,
  38. MSM8996_SG,
  39. NUM_OF_MSM8996_VERSIONS,
  40. };
  41. struct qcom_cpufreq_drv;
  42. struct qcom_cpufreq_match_data {
  43. int (*get_version)(struct device *cpu_dev,
  44. struct nvmem_cell *speedbin_nvmem,
  45. char **pvs_name,
  46. struct qcom_cpufreq_drv *drv);
  47. const char **genpd_names;
  48. };
  49. struct qcom_cpufreq_drv {
  50. struct opp_table **names_opp_tables;
  51. struct opp_table **hw_opp_tables;
  52. struct opp_table **genpd_opp_tables;
  53. u32 versions;
  54. const struct qcom_cpufreq_match_data *data;
  55. };
  56. static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
  57. static void get_krait_bin_format_a(struct device *cpu_dev,
  58. int *speed, int *pvs, int *pvs_ver,
  59. struct nvmem_cell *pvs_nvmem, u8 *buf)
  60. {
  61. u32 pte_efuse;
  62. pte_efuse = *((u32 *)buf);
  63. *speed = pte_efuse & 0xf;
  64. if (*speed == 0xf)
  65. *speed = (pte_efuse >> 4) & 0xf;
  66. if (*speed == 0xf) {
  67. *speed = 0;
  68. dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
  69. } else {
  70. dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
  71. }
  72. *pvs = (pte_efuse >> 10) & 0x7;
  73. if (*pvs == 0x7)
  74. *pvs = (pte_efuse >> 13) & 0x7;
  75. if (*pvs == 0x7) {
  76. *pvs = 0;
  77. dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
  78. } else {
  79. dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
  80. }
  81. }
  82. static void get_krait_bin_format_b(struct device *cpu_dev,
  83. int *speed, int *pvs, int *pvs_ver,
  84. struct nvmem_cell *pvs_nvmem, u8 *buf)
  85. {
  86. u32 pte_efuse, redundant_sel;
  87. pte_efuse = *((u32 *)buf);
  88. redundant_sel = (pte_efuse >> 24) & 0x7;
  89. *pvs_ver = (pte_efuse >> 4) & 0x3;
  90. switch (redundant_sel) {
  91. case 1:
  92. *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
  93. *speed = (pte_efuse >> 27) & 0xf;
  94. break;
  95. case 2:
  96. *pvs = (pte_efuse >> 27) & 0xf;
  97. *speed = pte_efuse & 0x7;
  98. break;
  99. default:
  100. /* 4 bits of PVS are in efuse register bits 31, 8-6. */
  101. *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
  102. *speed = pte_efuse & 0x7;
  103. }
  104. /* Check SPEED_BIN_BLOW_STATUS */
  105. if (pte_efuse & BIT(3)) {
  106. dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
  107. } else {
  108. dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
  109. *speed = 0;
  110. }
  111. /* Check PVS_BLOW_STATUS */
  112. pte_efuse = *(((u32 *)buf) + 1);
  113. pte_efuse &= BIT(21);
  114. if (pte_efuse) {
  115. dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
  116. } else {
  117. dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
  118. *pvs = 0;
  119. }
  120. dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
  121. }
  122. static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
  123. {
  124. size_t len;
  125. u32 *msm_id;
  126. enum _msm8996_version version;
  127. msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len);
  128. if (IS_ERR(msm_id))
  129. return NUM_OF_MSM8996_VERSIONS;
  130. /* The first 4 bytes are format, next to them is the actual msm-id */
  131. msm_id++;
  132. switch ((enum _msm_id)*msm_id) {
  133. case MSM8996V3:
  134. case APQ8096V3:
  135. version = MSM8996_V3;
  136. break;
  137. case MSM8996SG:
  138. case APQ8096SG:
  139. version = MSM8996_SG;
  140. break;
  141. default:
  142. version = NUM_OF_MSM8996_VERSIONS;
  143. }
  144. return version;
  145. }
  146. static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
  147. struct nvmem_cell *speedbin_nvmem,
  148. char **pvs_name,
  149. struct qcom_cpufreq_drv *drv)
  150. {
  151. size_t len;
  152. u8 *speedbin;
  153. enum _msm8996_version msm8996_version;
  154. *pvs_name = NULL;
  155. msm8996_version = qcom_cpufreq_get_msm_id();
  156. if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
  157. dev_err(cpu_dev, "Not Snapdragon 820/821!");
  158. return -ENODEV;
  159. }
  160. speedbin = nvmem_cell_read(speedbin_nvmem, &len);
  161. if (IS_ERR(speedbin))
  162. return PTR_ERR(speedbin);
  163. switch (msm8996_version) {
  164. case MSM8996_V3:
  165. drv->versions = 1 << (unsigned int)(*speedbin);
  166. break;
  167. case MSM8996_SG:
  168. drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
  169. break;
  170. default:
  171. BUG();
  172. break;
  173. }
  174. kfree(speedbin);
  175. return 0;
  176. }
  177. static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
  178. struct nvmem_cell *speedbin_nvmem,
  179. char **pvs_name,
  180. struct qcom_cpufreq_drv *drv)
  181. {
  182. int speed = 0, pvs = 0, pvs_ver = 0;
  183. u8 *speedbin;
  184. size_t len;
  185. speedbin = nvmem_cell_read(speedbin_nvmem, &len);
  186. if (IS_ERR(speedbin))
  187. return PTR_ERR(speedbin);
  188. switch (len) {
  189. case 4:
  190. get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
  191. speedbin_nvmem, speedbin);
  192. break;
  193. case 8:
  194. get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
  195. speedbin_nvmem, speedbin);
  196. break;
  197. default:
  198. dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
  199. return -ENODEV;
  200. }
  201. snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
  202. speed, pvs, pvs_ver);
  203. drv->versions = (1 << speed);
  204. kfree(speedbin);
  205. return 0;
  206. }
  207. static const struct qcom_cpufreq_match_data match_data_kryo = {
  208. .get_version = qcom_cpufreq_kryo_name_version,
  209. };
  210. static const struct qcom_cpufreq_match_data match_data_krait = {
  211. .get_version = qcom_cpufreq_krait_name_version,
  212. };
  213. static const char *qcs404_genpd_names[] = { "cpr", NULL };
  214. static const struct qcom_cpufreq_match_data match_data_qcs404 = {
  215. .genpd_names = qcs404_genpd_names,
  216. };
  217. static int qcom_cpufreq_probe(struct platform_device *pdev)
  218. {
  219. struct qcom_cpufreq_drv *drv;
  220. struct nvmem_cell *speedbin_nvmem;
  221. struct device_node *np;
  222. struct device *cpu_dev;
  223. char *pvs_name = "speedXX-pvsXX-vXX";
  224. unsigned cpu;
  225. const struct of_device_id *match;
  226. int ret;
  227. cpu_dev = get_cpu_device(0);
  228. if (!cpu_dev)
  229. return -ENODEV;
  230. np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
  231. if (!np)
  232. return -ENOENT;
  233. ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
  234. if (!ret) {
  235. of_node_put(np);
  236. return -ENOENT;
  237. }
  238. drv = kzalloc(sizeof(*drv), GFP_KERNEL);
  239. if (!drv)
  240. return -ENOMEM;
  241. match = pdev->dev.platform_data;
  242. drv->data = match->data;
  243. if (!drv->data) {
  244. ret = -ENODEV;
  245. goto free_drv;
  246. }
  247. if (drv->data->get_version) {
  248. speedbin_nvmem = of_nvmem_cell_get(np, NULL);
  249. if (IS_ERR(speedbin_nvmem)) {
  250. if (PTR_ERR(speedbin_nvmem) != -EPROBE_DEFER)
  251. dev_err(cpu_dev,
  252. "Could not get nvmem cell: %ld\n",
  253. PTR_ERR(speedbin_nvmem));
  254. ret = PTR_ERR(speedbin_nvmem);
  255. goto free_drv;
  256. }
  257. ret = drv->data->get_version(cpu_dev,
  258. speedbin_nvmem, &pvs_name, drv);
  259. if (ret) {
  260. nvmem_cell_put(speedbin_nvmem);
  261. goto free_drv;
  262. }
  263. nvmem_cell_put(speedbin_nvmem);
  264. }
  265. of_node_put(np);
  266. drv->names_opp_tables = kcalloc(num_possible_cpus(),
  267. sizeof(*drv->names_opp_tables),
  268. GFP_KERNEL);
  269. if (!drv->names_opp_tables) {
  270. ret = -ENOMEM;
  271. goto free_drv;
  272. }
  273. drv->hw_opp_tables = kcalloc(num_possible_cpus(),
  274. sizeof(*drv->hw_opp_tables),
  275. GFP_KERNEL);
  276. if (!drv->hw_opp_tables) {
  277. ret = -ENOMEM;
  278. goto free_opp_names;
  279. }
  280. drv->genpd_opp_tables = kcalloc(num_possible_cpus(),
  281. sizeof(*drv->genpd_opp_tables),
  282. GFP_KERNEL);
  283. if (!drv->genpd_opp_tables) {
  284. ret = -ENOMEM;
  285. goto free_opp;
  286. }
  287. for_each_possible_cpu(cpu) {
  288. cpu_dev = get_cpu_device(cpu);
  289. if (NULL == cpu_dev) {
  290. ret = -ENODEV;
  291. goto free_genpd_opp;
  292. }
  293. if (drv->data->get_version) {
  294. if (pvs_name) {
  295. drv->names_opp_tables[cpu] = dev_pm_opp_set_prop_name(
  296. cpu_dev,
  297. pvs_name);
  298. if (IS_ERR(drv->names_opp_tables[cpu])) {
  299. ret = PTR_ERR(drv->names_opp_tables[cpu]);
  300. dev_err(cpu_dev, "Failed to add OPP name %s\n",
  301. pvs_name);
  302. goto free_opp;
  303. }
  304. }
  305. drv->hw_opp_tables[cpu] = dev_pm_opp_set_supported_hw(
  306. cpu_dev, &drv->versions, 1);
  307. if (IS_ERR(drv->hw_opp_tables[cpu])) {
  308. ret = PTR_ERR(drv->hw_opp_tables[cpu]);
  309. dev_err(cpu_dev,
  310. "Failed to set supported hardware\n");
  311. goto free_genpd_opp;
  312. }
  313. }
  314. if (drv->data->genpd_names) {
  315. drv->genpd_opp_tables[cpu] =
  316. dev_pm_opp_attach_genpd(cpu_dev,
  317. drv->data->genpd_names,
  318. NULL);
  319. if (IS_ERR(drv->genpd_opp_tables[cpu])) {
  320. ret = PTR_ERR(drv->genpd_opp_tables[cpu]);
  321. if (ret != -EPROBE_DEFER)
  322. dev_err(cpu_dev,
  323. "Could not attach to pm_domain: %d\n",
  324. ret);
  325. goto free_genpd_opp;
  326. }
  327. }
  328. }
  329. cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
  330. NULL, 0);
  331. if (!IS_ERR(cpufreq_dt_pdev)) {
  332. platform_set_drvdata(pdev, drv);
  333. return 0;
  334. }
  335. ret = PTR_ERR(cpufreq_dt_pdev);
  336. dev_err(cpu_dev, "Failed to register platform device\n");
  337. free_genpd_opp:
  338. for_each_possible_cpu(cpu) {
  339. if (IS_ERR_OR_NULL(drv->genpd_opp_tables[cpu]))
  340. break;
  341. dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]);
  342. }
  343. kfree(drv->genpd_opp_tables);
  344. free_opp:
  345. for_each_possible_cpu(cpu) {
  346. if (IS_ERR_OR_NULL(drv->names_opp_tables[cpu]))
  347. break;
  348. dev_pm_opp_put_prop_name(drv->names_opp_tables[cpu]);
  349. }
  350. for_each_possible_cpu(cpu) {
  351. if (IS_ERR_OR_NULL(drv->hw_opp_tables[cpu]))
  352. break;
  353. dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
  354. }
  355. kfree(drv->hw_opp_tables);
  356. free_opp_names:
  357. kfree(drv->names_opp_tables);
  358. free_drv:
  359. kfree(drv);
  360. return ret;
  361. }
  362. static int qcom_cpufreq_remove(struct platform_device *pdev)
  363. {
  364. struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev);
  365. unsigned int cpu;
  366. platform_device_unregister(cpufreq_dt_pdev);
  367. for_each_possible_cpu(cpu) {
  368. if (drv->names_opp_tables[cpu])
  369. dev_pm_opp_put_supported_hw(drv->names_opp_tables[cpu]);
  370. if (drv->hw_opp_tables[cpu])
  371. dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
  372. if (drv->genpd_opp_tables[cpu])
  373. dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]);
  374. }
  375. kfree(drv->names_opp_tables);
  376. kfree(drv->hw_opp_tables);
  377. kfree(drv->genpd_opp_tables);
  378. kfree(drv);
  379. return 0;
  380. }
  381. static struct platform_driver qcom_cpufreq_driver = {
  382. .probe = qcom_cpufreq_probe,
  383. .remove = qcom_cpufreq_remove,
  384. .driver = {
  385. .name = "qcom-cpufreq-nvmem",
  386. },
  387. };
  388. static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
  389. { .compatible = "qcom,apq8096", .data = &match_data_kryo },
  390. { .compatible = "qcom,msm8996", .data = &match_data_kryo },
  391. { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
  392. { .compatible = "qcom,ipq8064", .data = &match_data_krait },
  393. { .compatible = "qcom,apq8064", .data = &match_data_krait },
  394. { .compatible = "qcom,msm8974", .data = &match_data_krait },
  395. { .compatible = "qcom,msm8960", .data = &match_data_krait },
  396. {},
  397. };
  398. MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);
  399. /*
  400. * Since the driver depends on smem and nvmem drivers, which may
  401. * return EPROBE_DEFER, all the real activity is done in the probe,
  402. * which may be defered as well. The init here is only registering
  403. * the driver and the platform device.
  404. */
  405. static int __init qcom_cpufreq_init(void)
  406. {
  407. struct device_node *np = of_find_node_by_path("/");
  408. const struct of_device_id *match;
  409. int ret;
  410. if (!np)
  411. return -ENODEV;
  412. match = of_match_node(qcom_cpufreq_match_list, np);
  413. of_node_put(np);
  414. if (!match)
  415. return -ENODEV;
  416. ret = platform_driver_register(&qcom_cpufreq_driver);
  417. if (unlikely(ret < 0))
  418. return ret;
  419. cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem",
  420. -1, match, sizeof(*match));
  421. ret = PTR_ERR_OR_ZERO(cpufreq_pdev);
  422. if (0 == ret)
  423. return 0;
  424. platform_driver_unregister(&qcom_cpufreq_driver);
  425. return ret;
  426. }
  427. module_init(qcom_cpufreq_init);
  428. static void __exit qcom_cpufreq_exit(void)
  429. {
  430. platform_device_unregister(cpufreq_pdev);
  431. platform_driver_unregister(&qcom_cpufreq_driver);
  432. }
  433. module_exit(qcom_cpufreq_exit);
  434. MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver");
  435. MODULE_LICENSE("GPL v2");