powernow-k8.h 6.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * (c) 2003-2006 Advanced Micro Devices, Inc.
  4. */
  5. struct powernow_k8_data {
  6. unsigned int cpu;
  7. u32 numps; /* number of p-states */
  8. u32 batps; /* number of p-states supported on battery */
  9. /* these values are constant when the PSB is used to determine
  10. * vid/fid pairings, but are modified during the ->target() call
  11. * when ACPI is used */
  12. u32 rvo; /* ramp voltage offset */
  13. u32 irt; /* isochronous relief time */
  14. u32 vidmvs; /* usable value calculated from mvs */
  15. u32 vstable; /* voltage stabilization time, units 20 us */
  16. u32 plllock; /* pll lock time, units 1 us */
  17. u32 exttype; /* extended interface = 1 */
  18. /* keep track of the current fid / vid or pstate */
  19. u32 currvid;
  20. u32 currfid;
  21. /* the powernow_table includes all frequency and vid/fid pairings:
  22. * fid are the lower 8 bits of the index, vid are the upper 8 bits.
  23. * frequency is in kHz */
  24. struct cpufreq_frequency_table *powernow_table;
  25. /* the acpi table needs to be kept. it's only available if ACPI was
  26. * used to determine valid frequency/vid/fid states */
  27. struct acpi_processor_performance acpi_data;
  28. /* we need to keep track of associated cores, but let cpufreq
  29. * handle hotplug events - so just point at cpufreq pol->cpus
  30. * structure */
  31. struct cpumask *available_cores;
  32. };
  33. /* processor's cpuid instruction support */
  34. #define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */
  35. #define CPUID_XFAM 0x0ff00000 /* extended family */
  36. #define CPUID_XFAM_K8 0
  37. #define CPUID_XMOD 0x000f0000 /* extended model */
  38. #define CPUID_XMOD_REV_MASK 0x000c0000
  39. #define CPUID_XFAM_10H 0x00100000 /* family 0x10 */
  40. #define CPUID_USE_XFAM_XMOD 0x00000f00
  41. #define CPUID_GET_MAX_CAPABILITIES 0x80000000
  42. #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
  43. #define P_STATE_TRANSITION_CAPABLE 6
  44. /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */
  45. /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
  46. /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
  47. /* the register number is placed in ecx, and the data is returned in edx:eax. */
  48. #define MSR_FIDVID_CTL 0xc0010041
  49. #define MSR_FIDVID_STATUS 0xc0010042
  50. /* Field definitions within the FID VID Low Control MSR : */
  51. #define MSR_C_LO_INIT_FID_VID 0x00010000
  52. #define MSR_C_LO_NEW_VID 0x00003f00
  53. #define MSR_C_LO_NEW_FID 0x0000003f
  54. #define MSR_C_LO_VID_SHIFT 8
  55. /* Field definitions within the FID VID High Control MSR : */
  56. #define MSR_C_HI_STP_GNT_TO 0x000fffff
  57. /* Field definitions within the FID VID Low Status MSR : */
  58. #define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */
  59. #define MSR_S_LO_MAX_RAMP_VID 0x3f000000
  60. #define MSR_S_LO_MAX_FID 0x003f0000
  61. #define MSR_S_LO_START_FID 0x00003f00
  62. #define MSR_S_LO_CURRENT_FID 0x0000003f
  63. /* Field definitions within the FID VID High Status MSR : */
  64. #define MSR_S_HI_MIN_WORKING_VID 0x3f000000
  65. #define MSR_S_HI_MAX_WORKING_VID 0x003f0000
  66. #define MSR_S_HI_START_VID 0x00003f00
  67. #define MSR_S_HI_CURRENT_VID 0x0000003f
  68. #define MSR_C_HI_STP_GNT_BENIGN 0x00000001
  69. /*
  70. * There are restrictions frequencies have to follow:
  71. * - only 1 entry in the low fid table ( <=1.4GHz )
  72. * - lowest entry in the high fid table must be >= 2 * the entry in the
  73. * low fid table
  74. * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
  75. * in the low fid table
  76. * - the parts can only step at <= 200 MHz intervals, odd fid values are
  77. * supported in revision G and later revisions.
  78. * - lowest frequency must be >= interprocessor hypertransport link speed
  79. * (only applies to MP systems obviously)
  80. */
  81. /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
  82. #define LO_FID_TABLE_TOP 7 /* fid values marking the boundary */
  83. #define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */
  84. #define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */
  85. #define HI_VCOFREQ_TABLE_BOTTOM 1600
  86. #define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */
  87. #define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */
  88. #define LEAST_VID 0x3e /* Lowest (numerically highest) useful vid value */
  89. #define MIN_FREQ 800 /* Min and max freqs, per spec */
  90. #define MAX_FREQ 5000
  91. #define INVALID_FID_MASK 0xffffffc0 /* not a valid fid if these bits are set */
  92. #define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */
  93. #define VID_OFF 0x3f
  94. #define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */
  95. #define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */
  96. #define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */
  97. #define VST_UNITS_20US 20 /* Voltage Stabilization Time is in units of 20us */
  98. /*
  99. * Most values of interest are encoded in a single field of the _PSS
  100. * entries: the "control" value.
  101. */
  102. #define IRT_SHIFT 30
  103. #define RVO_SHIFT 28
  104. #define EXT_TYPE_SHIFT 27
  105. #define PLL_L_SHIFT 20
  106. #define MVS_SHIFT 18
  107. #define VST_SHIFT 11
  108. #define VID_SHIFT 6
  109. #define IRT_MASK 3
  110. #define RVO_MASK 3
  111. #define EXT_TYPE_MASK 1
  112. #define PLL_L_MASK 0x7f
  113. #define MVS_MASK 3
  114. #define VST_MASK 0x7f
  115. #define VID_MASK 0x1f
  116. #define FID_MASK 0x1f
  117. #define EXT_VID_MASK 0x3f
  118. #define EXT_FID_MASK 0x3f
  119. /*
  120. * Version 1.4 of the PSB table. This table is constructed by BIOS and is
  121. * to tell the OS's power management driver which VIDs and FIDs are
  122. * supported by this particular processor.
  123. * If the data in the PSB / PST is wrong, then this driver will program the
  124. * wrong values into hardware, which is very likely to lead to a crash.
  125. */
  126. #define PSB_ID_STRING "AMDK7PNOW!"
  127. #define PSB_ID_STRING_LEN 10
  128. #define PSB_VERSION_1_4 0x14
  129. struct psb_s {
  130. u8 signature[10];
  131. u8 tableversion;
  132. u8 flags1;
  133. u16 vstable;
  134. u8 flags2;
  135. u8 num_tables;
  136. u32 cpuid;
  137. u8 plllocktime;
  138. u8 maxfid;
  139. u8 maxvid;
  140. u8 numps;
  141. };
  142. /* Pairs of fid/vid values are appended to the version 1.4 PSB table. */
  143. struct pst_s {
  144. u8 fid;
  145. u8 vid;
  146. };
  147. static int core_voltage_pre_transition(struct powernow_k8_data *data,
  148. u32 reqvid, u32 regfid);
  149. static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid);
  150. static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid);
  151. static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index);
  152. static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);