mediatek-cpufreq.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015 Linaro Ltd.
  4. * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/cpu.h>
  8. #include <linux/cpufreq.h>
  9. #include <linux/cpumask.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/pm_opp.h>
  14. #include <linux/regulator/consumer.h>
  15. #include <linux/slab.h>
  16. #include <linux/thermal.h>
  17. #define MIN_VOLT_SHIFT (100000)
  18. #define MAX_VOLT_SHIFT (200000)
  19. #define MAX_VOLT_LIMIT (1150000)
  20. #define VOLT_TOL (10000)
  21. /*
  22. * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
  23. * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
  24. * Mediatek SoCs has two voltage inputs, Vproc and Vsram. In some cases the two
  25. * voltage inputs need to be controlled under a hardware limitation:
  26. * 100mV < Vsram - Vproc < 200mV
  27. *
  28. * When scaling the clock frequency of a CPU clock domain, the clock source
  29. * needs to be switched to another stable PLL clock temporarily until
  30. * the original PLL becomes stable at target frequency.
  31. */
  32. struct mtk_cpu_dvfs_info {
  33. struct cpumask cpus;
  34. struct device *cpu_dev;
  35. struct regulator *proc_reg;
  36. struct regulator *sram_reg;
  37. struct clk *cpu_clk;
  38. struct clk *inter_clk;
  39. struct list_head list_head;
  40. int intermediate_voltage;
  41. bool need_voltage_tracking;
  42. };
  43. static LIST_HEAD(dvfs_info_list);
  44. static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu)
  45. {
  46. struct mtk_cpu_dvfs_info *info;
  47. list_for_each_entry(info, &dvfs_info_list, list_head) {
  48. if (cpumask_test_cpu(cpu, &info->cpus))
  49. return info;
  50. }
  51. return NULL;
  52. }
  53. static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
  54. int new_vproc)
  55. {
  56. struct regulator *proc_reg = info->proc_reg;
  57. struct regulator *sram_reg = info->sram_reg;
  58. int old_vproc, old_vsram, new_vsram, vsram, vproc, ret;
  59. old_vproc = regulator_get_voltage(proc_reg);
  60. if (old_vproc < 0) {
  61. pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
  62. return old_vproc;
  63. }
  64. /* Vsram should not exceed the maximum allowed voltage of SoC. */
  65. new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT);
  66. if (old_vproc < new_vproc) {
  67. /*
  68. * When scaling up voltages, Vsram and Vproc scale up step
  69. * by step. At each step, set Vsram to (Vproc + 200mV) first,
  70. * then set Vproc to (Vsram - 100mV).
  71. * Keep doing it until Vsram and Vproc hit target voltages.
  72. */
  73. do {
  74. old_vsram = regulator_get_voltage(sram_reg);
  75. if (old_vsram < 0) {
  76. pr_err("%s: invalid Vsram value: %d\n",
  77. __func__, old_vsram);
  78. return old_vsram;
  79. }
  80. old_vproc = regulator_get_voltage(proc_reg);
  81. if (old_vproc < 0) {
  82. pr_err("%s: invalid Vproc value: %d\n",
  83. __func__, old_vproc);
  84. return old_vproc;
  85. }
  86. vsram = min(new_vsram, old_vproc + MAX_VOLT_SHIFT);
  87. if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
  88. vsram = MAX_VOLT_LIMIT;
  89. /*
  90. * If the target Vsram hits the maximum voltage,
  91. * try to set the exact voltage value first.
  92. */
  93. ret = regulator_set_voltage(sram_reg, vsram,
  94. vsram);
  95. if (ret)
  96. ret = regulator_set_voltage(sram_reg,
  97. vsram - VOLT_TOL,
  98. vsram);
  99. vproc = new_vproc;
  100. } else {
  101. ret = regulator_set_voltage(sram_reg, vsram,
  102. vsram + VOLT_TOL);
  103. vproc = vsram - MIN_VOLT_SHIFT;
  104. }
  105. if (ret)
  106. return ret;
  107. ret = regulator_set_voltage(proc_reg, vproc,
  108. vproc + VOLT_TOL);
  109. if (ret) {
  110. regulator_set_voltage(sram_reg, old_vsram,
  111. old_vsram);
  112. return ret;
  113. }
  114. } while (vproc < new_vproc || vsram < new_vsram);
  115. } else if (old_vproc > new_vproc) {
  116. /*
  117. * When scaling down voltages, Vsram and Vproc scale down step
  118. * by step. At each step, set Vproc to (Vsram - 200mV) first,
  119. * then set Vproc to (Vproc + 100mV).
  120. * Keep doing it until Vsram and Vproc hit target voltages.
  121. */
  122. do {
  123. old_vproc = regulator_get_voltage(proc_reg);
  124. if (old_vproc < 0) {
  125. pr_err("%s: invalid Vproc value: %d\n",
  126. __func__, old_vproc);
  127. return old_vproc;
  128. }
  129. old_vsram = regulator_get_voltage(sram_reg);
  130. if (old_vsram < 0) {
  131. pr_err("%s: invalid Vsram value: %d\n",
  132. __func__, old_vsram);
  133. return old_vsram;
  134. }
  135. vproc = max(new_vproc, old_vsram - MAX_VOLT_SHIFT);
  136. ret = regulator_set_voltage(proc_reg, vproc,
  137. vproc + VOLT_TOL);
  138. if (ret)
  139. return ret;
  140. if (vproc == new_vproc)
  141. vsram = new_vsram;
  142. else
  143. vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT);
  144. if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
  145. vsram = MAX_VOLT_LIMIT;
  146. /*
  147. * If the target Vsram hits the maximum voltage,
  148. * try to set the exact voltage value first.
  149. */
  150. ret = regulator_set_voltage(sram_reg, vsram,
  151. vsram);
  152. if (ret)
  153. ret = regulator_set_voltage(sram_reg,
  154. vsram - VOLT_TOL,
  155. vsram);
  156. } else {
  157. ret = regulator_set_voltage(sram_reg, vsram,
  158. vsram + VOLT_TOL);
  159. }
  160. if (ret) {
  161. regulator_set_voltage(proc_reg, old_vproc,
  162. old_vproc);
  163. return ret;
  164. }
  165. } while (vproc > new_vproc + VOLT_TOL ||
  166. vsram > new_vsram + VOLT_TOL);
  167. }
  168. return 0;
  169. }
  170. static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
  171. {
  172. if (info->need_voltage_tracking)
  173. return mtk_cpufreq_voltage_tracking(info, vproc);
  174. else
  175. return regulator_set_voltage(info->proc_reg, vproc,
  176. vproc + VOLT_TOL);
  177. }
  178. static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
  179. unsigned int index)
  180. {
  181. struct cpufreq_frequency_table *freq_table = policy->freq_table;
  182. struct clk *cpu_clk = policy->clk;
  183. struct clk *armpll = clk_get_parent(cpu_clk);
  184. struct mtk_cpu_dvfs_info *info = policy->driver_data;
  185. struct device *cpu_dev = info->cpu_dev;
  186. struct dev_pm_opp *opp;
  187. long freq_hz, old_freq_hz;
  188. int vproc, old_vproc, inter_vproc, target_vproc, ret;
  189. inter_vproc = info->intermediate_voltage;
  190. old_freq_hz = clk_get_rate(cpu_clk);
  191. old_vproc = regulator_get_voltage(info->proc_reg);
  192. if (old_vproc < 0) {
  193. pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
  194. return old_vproc;
  195. }
  196. freq_hz = freq_table[index].frequency * 1000;
  197. opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
  198. if (IS_ERR(opp)) {
  199. pr_err("cpu%d: failed to find OPP for %ld\n",
  200. policy->cpu, freq_hz);
  201. return PTR_ERR(opp);
  202. }
  203. vproc = dev_pm_opp_get_voltage(opp);
  204. dev_pm_opp_put(opp);
  205. /*
  206. * If the new voltage or the intermediate voltage is higher than the
  207. * current voltage, scale up voltage first.
  208. */
  209. target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
  210. if (old_vproc < target_vproc) {
  211. ret = mtk_cpufreq_set_voltage(info, target_vproc);
  212. if (ret) {
  213. pr_err("cpu%d: failed to scale up voltage!\n",
  214. policy->cpu);
  215. mtk_cpufreq_set_voltage(info, old_vproc);
  216. return ret;
  217. }
  218. }
  219. /* Reparent the CPU clock to intermediate clock. */
  220. ret = clk_set_parent(cpu_clk, info->inter_clk);
  221. if (ret) {
  222. pr_err("cpu%d: failed to re-parent cpu clock!\n",
  223. policy->cpu);
  224. mtk_cpufreq_set_voltage(info, old_vproc);
  225. WARN_ON(1);
  226. return ret;
  227. }
  228. /* Set the original PLL to target rate. */
  229. ret = clk_set_rate(armpll, freq_hz);
  230. if (ret) {
  231. pr_err("cpu%d: failed to scale cpu clock rate!\n",
  232. policy->cpu);
  233. clk_set_parent(cpu_clk, armpll);
  234. mtk_cpufreq_set_voltage(info, old_vproc);
  235. return ret;
  236. }
  237. /* Set parent of CPU clock back to the original PLL. */
  238. ret = clk_set_parent(cpu_clk, armpll);
  239. if (ret) {
  240. pr_err("cpu%d: failed to re-parent cpu clock!\n",
  241. policy->cpu);
  242. mtk_cpufreq_set_voltage(info, inter_vproc);
  243. WARN_ON(1);
  244. return ret;
  245. }
  246. /*
  247. * If the new voltage is lower than the intermediate voltage or the
  248. * original voltage, scale down to the new voltage.
  249. */
  250. if (vproc < inter_vproc || vproc < old_vproc) {
  251. ret = mtk_cpufreq_set_voltage(info, vproc);
  252. if (ret) {
  253. pr_err("cpu%d: failed to scale down voltage!\n",
  254. policy->cpu);
  255. clk_set_parent(cpu_clk, info->inter_clk);
  256. clk_set_rate(armpll, old_freq_hz);
  257. clk_set_parent(cpu_clk, armpll);
  258. return ret;
  259. }
  260. }
  261. return 0;
  262. }
  263. #define DYNAMIC_POWER "dynamic-power-coefficient"
  264. static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
  265. {
  266. struct device *cpu_dev;
  267. struct regulator *proc_reg = ERR_PTR(-ENODEV);
  268. struct regulator *sram_reg = ERR_PTR(-ENODEV);
  269. struct clk *cpu_clk = ERR_PTR(-ENODEV);
  270. struct clk *inter_clk = ERR_PTR(-ENODEV);
  271. struct dev_pm_opp *opp;
  272. unsigned long rate;
  273. int ret;
  274. cpu_dev = get_cpu_device(cpu);
  275. if (!cpu_dev) {
  276. pr_err("failed to get cpu%d device\n", cpu);
  277. return -ENODEV;
  278. }
  279. cpu_clk = clk_get(cpu_dev, "cpu");
  280. if (IS_ERR(cpu_clk)) {
  281. if (PTR_ERR(cpu_clk) == -EPROBE_DEFER)
  282. pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu);
  283. else
  284. pr_err("failed to get cpu clk for cpu%d\n", cpu);
  285. ret = PTR_ERR(cpu_clk);
  286. return ret;
  287. }
  288. inter_clk = clk_get(cpu_dev, "intermediate");
  289. if (IS_ERR(inter_clk)) {
  290. if (PTR_ERR(inter_clk) == -EPROBE_DEFER)
  291. pr_warn("intermediate clk for cpu%d not ready, retry.\n",
  292. cpu);
  293. else
  294. pr_err("failed to get intermediate clk for cpu%d\n",
  295. cpu);
  296. ret = PTR_ERR(inter_clk);
  297. goto out_free_resources;
  298. }
  299. proc_reg = regulator_get_optional(cpu_dev, "proc");
  300. if (IS_ERR(proc_reg)) {
  301. if (PTR_ERR(proc_reg) == -EPROBE_DEFER)
  302. pr_warn("proc regulator for cpu%d not ready, retry.\n",
  303. cpu);
  304. else
  305. pr_err("failed to get proc regulator for cpu%d\n",
  306. cpu);
  307. ret = PTR_ERR(proc_reg);
  308. goto out_free_resources;
  309. }
  310. /* Both presence and absence of sram regulator are valid cases. */
  311. sram_reg = regulator_get_exclusive(cpu_dev, "sram");
  312. /* Get OPP-sharing information from "operating-points-v2" bindings */
  313. ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
  314. if (ret) {
  315. pr_err("failed to get OPP-sharing information for cpu%d\n",
  316. cpu);
  317. goto out_free_resources;
  318. }
  319. ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
  320. if (ret) {
  321. pr_warn("no OPP table for cpu%d\n", cpu);
  322. goto out_free_resources;
  323. }
  324. /* Search a safe voltage for intermediate frequency. */
  325. rate = clk_get_rate(inter_clk);
  326. opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
  327. if (IS_ERR(opp)) {
  328. pr_err("failed to get intermediate opp for cpu%d\n", cpu);
  329. ret = PTR_ERR(opp);
  330. goto out_free_opp_table;
  331. }
  332. info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
  333. dev_pm_opp_put(opp);
  334. info->cpu_dev = cpu_dev;
  335. info->proc_reg = proc_reg;
  336. info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg;
  337. info->cpu_clk = cpu_clk;
  338. info->inter_clk = inter_clk;
  339. /*
  340. * If SRAM regulator is present, software "voltage tracking" is needed
  341. * for this CPU power domain.
  342. */
  343. info->need_voltage_tracking = !IS_ERR(sram_reg);
  344. return 0;
  345. out_free_opp_table:
  346. dev_pm_opp_of_cpumask_remove_table(&info->cpus);
  347. out_free_resources:
  348. if (!IS_ERR(proc_reg))
  349. regulator_put(proc_reg);
  350. if (!IS_ERR(sram_reg))
  351. regulator_put(sram_reg);
  352. if (!IS_ERR(cpu_clk))
  353. clk_put(cpu_clk);
  354. if (!IS_ERR(inter_clk))
  355. clk_put(inter_clk);
  356. return ret;
  357. }
  358. static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
  359. {
  360. if (!IS_ERR(info->proc_reg))
  361. regulator_put(info->proc_reg);
  362. if (!IS_ERR(info->sram_reg))
  363. regulator_put(info->sram_reg);
  364. if (!IS_ERR(info->cpu_clk))
  365. clk_put(info->cpu_clk);
  366. if (!IS_ERR(info->inter_clk))
  367. clk_put(info->inter_clk);
  368. dev_pm_opp_of_cpumask_remove_table(&info->cpus);
  369. }
  370. static int mtk_cpufreq_init(struct cpufreq_policy *policy)
  371. {
  372. struct mtk_cpu_dvfs_info *info;
  373. struct cpufreq_frequency_table *freq_table;
  374. int ret;
  375. info = mtk_cpu_dvfs_info_lookup(policy->cpu);
  376. if (!info) {
  377. pr_err("dvfs info for cpu%d is not initialized.\n",
  378. policy->cpu);
  379. return -EINVAL;
  380. }
  381. ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table);
  382. if (ret) {
  383. pr_err("failed to init cpufreq table for cpu%d: %d\n",
  384. policy->cpu, ret);
  385. return ret;
  386. }
  387. cpumask_copy(policy->cpus, &info->cpus);
  388. policy->freq_table = freq_table;
  389. policy->driver_data = info;
  390. policy->clk = info->cpu_clk;
  391. dev_pm_opp_of_register_em(info->cpu_dev, policy->cpus);
  392. return 0;
  393. }
  394. static int mtk_cpufreq_exit(struct cpufreq_policy *policy)
  395. {
  396. struct mtk_cpu_dvfs_info *info = policy->driver_data;
  397. dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table);
  398. return 0;
  399. }
  400. static struct cpufreq_driver mtk_cpufreq_driver = {
  401. .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
  402. CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
  403. CPUFREQ_IS_COOLING_DEV,
  404. .verify = cpufreq_generic_frequency_table_verify,
  405. .target_index = mtk_cpufreq_set_target,
  406. .get = cpufreq_generic_get,
  407. .init = mtk_cpufreq_init,
  408. .exit = mtk_cpufreq_exit,
  409. .name = "mtk-cpufreq",
  410. .attr = cpufreq_generic_attr,
  411. };
  412. static int mtk_cpufreq_probe(struct platform_device *pdev)
  413. {
  414. struct mtk_cpu_dvfs_info *info, *tmp;
  415. int cpu, ret;
  416. for_each_possible_cpu(cpu) {
  417. info = mtk_cpu_dvfs_info_lookup(cpu);
  418. if (info)
  419. continue;
  420. info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
  421. if (!info) {
  422. ret = -ENOMEM;
  423. goto release_dvfs_info_list;
  424. }
  425. ret = mtk_cpu_dvfs_info_init(info, cpu);
  426. if (ret) {
  427. dev_err(&pdev->dev,
  428. "failed to initialize dvfs info for cpu%d\n",
  429. cpu);
  430. goto release_dvfs_info_list;
  431. }
  432. list_add(&info->list_head, &dvfs_info_list);
  433. }
  434. ret = cpufreq_register_driver(&mtk_cpufreq_driver);
  435. if (ret) {
  436. dev_err(&pdev->dev, "failed to register mtk cpufreq driver\n");
  437. goto release_dvfs_info_list;
  438. }
  439. return 0;
  440. release_dvfs_info_list:
  441. list_for_each_entry_safe(info, tmp, &dvfs_info_list, list_head) {
  442. mtk_cpu_dvfs_info_release(info);
  443. list_del(&info->list_head);
  444. }
  445. return ret;
  446. }
  447. static struct platform_driver mtk_cpufreq_platdrv = {
  448. .driver = {
  449. .name = "mtk-cpufreq",
  450. },
  451. .probe = mtk_cpufreq_probe,
  452. };
  453. /* List of machines supported by this driver */
  454. static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
  455. { .compatible = "mediatek,mt2701", },
  456. { .compatible = "mediatek,mt2712", },
  457. { .compatible = "mediatek,mt7622", },
  458. { .compatible = "mediatek,mt7623", },
  459. { .compatible = "mediatek,mt817x", },
  460. { .compatible = "mediatek,mt8173", },
  461. { .compatible = "mediatek,mt8176", },
  462. { .compatible = "mediatek,mt8183", },
  463. { .compatible = "mediatek,mt8516", },
  464. { }
  465. };
  466. MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines);
  467. static int __init mtk_cpufreq_driver_init(void)
  468. {
  469. struct device_node *np;
  470. const struct of_device_id *match;
  471. struct platform_device *pdev;
  472. int err;
  473. np = of_find_node_by_path("/");
  474. if (!np)
  475. return -ENODEV;
  476. match = of_match_node(mtk_cpufreq_machines, np);
  477. of_node_put(np);
  478. if (!match) {
  479. pr_debug("Machine is not compatible with mtk-cpufreq\n");
  480. return -ENODEV;
  481. }
  482. err = platform_driver_register(&mtk_cpufreq_platdrv);
  483. if (err)
  484. return err;
  485. /*
  486. * Since there's no place to hold device registration code and no
  487. * device tree based way to match cpufreq driver yet, both the driver
  488. * and the device registration codes are put here to handle defer
  489. * probing.
  490. */
  491. pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
  492. if (IS_ERR(pdev)) {
  493. pr_err("failed to register mtk-cpufreq platform device\n");
  494. return PTR_ERR(pdev);
  495. }
  496. return 0;
  497. }
  498. device_initcall(mtk_cpufreq_driver_init);
  499. MODULE_DESCRIPTION("MediaTek CPUFreq driver");
  500. MODULE_AUTHOR("Pi-Cheng Chen <pi-cheng.chen@linaro.org>");
  501. MODULE_LICENSE("GPL v2");