maple-cpufreq.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2011 Dmitry Eremin-Solenikov
  4. * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
  5. * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
  6. *
  7. * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
  8. * that is iMac G5 and latest single CPU desktop.
  9. */
  10. #undef DEBUG
  11. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/types.h>
  14. #include <linux/errno.h>
  15. #include <linux/kernel.h>
  16. #include <linux/delay.h>
  17. #include <linux/sched.h>
  18. #include <linux/cpufreq.h>
  19. #include <linux/init.h>
  20. #include <linux/completion.h>
  21. #include <linux/mutex.h>
  22. #include <linux/time.h>
  23. #include <linux/of_device.h>
  24. #define DBG(fmt...) pr_debug(fmt)
  25. /* see 970FX user manual */
  26. #define SCOM_PCR 0x0aa001 /* PCR scom addr */
  27. #define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */
  28. #define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
  29. #define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
  30. #define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
  31. #define PCR_SPEED_MASK 0x000e0000U /* speed mask */
  32. #define PCR_SPEED_SHIFT 17
  33. #define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */
  34. #define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */
  35. #define PCR_TARGET_TIME_MASK 0x00006000U /* target time */
  36. #define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */
  37. #define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */
  38. #define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */
  39. #define SCOM_PSR 0x408001 /* PSR scom addr */
  40. /* warning: PSR is a 64 bits register */
  41. #define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */
  42. #define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */
  43. #define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
  44. #define PSR_CUR_SPEED_SHIFT (56)
  45. /*
  46. * The G5 only supports two frequencies (Quarter speed is not supported)
  47. */
  48. #define CPUFREQ_HIGH 0
  49. #define CPUFREQ_LOW 1
  50. static struct cpufreq_frequency_table maple_cpu_freqs[] = {
  51. {0, CPUFREQ_HIGH, 0},
  52. {0, CPUFREQ_LOW, 0},
  53. {0, 0, CPUFREQ_TABLE_END},
  54. };
  55. /* Power mode data is an array of the 32 bits PCR values to use for
  56. * the various frequencies, retrieved from the device-tree
  57. */
  58. static int maple_pmode_cur;
  59. static const u32 *maple_pmode_data;
  60. static int maple_pmode_max;
  61. /*
  62. * SCOM based frequency switching for 970FX rev3
  63. */
  64. static int maple_scom_switch_freq(int speed_mode)
  65. {
  66. unsigned long flags;
  67. int to;
  68. local_irq_save(flags);
  69. /* Clear PCR high */
  70. scom970_write(SCOM_PCR, 0);
  71. /* Clear PCR low */
  72. scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
  73. /* Set PCR low */
  74. scom970_write(SCOM_PCR, PCR_HILO_SELECT |
  75. maple_pmode_data[speed_mode]);
  76. /* Wait for completion */
  77. for (to = 0; to < 10; to++) {
  78. unsigned long psr = scom970_read(SCOM_PSR);
  79. if ((psr & PSR_CMD_RECEIVED) == 0 &&
  80. (((psr >> PSR_CUR_SPEED_SHIFT) ^
  81. (maple_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
  82. == 0)
  83. break;
  84. if (psr & PSR_CMD_COMPLETED)
  85. break;
  86. udelay(100);
  87. }
  88. local_irq_restore(flags);
  89. maple_pmode_cur = speed_mode;
  90. ppc_proc_freq = maple_cpu_freqs[speed_mode].frequency * 1000ul;
  91. return 0;
  92. }
  93. static int maple_scom_query_freq(void)
  94. {
  95. unsigned long psr = scom970_read(SCOM_PSR);
  96. int i;
  97. for (i = 0; i <= maple_pmode_max; i++)
  98. if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
  99. (maple_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
  100. break;
  101. return i;
  102. }
  103. /*
  104. * Common interface to the cpufreq core
  105. */
  106. static int maple_cpufreq_target(struct cpufreq_policy *policy,
  107. unsigned int index)
  108. {
  109. return maple_scom_switch_freq(index);
  110. }
  111. static unsigned int maple_cpufreq_get_speed(unsigned int cpu)
  112. {
  113. return maple_cpu_freqs[maple_pmode_cur].frequency;
  114. }
  115. static int maple_cpufreq_cpu_init(struct cpufreq_policy *policy)
  116. {
  117. cpufreq_generic_init(policy, maple_cpu_freqs, 12000);
  118. return 0;
  119. }
  120. static struct cpufreq_driver maple_cpufreq_driver = {
  121. .name = "maple",
  122. .flags = CPUFREQ_CONST_LOOPS,
  123. .init = maple_cpufreq_cpu_init,
  124. .verify = cpufreq_generic_frequency_table_verify,
  125. .target_index = maple_cpufreq_target,
  126. .get = maple_cpufreq_get_speed,
  127. .attr = cpufreq_generic_attr,
  128. };
  129. static int __init maple_cpufreq_init(void)
  130. {
  131. struct device_node *cpunode;
  132. unsigned int psize;
  133. unsigned long max_freq;
  134. const u32 *valp;
  135. u32 pvr_hi;
  136. int rc = -ENODEV;
  137. /*
  138. * Behave here like powermac driver which checks machine compatibility
  139. * to ease merging of two drivers in future.
  140. */
  141. if (!of_machine_is_compatible("Momentum,Maple") &&
  142. !of_machine_is_compatible("Momentum,Apache"))
  143. return 0;
  144. /* Get first CPU node */
  145. cpunode = of_cpu_device_node_get(0);
  146. if (cpunode == NULL) {
  147. pr_err("Can't find any CPU 0 node\n");
  148. goto bail_noprops;
  149. }
  150. /* Check 970FX for now */
  151. /* we actually don't care on which CPU to access PVR */
  152. pvr_hi = PVR_VER(mfspr(SPRN_PVR));
  153. if (pvr_hi != 0x3c && pvr_hi != 0x44) {
  154. pr_err("Unsupported CPU version (%x)\n", pvr_hi);
  155. goto bail_noprops;
  156. }
  157. /* Look for the powertune data in the device-tree */
  158. /*
  159. * On Maple this property is provided by PIBS in dual-processor config,
  160. * not provided by PIBS in CPU0 config and also not provided by SLOF,
  161. * so YMMV
  162. */
  163. maple_pmode_data = of_get_property(cpunode, "power-mode-data", &psize);
  164. if (!maple_pmode_data) {
  165. DBG("No power-mode-data !\n");
  166. goto bail_noprops;
  167. }
  168. maple_pmode_max = psize / sizeof(u32) - 1;
  169. /*
  170. * From what I see, clock-frequency is always the maximal frequency.
  171. * The current driver can not slew sysclk yet, so we really only deal
  172. * with powertune steps for now. We also only implement full freq and
  173. * half freq in this version. So far, I haven't yet seen a machine
  174. * supporting anything else.
  175. */
  176. valp = of_get_property(cpunode, "clock-frequency", NULL);
  177. if (!valp)
  178. goto bail_noprops;
  179. max_freq = (*valp)/1000;
  180. maple_cpu_freqs[0].frequency = max_freq;
  181. maple_cpu_freqs[1].frequency = max_freq/2;
  182. /* Force apply current frequency to make sure everything is in
  183. * sync (voltage is right for example). Firmware may leave us with
  184. * a strange setting ...
  185. */
  186. msleep(10);
  187. maple_pmode_cur = -1;
  188. maple_scom_switch_freq(maple_scom_query_freq());
  189. pr_info("Registering Maple CPU frequency driver\n");
  190. pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
  191. maple_cpu_freqs[1].frequency/1000,
  192. maple_cpu_freqs[0].frequency/1000,
  193. maple_cpu_freqs[maple_pmode_cur].frequency/1000);
  194. rc = cpufreq_register_driver(&maple_cpufreq_driver);
  195. bail_noprops:
  196. of_node_put(cpunode);
  197. return rc;
  198. }
  199. module_init(maple_cpufreq_init);
  200. MODULE_LICENSE("GPL");