longhaul.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * (C) 2001-2004 Dave Jones.
  4. * (C) 2002 Padraig Brady. <padraig@antefacto.com>
  5. *
  6. * Based upon datasheets & sample CPUs kindly provided by VIA.
  7. *
  8. * VIA have currently 3 different versions of Longhaul.
  9. * Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
  10. * It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
  11. * Version 2 of longhaul is backward compatible with v1, but adds
  12. * LONGHAUL MSR for purpose of both frequency and voltage scaling.
  13. * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
  14. * Version 3 of longhaul got renamed to Powersaver and redesigned
  15. * to use only the POWERSAVER MSR at 0x110a.
  16. * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
  17. * It's pretty much the same feature wise to longhaul v2, though
  18. * there is provision for scaling FSB too, but this doesn't work
  19. * too well in practice so we don't even try to use this.
  20. *
  21. * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
  22. */
  23. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/moduleparam.h>
  27. #include <linux/init.h>
  28. #include <linux/cpufreq.h>
  29. #include <linux/pci.h>
  30. #include <linux/slab.h>
  31. #include <linux/string.h>
  32. #include <linux/delay.h>
  33. #include <linux/timex.h>
  34. #include <linux/io.h>
  35. #include <linux/acpi.h>
  36. #include <asm/msr.h>
  37. #include <asm/cpu_device_id.h>
  38. #include <acpi/processor.h>
  39. #include "longhaul.h"
  40. #define TYPE_LONGHAUL_V1 1
  41. #define TYPE_LONGHAUL_V2 2
  42. #define TYPE_POWERSAVER 3
  43. #define CPU_SAMUEL 1
  44. #define CPU_SAMUEL2 2
  45. #define CPU_EZRA 3
  46. #define CPU_EZRA_T 4
  47. #define CPU_NEHEMIAH 5
  48. #define CPU_NEHEMIAH_C 6
  49. /* Flags */
  50. #define USE_ACPI_C3 (1 << 1)
  51. #define USE_NORTHBRIDGE (1 << 2)
  52. static int cpu_model;
  53. static unsigned int numscales = 16;
  54. static unsigned int fsb;
  55. static const struct mV_pos *vrm_mV_table;
  56. static const unsigned char *mV_vrm_table;
  57. static unsigned int highest_speed, lowest_speed; /* kHz */
  58. static unsigned int minmult, maxmult;
  59. static int can_scale_voltage;
  60. static struct acpi_processor *pr;
  61. static struct acpi_processor_cx *cx;
  62. static u32 acpi_regs_addr;
  63. static u8 longhaul_flags;
  64. static unsigned int longhaul_index;
  65. /* Module parameters */
  66. static int scale_voltage;
  67. static int disable_acpi_c3;
  68. static int revid_errata;
  69. static int enable;
  70. /* Clock ratios multiplied by 10 */
  71. static int mults[32];
  72. static int eblcr[32];
  73. static int longhaul_version;
  74. static struct cpufreq_frequency_table *longhaul_table;
  75. static char speedbuffer[8];
  76. static char *print_speed(int speed)
  77. {
  78. if (speed < 1000) {
  79. snprintf(speedbuffer, sizeof(speedbuffer), "%dMHz", speed);
  80. return speedbuffer;
  81. }
  82. if (speed%1000 == 0)
  83. snprintf(speedbuffer, sizeof(speedbuffer),
  84. "%dGHz", speed/1000);
  85. else
  86. snprintf(speedbuffer, sizeof(speedbuffer),
  87. "%d.%dGHz", speed/1000, (speed%1000)/100);
  88. return speedbuffer;
  89. }
  90. static unsigned int calc_speed(int mult)
  91. {
  92. int khz;
  93. khz = (mult/10)*fsb;
  94. if (mult%10)
  95. khz += fsb/2;
  96. khz *= 1000;
  97. return khz;
  98. }
  99. static int longhaul_get_cpu_mult(void)
  100. {
  101. unsigned long invalue = 0, lo, hi;
  102. rdmsr(MSR_IA32_EBL_CR_POWERON, lo, hi);
  103. invalue = (lo & (1<<22|1<<23|1<<24|1<<25))>>22;
  104. if (longhaul_version == TYPE_LONGHAUL_V2 ||
  105. longhaul_version == TYPE_POWERSAVER) {
  106. if (lo & (1<<27))
  107. invalue += 16;
  108. }
  109. return eblcr[invalue];
  110. }
  111. /* For processor with BCR2 MSR */
  112. static void do_longhaul1(unsigned int mults_index)
  113. {
  114. union msr_bcr2 bcr2;
  115. rdmsrl(MSR_VIA_BCR2, bcr2.val);
  116. /* Enable software clock multiplier */
  117. bcr2.bits.ESOFTBF = 1;
  118. bcr2.bits.CLOCKMUL = mults_index & 0xff;
  119. /* Sync to timer tick */
  120. safe_halt();
  121. /* Change frequency on next halt or sleep */
  122. wrmsrl(MSR_VIA_BCR2, bcr2.val);
  123. /* Invoke transition */
  124. ACPI_FLUSH_CPU_CACHE();
  125. halt();
  126. /* Disable software clock multiplier */
  127. local_irq_disable();
  128. rdmsrl(MSR_VIA_BCR2, bcr2.val);
  129. bcr2.bits.ESOFTBF = 0;
  130. wrmsrl(MSR_VIA_BCR2, bcr2.val);
  131. }
  132. /* For processor with Longhaul MSR */
  133. static void do_powersaver(int cx_address, unsigned int mults_index,
  134. unsigned int dir)
  135. {
  136. union msr_longhaul longhaul;
  137. u32 t;
  138. rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  139. /* Setup new frequency */
  140. if (!revid_errata)
  141. longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
  142. else
  143. longhaul.bits.RevisionKey = 0;
  144. longhaul.bits.SoftBusRatio = mults_index & 0xf;
  145. longhaul.bits.SoftBusRatio4 = (mults_index & 0x10) >> 4;
  146. /* Setup new voltage */
  147. if (can_scale_voltage)
  148. longhaul.bits.SoftVID = (mults_index >> 8) & 0x1f;
  149. /* Sync to timer tick */
  150. safe_halt();
  151. /* Raise voltage if necessary */
  152. if (can_scale_voltage && dir) {
  153. longhaul.bits.EnableSoftVID = 1;
  154. wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  155. /* Change voltage */
  156. if (!cx_address) {
  157. ACPI_FLUSH_CPU_CACHE();
  158. halt();
  159. } else {
  160. ACPI_FLUSH_CPU_CACHE();
  161. /* Invoke C3 */
  162. inb(cx_address);
  163. /* Dummy op - must do something useless after P_LVL3
  164. * read */
  165. t = inl(acpi_gbl_FADT.xpm_timer_block.address);
  166. }
  167. longhaul.bits.EnableSoftVID = 0;
  168. wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  169. }
  170. /* Change frequency on next halt or sleep */
  171. longhaul.bits.EnableSoftBusRatio = 1;
  172. wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  173. if (!cx_address) {
  174. ACPI_FLUSH_CPU_CACHE();
  175. halt();
  176. } else {
  177. ACPI_FLUSH_CPU_CACHE();
  178. /* Invoke C3 */
  179. inb(cx_address);
  180. /* Dummy op - must do something useless after P_LVL3 read */
  181. t = inl(acpi_gbl_FADT.xpm_timer_block.address);
  182. }
  183. /* Disable bus ratio bit */
  184. longhaul.bits.EnableSoftBusRatio = 0;
  185. wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  186. /* Reduce voltage if necessary */
  187. if (can_scale_voltage && !dir) {
  188. longhaul.bits.EnableSoftVID = 1;
  189. wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  190. /* Change voltage */
  191. if (!cx_address) {
  192. ACPI_FLUSH_CPU_CACHE();
  193. halt();
  194. } else {
  195. ACPI_FLUSH_CPU_CACHE();
  196. /* Invoke C3 */
  197. inb(cx_address);
  198. /* Dummy op - must do something useless after P_LVL3
  199. * read */
  200. t = inl(acpi_gbl_FADT.xpm_timer_block.address);
  201. }
  202. longhaul.bits.EnableSoftVID = 0;
  203. wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  204. }
  205. }
  206. /**
  207. * longhaul_set_cpu_frequency()
  208. * @mults_index : bitpattern of the new multiplier.
  209. *
  210. * Sets a new clock ratio.
  211. */
  212. static int longhaul_setstate(struct cpufreq_policy *policy,
  213. unsigned int table_index)
  214. {
  215. unsigned int mults_index;
  216. int speed, mult;
  217. struct cpufreq_freqs freqs;
  218. unsigned long flags;
  219. unsigned int pic1_mask, pic2_mask;
  220. u16 bm_status = 0;
  221. u32 bm_timeout = 1000;
  222. unsigned int dir = 0;
  223. mults_index = longhaul_table[table_index].driver_data;
  224. /* Safety precautions */
  225. mult = mults[mults_index & 0x1f];
  226. if (mult == -1)
  227. return -EINVAL;
  228. speed = calc_speed(mult);
  229. if ((speed > highest_speed) || (speed < lowest_speed))
  230. return -EINVAL;
  231. /* Voltage transition before frequency transition? */
  232. if (can_scale_voltage && longhaul_index < table_index)
  233. dir = 1;
  234. freqs.old = calc_speed(longhaul_get_cpu_mult());
  235. freqs.new = speed;
  236. pr_debug("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
  237. fsb, mult/10, mult%10, print_speed(speed/1000));
  238. retry_loop:
  239. preempt_disable();
  240. local_irq_save(flags);
  241. pic2_mask = inb(0xA1);
  242. pic1_mask = inb(0x21); /* works on C3. save mask. */
  243. outb(0xFF, 0xA1); /* Overkill */
  244. outb(0xFE, 0x21); /* TMR0 only */
  245. /* Wait while PCI bus is busy. */
  246. if (acpi_regs_addr && (longhaul_flags & USE_NORTHBRIDGE
  247. || ((pr != NULL) && pr->flags.bm_control))) {
  248. bm_status = inw(acpi_regs_addr);
  249. bm_status &= 1 << 4;
  250. while (bm_status && bm_timeout) {
  251. outw(1 << 4, acpi_regs_addr);
  252. bm_timeout--;
  253. bm_status = inw(acpi_regs_addr);
  254. bm_status &= 1 << 4;
  255. }
  256. }
  257. if (longhaul_flags & USE_NORTHBRIDGE) {
  258. /* Disable AGP and PCI arbiters */
  259. outb(3, 0x22);
  260. } else if ((pr != NULL) && pr->flags.bm_control) {
  261. /* Disable bus master arbitration */
  262. acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1);
  263. }
  264. switch (longhaul_version) {
  265. /*
  266. * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
  267. * Software controlled multipliers only.
  268. */
  269. case TYPE_LONGHAUL_V1:
  270. do_longhaul1(mults_index);
  271. break;
  272. /*
  273. * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5B] and Ezra [C5C]
  274. *
  275. * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
  276. * Nehemiah can do FSB scaling too, but this has never been proven
  277. * to work in practice.
  278. */
  279. case TYPE_LONGHAUL_V2:
  280. case TYPE_POWERSAVER:
  281. if (longhaul_flags & USE_ACPI_C3) {
  282. /* Don't allow wakeup */
  283. acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
  284. do_powersaver(cx->address, mults_index, dir);
  285. } else {
  286. do_powersaver(0, mults_index, dir);
  287. }
  288. break;
  289. }
  290. if (longhaul_flags & USE_NORTHBRIDGE) {
  291. /* Enable arbiters */
  292. outb(0, 0x22);
  293. } else if ((pr != NULL) && pr->flags.bm_control) {
  294. /* Enable bus master arbitration */
  295. acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0);
  296. }
  297. outb(pic2_mask, 0xA1); /* restore mask */
  298. outb(pic1_mask, 0x21);
  299. local_irq_restore(flags);
  300. preempt_enable();
  301. freqs.new = calc_speed(longhaul_get_cpu_mult());
  302. /* Check if requested frequency is set. */
  303. if (unlikely(freqs.new != speed)) {
  304. pr_info("Failed to set requested frequency!\n");
  305. /* Revision ID = 1 but processor is expecting revision key
  306. * equal to 0. Jumpers at the bottom of processor will change
  307. * multiplier and FSB, but will not change bits in Longhaul
  308. * MSR nor enable voltage scaling. */
  309. if (!revid_errata) {
  310. pr_info("Enabling \"Ignore Revision ID\" option\n");
  311. revid_errata = 1;
  312. msleep(200);
  313. goto retry_loop;
  314. }
  315. /* Why ACPI C3 sometimes doesn't work is a mystery for me.
  316. * But it does happen. Processor is entering ACPI C3 state,
  317. * but it doesn't change frequency. I tried poking various
  318. * bits in northbridge registers, but without success. */
  319. if (longhaul_flags & USE_ACPI_C3) {
  320. pr_info("Disabling ACPI C3 support\n");
  321. longhaul_flags &= ~USE_ACPI_C3;
  322. if (revid_errata) {
  323. pr_info("Disabling \"Ignore Revision ID\" option\n");
  324. revid_errata = 0;
  325. }
  326. msleep(200);
  327. goto retry_loop;
  328. }
  329. /* This shouldn't happen. Longhaul ver. 2 was reported not
  330. * working on processors without voltage scaling, but with
  331. * RevID = 1. RevID errata will make things right. Just
  332. * to be 100% sure. */
  333. if (longhaul_version == TYPE_LONGHAUL_V2) {
  334. pr_info("Switching to Longhaul ver. 1\n");
  335. longhaul_version = TYPE_LONGHAUL_V1;
  336. msleep(200);
  337. goto retry_loop;
  338. }
  339. }
  340. if (!bm_timeout) {
  341. pr_info("Warning: Timeout while waiting for idle PCI bus\n");
  342. return -EBUSY;
  343. }
  344. return 0;
  345. }
  346. /*
  347. * Centaur decided to make life a little more tricky.
  348. * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
  349. * Samuel2 and above have to try and guess what the FSB is.
  350. * We do this by assuming we booted at maximum multiplier, and interpolate
  351. * between that value multiplied by possible FSBs and cpu_mhz which
  352. * was calculated at boot time. Really ugly, but no other way to do this.
  353. */
  354. #define ROUNDING 0xf
  355. static int guess_fsb(int mult)
  356. {
  357. int speed = cpu_khz / 1000;
  358. int i;
  359. int speeds[] = { 666, 1000, 1333, 2000 };
  360. int f_max, f_min;
  361. for (i = 0; i < 4; i++) {
  362. f_max = ((speeds[i] * mult) + 50) / 100;
  363. f_max += (ROUNDING / 2);
  364. f_min = f_max - ROUNDING;
  365. if ((speed <= f_max) && (speed >= f_min))
  366. return speeds[i] / 10;
  367. }
  368. return 0;
  369. }
  370. static int longhaul_get_ranges(void)
  371. {
  372. unsigned int i, j, k = 0;
  373. unsigned int ratio;
  374. int mult;
  375. /* Get current frequency */
  376. mult = longhaul_get_cpu_mult();
  377. if (mult == -1) {
  378. pr_info("Invalid (reserved) multiplier!\n");
  379. return -EINVAL;
  380. }
  381. fsb = guess_fsb(mult);
  382. if (fsb == 0) {
  383. pr_info("Invalid (reserved) FSB!\n");
  384. return -EINVAL;
  385. }
  386. /* Get max multiplier - as we always did.
  387. * Longhaul MSR is useful only when voltage scaling is enabled.
  388. * C3 is booting at max anyway. */
  389. maxmult = mult;
  390. /* Get min multiplier */
  391. switch (cpu_model) {
  392. case CPU_NEHEMIAH:
  393. minmult = 50;
  394. break;
  395. case CPU_NEHEMIAH_C:
  396. minmult = 40;
  397. break;
  398. default:
  399. minmult = 30;
  400. break;
  401. }
  402. pr_debug("MinMult:%d.%dx MaxMult:%d.%dx\n",
  403. minmult/10, minmult%10, maxmult/10, maxmult%10);
  404. highest_speed = calc_speed(maxmult);
  405. lowest_speed = calc_speed(minmult);
  406. pr_debug("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb,
  407. print_speed(lowest_speed/1000),
  408. print_speed(highest_speed/1000));
  409. if (lowest_speed == highest_speed) {
  410. pr_info("highestspeed == lowest, aborting\n");
  411. return -EINVAL;
  412. }
  413. if (lowest_speed > highest_speed) {
  414. pr_info("nonsense! lowest (%d > %d) !\n",
  415. lowest_speed, highest_speed);
  416. return -EINVAL;
  417. }
  418. longhaul_table = kcalloc(numscales + 1, sizeof(*longhaul_table),
  419. GFP_KERNEL);
  420. if (!longhaul_table)
  421. return -ENOMEM;
  422. for (j = 0; j < numscales; j++) {
  423. ratio = mults[j];
  424. if (ratio == -1)
  425. continue;
  426. if (ratio > maxmult || ratio < minmult)
  427. continue;
  428. longhaul_table[k].frequency = calc_speed(ratio);
  429. longhaul_table[k].driver_data = j;
  430. k++;
  431. }
  432. if (k <= 1) {
  433. kfree(longhaul_table);
  434. return -ENODEV;
  435. }
  436. /* Sort */
  437. for (j = 0; j < k - 1; j++) {
  438. unsigned int min_f, min_i;
  439. min_f = longhaul_table[j].frequency;
  440. min_i = j;
  441. for (i = j + 1; i < k; i++) {
  442. if (longhaul_table[i].frequency < min_f) {
  443. min_f = longhaul_table[i].frequency;
  444. min_i = i;
  445. }
  446. }
  447. if (min_i != j) {
  448. swap(longhaul_table[j].frequency,
  449. longhaul_table[min_i].frequency);
  450. swap(longhaul_table[j].driver_data,
  451. longhaul_table[min_i].driver_data);
  452. }
  453. }
  454. longhaul_table[k].frequency = CPUFREQ_TABLE_END;
  455. /* Find index we are running on */
  456. for (j = 0; j < k; j++) {
  457. if (mults[longhaul_table[j].driver_data & 0x1f] == mult) {
  458. longhaul_index = j;
  459. break;
  460. }
  461. }
  462. return 0;
  463. }
  464. static void longhaul_setup_voltagescaling(void)
  465. {
  466. struct cpufreq_frequency_table *freq_pos;
  467. union msr_longhaul longhaul;
  468. struct mV_pos minvid, maxvid, vid;
  469. unsigned int j, speed, pos, kHz_step, numvscales;
  470. int min_vid_speed;
  471. rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  472. if (!(longhaul.bits.RevisionID & 1)) {
  473. pr_info("Voltage scaling not supported by CPU\n");
  474. return;
  475. }
  476. if (!longhaul.bits.VRMRev) {
  477. pr_info("VRM 8.5\n");
  478. vrm_mV_table = &vrm85_mV[0];
  479. mV_vrm_table = &mV_vrm85[0];
  480. } else {
  481. pr_info("Mobile VRM\n");
  482. if (cpu_model < CPU_NEHEMIAH)
  483. return;
  484. vrm_mV_table = &mobilevrm_mV[0];
  485. mV_vrm_table = &mV_mobilevrm[0];
  486. }
  487. minvid = vrm_mV_table[longhaul.bits.MinimumVID];
  488. maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
  489. if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
  490. pr_info("Bogus values Min:%d.%03d Max:%d.%03d - Voltage scaling disabled\n",
  491. minvid.mV/1000, minvid.mV%1000,
  492. maxvid.mV/1000, maxvid.mV%1000);
  493. return;
  494. }
  495. if (minvid.mV == maxvid.mV) {
  496. pr_info("Claims to support voltage scaling but min & max are both %d.%03d - Voltage scaling disabled\n",
  497. maxvid.mV/1000, maxvid.mV%1000);
  498. return;
  499. }
  500. /* How many voltage steps*/
  501. numvscales = maxvid.pos - minvid.pos + 1;
  502. pr_info("Max VID=%d.%03d Min VID=%d.%03d, %d possible voltage scales\n",
  503. maxvid.mV/1000, maxvid.mV%1000,
  504. minvid.mV/1000, minvid.mV%1000,
  505. numvscales);
  506. /* Calculate max frequency at min voltage */
  507. j = longhaul.bits.MinMHzBR;
  508. if (longhaul.bits.MinMHzBR4)
  509. j += 16;
  510. min_vid_speed = eblcr[j];
  511. if (min_vid_speed == -1)
  512. return;
  513. switch (longhaul.bits.MinMHzFSB) {
  514. case 0:
  515. min_vid_speed *= 13333;
  516. break;
  517. case 1:
  518. min_vid_speed *= 10000;
  519. break;
  520. case 3:
  521. min_vid_speed *= 6666;
  522. break;
  523. default:
  524. return;
  525. }
  526. if (min_vid_speed >= highest_speed)
  527. return;
  528. /* Calculate kHz for one voltage step */
  529. kHz_step = (highest_speed - min_vid_speed) / numvscales;
  530. cpufreq_for_each_entry_idx(freq_pos, longhaul_table, j) {
  531. speed = freq_pos->frequency;
  532. if (speed > min_vid_speed)
  533. pos = (speed - min_vid_speed) / kHz_step + minvid.pos;
  534. else
  535. pos = minvid.pos;
  536. freq_pos->driver_data |= mV_vrm_table[pos] << 8;
  537. vid = vrm_mV_table[mV_vrm_table[pos]];
  538. pr_info("f: %d kHz, index: %d, vid: %d mV\n",
  539. speed, j, vid.mV);
  540. }
  541. can_scale_voltage = 1;
  542. pr_info("Voltage scaling enabled\n");
  543. }
  544. static int longhaul_target(struct cpufreq_policy *policy,
  545. unsigned int table_index)
  546. {
  547. unsigned int i;
  548. unsigned int dir = 0;
  549. u8 vid, current_vid;
  550. int retval = 0;
  551. if (!can_scale_voltage)
  552. retval = longhaul_setstate(policy, table_index);
  553. else {
  554. /* On test system voltage transitions exceeding single
  555. * step up or down were turning motherboard off. Both
  556. * "ondemand" and "userspace" are unsafe. C7 is doing
  557. * this in hardware, C3 is old and we need to do this
  558. * in software. */
  559. i = longhaul_index;
  560. current_vid = (longhaul_table[longhaul_index].driver_data >> 8);
  561. current_vid &= 0x1f;
  562. if (table_index > longhaul_index)
  563. dir = 1;
  564. while (i != table_index) {
  565. vid = (longhaul_table[i].driver_data >> 8) & 0x1f;
  566. if (vid != current_vid) {
  567. retval = longhaul_setstate(policy, i);
  568. current_vid = vid;
  569. msleep(200);
  570. }
  571. if (dir)
  572. i++;
  573. else
  574. i--;
  575. }
  576. retval = longhaul_setstate(policy, table_index);
  577. }
  578. longhaul_index = table_index;
  579. return retval;
  580. }
  581. static unsigned int longhaul_get(unsigned int cpu)
  582. {
  583. if (cpu)
  584. return 0;
  585. return calc_speed(longhaul_get_cpu_mult());
  586. }
  587. static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
  588. u32 nesting_level,
  589. void *context, void **return_value)
  590. {
  591. struct acpi_device *d;
  592. if (acpi_bus_get_device(obj_handle, &d))
  593. return 0;
  594. *return_value = acpi_driver_data(d);
  595. return 1;
  596. }
  597. /* VIA don't support PM2 reg, but have something similar */
  598. static int enable_arbiter_disable(void)
  599. {
  600. struct pci_dev *dev;
  601. int status = 1;
  602. int reg;
  603. u8 pci_cmd;
  604. /* Find PLE133 host bridge */
  605. reg = 0x78;
  606. dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0,
  607. NULL);
  608. /* Find PM133/VT8605 host bridge */
  609. if (dev == NULL)
  610. dev = pci_get_device(PCI_VENDOR_ID_VIA,
  611. PCI_DEVICE_ID_VIA_8605_0, NULL);
  612. /* Find CLE266 host bridge */
  613. if (dev == NULL) {
  614. reg = 0x76;
  615. dev = pci_get_device(PCI_VENDOR_ID_VIA,
  616. PCI_DEVICE_ID_VIA_862X_0, NULL);
  617. /* Find CN400 V-Link host bridge */
  618. if (dev == NULL)
  619. dev = pci_get_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
  620. }
  621. if (dev != NULL) {
  622. /* Enable access to port 0x22 */
  623. pci_read_config_byte(dev, reg, &pci_cmd);
  624. if (!(pci_cmd & 1<<7)) {
  625. pci_cmd |= 1<<7;
  626. pci_write_config_byte(dev, reg, pci_cmd);
  627. pci_read_config_byte(dev, reg, &pci_cmd);
  628. if (!(pci_cmd & 1<<7)) {
  629. pr_err("Can't enable access to port 0x22\n");
  630. status = 0;
  631. }
  632. }
  633. pci_dev_put(dev);
  634. return status;
  635. }
  636. return 0;
  637. }
  638. static int longhaul_setup_southbridge(void)
  639. {
  640. struct pci_dev *dev;
  641. u8 pci_cmd;
  642. /* Find VT8235 southbridge */
  643. dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL);
  644. if (dev == NULL)
  645. /* Find VT8237 southbridge */
  646. dev = pci_get_device(PCI_VENDOR_ID_VIA,
  647. PCI_DEVICE_ID_VIA_8237, NULL);
  648. if (dev != NULL) {
  649. /* Set transition time to max */
  650. pci_read_config_byte(dev, 0xec, &pci_cmd);
  651. pci_cmd &= ~(1 << 2);
  652. pci_write_config_byte(dev, 0xec, pci_cmd);
  653. pci_read_config_byte(dev, 0xe4, &pci_cmd);
  654. pci_cmd &= ~(1 << 7);
  655. pci_write_config_byte(dev, 0xe4, pci_cmd);
  656. pci_read_config_byte(dev, 0xe5, &pci_cmd);
  657. pci_cmd |= 1 << 7;
  658. pci_write_config_byte(dev, 0xe5, pci_cmd);
  659. /* Get address of ACPI registers block*/
  660. pci_read_config_byte(dev, 0x81, &pci_cmd);
  661. if (pci_cmd & 1 << 7) {
  662. pci_read_config_dword(dev, 0x88, &acpi_regs_addr);
  663. acpi_regs_addr &= 0xff00;
  664. pr_info("ACPI I/O at 0x%x\n", acpi_regs_addr);
  665. }
  666. pci_dev_put(dev);
  667. return 1;
  668. }
  669. return 0;
  670. }
  671. static int longhaul_cpu_init(struct cpufreq_policy *policy)
  672. {
  673. struct cpuinfo_x86 *c = &cpu_data(0);
  674. char *cpuname = NULL;
  675. int ret;
  676. u32 lo, hi;
  677. /* Check what we have on this motherboard */
  678. switch (c->x86_model) {
  679. case 6:
  680. cpu_model = CPU_SAMUEL;
  681. cpuname = "C3 'Samuel' [C5A]";
  682. longhaul_version = TYPE_LONGHAUL_V1;
  683. memcpy(mults, samuel1_mults, sizeof(samuel1_mults));
  684. memcpy(eblcr, samuel1_eblcr, sizeof(samuel1_eblcr));
  685. break;
  686. case 7:
  687. switch (c->x86_stepping) {
  688. case 0:
  689. longhaul_version = TYPE_LONGHAUL_V1;
  690. cpu_model = CPU_SAMUEL2;
  691. cpuname = "C3 'Samuel 2' [C5B]";
  692. /* Note, this is not a typo, early Samuel2's had
  693. * Samuel1 ratios. */
  694. memcpy(mults, samuel1_mults, sizeof(samuel1_mults));
  695. memcpy(eblcr, samuel2_eblcr, sizeof(samuel2_eblcr));
  696. break;
  697. case 1 ... 15:
  698. longhaul_version = TYPE_LONGHAUL_V2;
  699. if (c->x86_stepping < 8) {
  700. cpu_model = CPU_SAMUEL2;
  701. cpuname = "C3 'Samuel 2' [C5B]";
  702. } else {
  703. cpu_model = CPU_EZRA;
  704. cpuname = "C3 'Ezra' [C5C]";
  705. }
  706. memcpy(mults, ezra_mults, sizeof(ezra_mults));
  707. memcpy(eblcr, ezra_eblcr, sizeof(ezra_eblcr));
  708. break;
  709. }
  710. break;
  711. case 8:
  712. cpu_model = CPU_EZRA_T;
  713. cpuname = "C3 'Ezra-T' [C5M]";
  714. longhaul_version = TYPE_POWERSAVER;
  715. numscales = 32;
  716. memcpy(mults, ezrat_mults, sizeof(ezrat_mults));
  717. memcpy(eblcr, ezrat_eblcr, sizeof(ezrat_eblcr));
  718. break;
  719. case 9:
  720. longhaul_version = TYPE_POWERSAVER;
  721. numscales = 32;
  722. memcpy(mults, nehemiah_mults, sizeof(nehemiah_mults));
  723. memcpy(eblcr, nehemiah_eblcr, sizeof(nehemiah_eblcr));
  724. switch (c->x86_stepping) {
  725. case 0 ... 1:
  726. cpu_model = CPU_NEHEMIAH;
  727. cpuname = "C3 'Nehemiah A' [C5XLOE]";
  728. break;
  729. case 2 ... 4:
  730. cpu_model = CPU_NEHEMIAH;
  731. cpuname = "C3 'Nehemiah B' [C5XLOH]";
  732. break;
  733. case 5 ... 15:
  734. cpu_model = CPU_NEHEMIAH_C;
  735. cpuname = "C3 'Nehemiah C' [C5P]";
  736. break;
  737. }
  738. break;
  739. default:
  740. cpuname = "Unknown";
  741. break;
  742. }
  743. /* Check Longhaul ver. 2 */
  744. if (longhaul_version == TYPE_LONGHAUL_V2) {
  745. rdmsr(MSR_VIA_LONGHAUL, lo, hi);
  746. if (lo == 0 && hi == 0)
  747. /* Looks like MSR isn't present */
  748. longhaul_version = TYPE_LONGHAUL_V1;
  749. }
  750. pr_info("VIA %s CPU detected. ", cpuname);
  751. switch (longhaul_version) {
  752. case TYPE_LONGHAUL_V1:
  753. case TYPE_LONGHAUL_V2:
  754. pr_cont("Longhaul v%d supported\n", longhaul_version);
  755. break;
  756. case TYPE_POWERSAVER:
  757. pr_cont("Powersaver supported\n");
  758. break;
  759. }
  760. /* Doesn't hurt */
  761. longhaul_setup_southbridge();
  762. /* Find ACPI data for processor */
  763. acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
  764. ACPI_UINT32_MAX, &longhaul_walk_callback, NULL,
  765. NULL, (void *)&pr);
  766. /* Check ACPI support for C3 state */
  767. if (pr != NULL && longhaul_version == TYPE_POWERSAVER) {
  768. cx = &pr->power.states[ACPI_STATE_C3];
  769. if (cx->address > 0 && cx->latency <= 1000)
  770. longhaul_flags |= USE_ACPI_C3;
  771. }
  772. /* Disable if it isn't working */
  773. if (disable_acpi_c3)
  774. longhaul_flags &= ~USE_ACPI_C3;
  775. /* Check if northbridge is friendly */
  776. if (enable_arbiter_disable())
  777. longhaul_flags |= USE_NORTHBRIDGE;
  778. /* Check ACPI support for bus master arbiter disable */
  779. if (!(longhaul_flags & USE_ACPI_C3
  780. || longhaul_flags & USE_NORTHBRIDGE)
  781. && ((pr == NULL) || !(pr->flags.bm_control))) {
  782. pr_err("No ACPI support: Unsupported northbridge\n");
  783. return -ENODEV;
  784. }
  785. if (longhaul_flags & USE_NORTHBRIDGE)
  786. pr_info("Using northbridge support\n");
  787. if (longhaul_flags & USE_ACPI_C3)
  788. pr_info("Using ACPI support\n");
  789. ret = longhaul_get_ranges();
  790. if (ret != 0)
  791. return ret;
  792. if ((longhaul_version != TYPE_LONGHAUL_V1) && (scale_voltage != 0))
  793. longhaul_setup_voltagescaling();
  794. policy->transition_delay_us = 200000; /* usec */
  795. policy->freq_table = longhaul_table;
  796. return 0;
  797. }
  798. static struct cpufreq_driver longhaul_driver = {
  799. .verify = cpufreq_generic_frequency_table_verify,
  800. .target_index = longhaul_target,
  801. .get = longhaul_get,
  802. .init = longhaul_cpu_init,
  803. .name = "longhaul",
  804. .attr = cpufreq_generic_attr,
  805. };
  806. static const struct x86_cpu_id longhaul_id[] = {
  807. X86_MATCH_VENDOR_FAM(CENTAUR, 6, NULL),
  808. {}
  809. };
  810. MODULE_DEVICE_TABLE(x86cpu, longhaul_id);
  811. static int __init longhaul_init(void)
  812. {
  813. struct cpuinfo_x86 *c = &cpu_data(0);
  814. if (!x86_match_cpu(longhaul_id))
  815. return -ENODEV;
  816. if (!enable) {
  817. pr_err("Option \"enable\" not set - Aborting\n");
  818. return -ENODEV;
  819. }
  820. #ifdef CONFIG_SMP
  821. if (num_online_cpus() > 1) {
  822. pr_err("More than 1 CPU detected, longhaul disabled\n");
  823. return -ENODEV;
  824. }
  825. #endif
  826. #ifdef CONFIG_X86_IO_APIC
  827. if (boot_cpu_has(X86_FEATURE_APIC)) {
  828. pr_err("APIC detected. Longhaul is currently broken in this configuration.\n");
  829. return -ENODEV;
  830. }
  831. #endif
  832. switch (c->x86_model) {
  833. case 6 ... 9:
  834. return cpufreq_register_driver(&longhaul_driver);
  835. case 10:
  836. pr_err("Use acpi-cpufreq driver for VIA C7\n");
  837. default:
  838. ;
  839. }
  840. return -ENODEV;
  841. }
  842. static void __exit longhaul_exit(void)
  843. {
  844. struct cpufreq_policy *policy = cpufreq_cpu_get(0);
  845. int i;
  846. for (i = 0; i < numscales; i++) {
  847. if (mults[i] == maxmult) {
  848. struct cpufreq_freqs freqs;
  849. freqs.old = policy->cur;
  850. freqs.new = longhaul_table[i].frequency;
  851. freqs.flags = 0;
  852. cpufreq_freq_transition_begin(policy, &freqs);
  853. longhaul_setstate(policy, i);
  854. cpufreq_freq_transition_end(policy, &freqs, 0);
  855. break;
  856. }
  857. }
  858. cpufreq_cpu_put(policy);
  859. cpufreq_unregister_driver(&longhaul_driver);
  860. kfree(longhaul_table);
  861. }
  862. /* Even if BIOS is exporting ACPI C3 state, and it is used
  863. * with success when CPU is idle, this state doesn't
  864. * trigger frequency transition in some cases. */
  865. module_param(disable_acpi_c3, int, 0644);
  866. MODULE_PARM_DESC(disable_acpi_c3, "Don't use ACPI C3 support");
  867. /* Change CPU voltage with frequency. Very useful to save
  868. * power, but most VIA C3 processors aren't supporting it. */
  869. module_param(scale_voltage, int, 0644);
  870. MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
  871. /* Force revision key to 0 for processors which doesn't
  872. * support voltage scaling, but are introducing itself as
  873. * such. */
  874. module_param(revid_errata, int, 0644);
  875. MODULE_PARM_DESC(revid_errata, "Ignore CPU Revision ID");
  876. /* By default driver is disabled to prevent incompatible
  877. * system freeze. */
  878. module_param(enable, int, 0644);
  879. MODULE_PARM_DESC(enable, "Enable driver");
  880. MODULE_AUTHOR("Dave Jones");
  881. MODULE_DESCRIPTION("Longhaul driver for VIA Cyrix processors.");
  882. MODULE_LICENSE("GPL");
  883. late_initcall(longhaul_init);
  884. module_exit(longhaul_exit);