imx6q-cpufreq.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/cpu.h>
  7. #include <linux/cpufreq.h>
  8. #include <linux/err.h>
  9. #include <linux/module.h>
  10. #include <linux/nvmem-consumer.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <linux/pm_opp.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/regulator/consumer.h>
  16. #define PU_SOC_VOLTAGE_NORMAL 1250000
  17. #define PU_SOC_VOLTAGE_HIGH 1275000
  18. #define FREQ_1P2_GHZ 1200000000
  19. static struct regulator *arm_reg;
  20. static struct regulator *pu_reg;
  21. static struct regulator *soc_reg;
  22. enum IMX6_CPUFREQ_CLKS {
  23. ARM,
  24. PLL1_SYS,
  25. STEP,
  26. PLL1_SW,
  27. PLL2_PFD2_396M,
  28. /* MX6UL requires two more clks */
  29. PLL2_BUS,
  30. SECONDARY_SEL,
  31. };
  32. #define IMX6Q_CPUFREQ_CLK_NUM 5
  33. #define IMX6UL_CPUFREQ_CLK_NUM 7
  34. static int num_clks;
  35. static struct clk_bulk_data clks[] = {
  36. { .id = "arm" },
  37. { .id = "pll1_sys" },
  38. { .id = "step" },
  39. { .id = "pll1_sw" },
  40. { .id = "pll2_pfd2_396m" },
  41. { .id = "pll2_bus" },
  42. { .id = "secondary_sel" },
  43. };
  44. static struct device *cpu_dev;
  45. static struct cpufreq_frequency_table *freq_table;
  46. static unsigned int max_freq;
  47. static unsigned int transition_latency;
  48. static u32 *imx6_soc_volt;
  49. static u32 soc_opp_count;
  50. static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
  51. {
  52. struct dev_pm_opp *opp;
  53. unsigned long freq_hz, volt, volt_old;
  54. unsigned int old_freq, new_freq;
  55. bool pll1_sys_temp_enabled = false;
  56. int ret;
  57. new_freq = freq_table[index].frequency;
  58. freq_hz = new_freq * 1000;
  59. old_freq = clk_get_rate(clks[ARM].clk) / 1000;
  60. opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
  61. if (IS_ERR(opp)) {
  62. dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
  63. return PTR_ERR(opp);
  64. }
  65. volt = dev_pm_opp_get_voltage(opp);
  66. dev_pm_opp_put(opp);
  67. volt_old = regulator_get_voltage(arm_reg);
  68. dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
  69. old_freq / 1000, volt_old / 1000,
  70. new_freq / 1000, volt / 1000);
  71. /* scaling up? scale voltage before frequency */
  72. if (new_freq > old_freq) {
  73. if (!IS_ERR(pu_reg)) {
  74. ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
  75. if (ret) {
  76. dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
  77. return ret;
  78. }
  79. }
  80. ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
  81. if (ret) {
  82. dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
  83. return ret;
  84. }
  85. ret = regulator_set_voltage_tol(arm_reg, volt, 0);
  86. if (ret) {
  87. dev_err(cpu_dev,
  88. "failed to scale vddarm up: %d\n", ret);
  89. return ret;
  90. }
  91. }
  92. /*
  93. * The setpoints are selected per PLL/PDF frequencies, so we need to
  94. * reprogram PLL for frequency scaling. The procedure of reprogramming
  95. * PLL1 is as below.
  96. * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
  97. * flow is slightly different from other i.MX6 OSC.
  98. * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
  99. * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
  100. * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
  101. * - Disable pll2_pfd2_396m_clk
  102. */
  103. if (of_machine_is_compatible("fsl,imx6ul") ||
  104. of_machine_is_compatible("fsl,imx6ull")) {
  105. /*
  106. * When changing pll1_sw_clk's parent to pll1_sys_clk,
  107. * CPU may run at higher than 528MHz, this will lead to
  108. * the system unstable if the voltage is lower than the
  109. * voltage of 528MHz, so lower the CPU frequency to one
  110. * half before changing CPU frequency.
  111. */
  112. clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
  113. clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
  114. if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
  115. clk_set_parent(clks[SECONDARY_SEL].clk,
  116. clks[PLL2_BUS].clk);
  117. else
  118. clk_set_parent(clks[SECONDARY_SEL].clk,
  119. clks[PLL2_PFD2_396M].clk);
  120. clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
  121. clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
  122. if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
  123. clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
  124. clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
  125. }
  126. } else {
  127. clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
  128. clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
  129. if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
  130. clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
  131. clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
  132. } else {
  133. /* pll1_sys needs to be enabled for divider rate change to work. */
  134. pll1_sys_temp_enabled = true;
  135. clk_prepare_enable(clks[PLL1_SYS].clk);
  136. }
  137. }
  138. /* Ensure the arm clock divider is what we expect */
  139. ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
  140. if (ret) {
  141. int ret1;
  142. dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
  143. ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0);
  144. if (ret1)
  145. dev_warn(cpu_dev,
  146. "failed to restore vddarm voltage: %d\n", ret1);
  147. return ret;
  148. }
  149. /* PLL1 is only needed until after ARM-PODF is set. */
  150. if (pll1_sys_temp_enabled)
  151. clk_disable_unprepare(clks[PLL1_SYS].clk);
  152. /* scaling down? scale voltage after frequency */
  153. if (new_freq < old_freq) {
  154. ret = regulator_set_voltage_tol(arm_reg, volt, 0);
  155. if (ret)
  156. dev_warn(cpu_dev,
  157. "failed to scale vddarm down: %d\n", ret);
  158. ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
  159. if (ret)
  160. dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
  161. if (!IS_ERR(pu_reg)) {
  162. ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
  163. if (ret)
  164. dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
  165. }
  166. }
  167. return 0;
  168. }
  169. static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
  170. {
  171. policy->clk = clks[ARM].clk;
  172. cpufreq_generic_init(policy, freq_table, transition_latency);
  173. policy->suspend_freq = max_freq;
  174. dev_pm_opp_of_register_em(cpu_dev, policy->cpus);
  175. return 0;
  176. }
  177. static struct cpufreq_driver imx6q_cpufreq_driver = {
  178. .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
  179. CPUFREQ_IS_COOLING_DEV,
  180. .verify = cpufreq_generic_frequency_table_verify,
  181. .target_index = imx6q_set_target,
  182. .get = cpufreq_generic_get,
  183. .init = imx6q_cpufreq_init,
  184. .name = "imx6q-cpufreq",
  185. .attr = cpufreq_generic_attr,
  186. .suspend = cpufreq_generic_suspend,
  187. };
  188. #define OCOTP_CFG3 0x440
  189. #define OCOTP_CFG3_SPEED_SHIFT 16
  190. #define OCOTP_CFG3_SPEED_1P2GHZ 0x3
  191. #define OCOTP_CFG3_SPEED_996MHZ 0x2
  192. #define OCOTP_CFG3_SPEED_852MHZ 0x1
  193. static int imx6q_opp_check_speed_grading(struct device *dev)
  194. {
  195. struct device_node *np;
  196. void __iomem *base;
  197. u32 val;
  198. int ret;
  199. if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
  200. ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
  201. if (ret)
  202. return ret;
  203. } else {
  204. np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
  205. if (!np)
  206. return -ENOENT;
  207. base = of_iomap(np, 0);
  208. of_node_put(np);
  209. if (!base) {
  210. dev_err(dev, "failed to map ocotp\n");
  211. return -EFAULT;
  212. }
  213. /*
  214. * SPEED_GRADING[1:0] defines the max speed of ARM:
  215. * 2b'11: 1200000000Hz;
  216. * 2b'10: 996000000Hz;
  217. * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
  218. * 2b'00: 792000000Hz;
  219. * We need to set the max speed of ARM according to fuse map.
  220. */
  221. val = readl_relaxed(base + OCOTP_CFG3);
  222. iounmap(base);
  223. }
  224. val >>= OCOTP_CFG3_SPEED_SHIFT;
  225. val &= 0x3;
  226. if (val < OCOTP_CFG3_SPEED_996MHZ)
  227. if (dev_pm_opp_disable(dev, 996000000))
  228. dev_warn(dev, "failed to disable 996MHz OPP\n");
  229. if (of_machine_is_compatible("fsl,imx6q") ||
  230. of_machine_is_compatible("fsl,imx6qp")) {
  231. if (val != OCOTP_CFG3_SPEED_852MHZ)
  232. if (dev_pm_opp_disable(dev, 852000000))
  233. dev_warn(dev, "failed to disable 852MHz OPP\n");
  234. if (val != OCOTP_CFG3_SPEED_1P2GHZ)
  235. if (dev_pm_opp_disable(dev, 1200000000))
  236. dev_warn(dev, "failed to disable 1.2GHz OPP\n");
  237. }
  238. return 0;
  239. }
  240. #define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
  241. #define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
  242. #define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
  243. static int imx6ul_opp_check_speed_grading(struct device *dev)
  244. {
  245. u32 val;
  246. int ret = 0;
  247. if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
  248. ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
  249. if (ret)
  250. return ret;
  251. } else {
  252. struct device_node *np;
  253. void __iomem *base;
  254. np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
  255. if (!np)
  256. np = of_find_compatible_node(NULL, NULL,
  257. "fsl,imx6ull-ocotp");
  258. if (!np)
  259. return -ENOENT;
  260. base = of_iomap(np, 0);
  261. of_node_put(np);
  262. if (!base) {
  263. dev_err(dev, "failed to map ocotp\n");
  264. return -EFAULT;
  265. }
  266. val = readl_relaxed(base + OCOTP_CFG3);
  267. iounmap(base);
  268. }
  269. /*
  270. * Speed GRADING[1:0] defines the max speed of ARM:
  271. * 2b'00: Reserved;
  272. * 2b'01: 528000000Hz;
  273. * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
  274. * 2b'11: 900000000Hz on i.MX6ULL only;
  275. * We need to set the max speed of ARM according to fuse map.
  276. */
  277. val >>= OCOTP_CFG3_SPEED_SHIFT;
  278. val &= 0x3;
  279. if (of_machine_is_compatible("fsl,imx6ul")) {
  280. if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
  281. if (dev_pm_opp_disable(dev, 696000000))
  282. dev_warn(dev, "failed to disable 696MHz OPP\n");
  283. }
  284. if (of_machine_is_compatible("fsl,imx6ull")) {
  285. if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
  286. if (dev_pm_opp_disable(dev, 792000000))
  287. dev_warn(dev, "failed to disable 792MHz OPP\n");
  288. if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
  289. if (dev_pm_opp_disable(dev, 900000000))
  290. dev_warn(dev, "failed to disable 900MHz OPP\n");
  291. }
  292. return ret;
  293. }
  294. static int imx6q_cpufreq_probe(struct platform_device *pdev)
  295. {
  296. struct device_node *np;
  297. struct dev_pm_opp *opp;
  298. unsigned long min_volt, max_volt;
  299. int num, ret;
  300. const struct property *prop;
  301. const __be32 *val;
  302. u32 nr, i, j;
  303. cpu_dev = get_cpu_device(0);
  304. if (!cpu_dev) {
  305. pr_err("failed to get cpu0 device\n");
  306. return -ENODEV;
  307. }
  308. np = of_node_get(cpu_dev->of_node);
  309. if (!np) {
  310. dev_err(cpu_dev, "failed to find cpu0 node\n");
  311. return -ENOENT;
  312. }
  313. if (of_machine_is_compatible("fsl,imx6ul") ||
  314. of_machine_is_compatible("fsl,imx6ull"))
  315. num_clks = IMX6UL_CPUFREQ_CLK_NUM;
  316. else
  317. num_clks = IMX6Q_CPUFREQ_CLK_NUM;
  318. ret = clk_bulk_get(cpu_dev, num_clks, clks);
  319. if (ret)
  320. goto put_node;
  321. arm_reg = regulator_get(cpu_dev, "arm");
  322. pu_reg = regulator_get_optional(cpu_dev, "pu");
  323. soc_reg = regulator_get(cpu_dev, "soc");
  324. if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
  325. PTR_ERR(soc_reg) == -EPROBE_DEFER ||
  326. PTR_ERR(pu_reg) == -EPROBE_DEFER) {
  327. ret = -EPROBE_DEFER;
  328. dev_dbg(cpu_dev, "regulators not ready, defer\n");
  329. goto put_reg;
  330. }
  331. if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
  332. dev_err(cpu_dev, "failed to get regulators\n");
  333. ret = -ENOENT;
  334. goto put_reg;
  335. }
  336. ret = dev_pm_opp_of_add_table(cpu_dev);
  337. if (ret < 0) {
  338. dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
  339. goto put_reg;
  340. }
  341. if (of_machine_is_compatible("fsl,imx6ul") ||
  342. of_machine_is_compatible("fsl,imx6ull")) {
  343. ret = imx6ul_opp_check_speed_grading(cpu_dev);
  344. } else {
  345. ret = imx6q_opp_check_speed_grading(cpu_dev);
  346. }
  347. if (ret) {
  348. if (ret != -EPROBE_DEFER)
  349. dev_err(cpu_dev, "failed to read ocotp: %d\n",
  350. ret);
  351. goto out_free_opp;
  352. }
  353. num = dev_pm_opp_get_opp_count(cpu_dev);
  354. if (num < 0) {
  355. ret = num;
  356. dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
  357. goto out_free_opp;
  358. }
  359. ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
  360. if (ret) {
  361. dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
  362. goto out_free_opp;
  363. }
  364. /* Make imx6_soc_volt array's size same as arm opp number */
  365. imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt),
  366. GFP_KERNEL);
  367. if (imx6_soc_volt == NULL) {
  368. ret = -ENOMEM;
  369. goto free_freq_table;
  370. }
  371. prop = of_find_property(np, "fsl,soc-operating-points", NULL);
  372. if (!prop || !prop->value)
  373. goto soc_opp_out;
  374. /*
  375. * Each OPP is a set of tuples consisting of frequency and
  376. * voltage like <freq-kHz vol-uV>.
  377. */
  378. nr = prop->length / sizeof(u32);
  379. if (nr % 2 || (nr / 2) < num)
  380. goto soc_opp_out;
  381. for (j = 0; j < num; j++) {
  382. val = prop->value;
  383. for (i = 0; i < nr / 2; i++) {
  384. unsigned long freq = be32_to_cpup(val++);
  385. unsigned long volt = be32_to_cpup(val++);
  386. if (freq_table[j].frequency == freq) {
  387. imx6_soc_volt[soc_opp_count++] = volt;
  388. break;
  389. }
  390. }
  391. }
  392. soc_opp_out:
  393. /* use fixed soc opp volt if no valid soc opp info found in dtb */
  394. if (soc_opp_count != num) {
  395. dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
  396. for (j = 0; j < num; j++)
  397. imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
  398. if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
  399. imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
  400. }
  401. if (of_property_read_u32(np, "clock-latency", &transition_latency))
  402. transition_latency = CPUFREQ_ETERNAL;
  403. /*
  404. * Calculate the ramp time for max voltage change in the
  405. * VDDSOC and VDDPU regulators.
  406. */
  407. ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
  408. if (ret > 0)
  409. transition_latency += ret * 1000;
  410. if (!IS_ERR(pu_reg)) {
  411. ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
  412. if (ret > 0)
  413. transition_latency += ret * 1000;
  414. }
  415. /*
  416. * OPP is maintained in order of increasing frequency, and
  417. * freq_table initialised from OPP is therefore sorted in the
  418. * same order.
  419. */
  420. max_freq = freq_table[--num].frequency;
  421. opp = dev_pm_opp_find_freq_exact(cpu_dev,
  422. freq_table[0].frequency * 1000, true);
  423. min_volt = dev_pm_opp_get_voltage(opp);
  424. dev_pm_opp_put(opp);
  425. opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
  426. max_volt = dev_pm_opp_get_voltage(opp);
  427. dev_pm_opp_put(opp);
  428. ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
  429. if (ret > 0)
  430. transition_latency += ret * 1000;
  431. ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
  432. if (ret) {
  433. dev_err(cpu_dev, "failed register driver: %d\n", ret);
  434. goto free_freq_table;
  435. }
  436. of_node_put(np);
  437. return 0;
  438. free_freq_table:
  439. dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
  440. out_free_opp:
  441. dev_pm_opp_of_remove_table(cpu_dev);
  442. put_reg:
  443. if (!IS_ERR(arm_reg))
  444. regulator_put(arm_reg);
  445. if (!IS_ERR(pu_reg))
  446. regulator_put(pu_reg);
  447. if (!IS_ERR(soc_reg))
  448. regulator_put(soc_reg);
  449. clk_bulk_put(num_clks, clks);
  450. put_node:
  451. of_node_put(np);
  452. return ret;
  453. }
  454. static int imx6q_cpufreq_remove(struct platform_device *pdev)
  455. {
  456. cpufreq_unregister_driver(&imx6q_cpufreq_driver);
  457. dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
  458. dev_pm_opp_of_remove_table(cpu_dev);
  459. regulator_put(arm_reg);
  460. if (!IS_ERR(pu_reg))
  461. regulator_put(pu_reg);
  462. regulator_put(soc_reg);
  463. clk_bulk_put(num_clks, clks);
  464. return 0;
  465. }
  466. static struct platform_driver imx6q_cpufreq_platdrv = {
  467. .driver = {
  468. .name = "imx6q-cpufreq",
  469. },
  470. .probe = imx6q_cpufreq_probe,
  471. .remove = imx6q_cpufreq_remove,
  472. };
  473. module_platform_driver(imx6q_cpufreq_platdrv);
  474. MODULE_ALIAS("platform:imx6q-cpufreq");
  475. MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
  476. MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
  477. MODULE_LICENSE("GPL");