imx-cpufreq-dt.c 5.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/cpu.h>
  7. #include <linux/cpufreq.h>
  8. #include <linux/err.h>
  9. #include <linux/init.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/nvmem-consumer.h>
  13. #include <linux/of.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm_opp.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/slab.h>
  18. #include "cpufreq-dt.h"
  19. #define OCOTP_CFG3_SPEED_GRADE_SHIFT 8
  20. #define OCOTP_CFG3_SPEED_GRADE_MASK (0x3 << 8)
  21. #define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK (0xf << 8)
  22. #define OCOTP_CFG3_MKT_SEGMENT_SHIFT 6
  23. #define OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 6)
  24. #define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT 5
  25. #define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 5)
  26. #define IMX7ULP_MAX_RUN_FREQ 528000
  27. /* cpufreq-dt device registered by imx-cpufreq-dt */
  28. static struct platform_device *cpufreq_dt_pdev;
  29. static struct opp_table *cpufreq_opp_table;
  30. static struct device *cpu_dev;
  31. enum IMX7ULP_CPUFREQ_CLKS {
  32. ARM,
  33. CORE,
  34. SCS_SEL,
  35. HSRUN_CORE,
  36. HSRUN_SCS_SEL,
  37. FIRC,
  38. };
  39. static struct clk_bulk_data imx7ulp_clks[] = {
  40. { .id = "arm" },
  41. { .id = "core" },
  42. { .id = "scs_sel" },
  43. { .id = "hsrun_core" },
  44. { .id = "hsrun_scs_sel" },
  45. { .id = "firc" },
  46. };
  47. static unsigned int imx7ulp_get_intermediate(struct cpufreq_policy *policy,
  48. unsigned int index)
  49. {
  50. return clk_get_rate(imx7ulp_clks[FIRC].clk);
  51. }
  52. static int imx7ulp_target_intermediate(struct cpufreq_policy *policy,
  53. unsigned int index)
  54. {
  55. unsigned int newfreq = policy->freq_table[index].frequency;
  56. clk_set_parent(imx7ulp_clks[SCS_SEL].clk, imx7ulp_clks[FIRC].clk);
  57. clk_set_parent(imx7ulp_clks[HSRUN_SCS_SEL].clk, imx7ulp_clks[FIRC].clk);
  58. if (newfreq > IMX7ULP_MAX_RUN_FREQ)
  59. clk_set_parent(imx7ulp_clks[ARM].clk,
  60. imx7ulp_clks[HSRUN_CORE].clk);
  61. else
  62. clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk);
  63. return 0;
  64. }
  65. static struct cpufreq_dt_platform_data imx7ulp_data = {
  66. .target_intermediate = imx7ulp_target_intermediate,
  67. .get_intermediate = imx7ulp_get_intermediate,
  68. };
  69. static int imx_cpufreq_dt_probe(struct platform_device *pdev)
  70. {
  71. struct platform_device *dt_pdev;
  72. u32 cell_value, supported_hw[2];
  73. int speed_grade, mkt_segment;
  74. int ret;
  75. cpu_dev = get_cpu_device(0);
  76. if (!of_find_property(cpu_dev->of_node, "cpu-supply", NULL))
  77. return -ENODEV;
  78. if (of_machine_is_compatible("fsl,imx7ulp")) {
  79. ret = clk_bulk_get(cpu_dev, ARRAY_SIZE(imx7ulp_clks),
  80. imx7ulp_clks);
  81. if (ret)
  82. return ret;
  83. dt_pdev = platform_device_register_data(NULL, "cpufreq-dt",
  84. -1, &imx7ulp_data,
  85. sizeof(imx7ulp_data));
  86. if (IS_ERR(dt_pdev)) {
  87. clk_bulk_put(ARRAY_SIZE(imx7ulp_clks), imx7ulp_clks);
  88. ret = PTR_ERR(dt_pdev);
  89. dev_err(&pdev->dev, "Failed to register cpufreq-dt: %d\n", ret);
  90. return ret;
  91. }
  92. cpufreq_dt_pdev = dt_pdev;
  93. return 0;
  94. }
  95. ret = nvmem_cell_read_u32(cpu_dev, "speed_grade", &cell_value);
  96. if (ret)
  97. return ret;
  98. if (of_machine_is_compatible("fsl,imx8mn") ||
  99. of_machine_is_compatible("fsl,imx8mp"))
  100. speed_grade = (cell_value & IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK)
  101. >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
  102. else
  103. speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK)
  104. >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
  105. if (of_machine_is_compatible("fsl,imx8mp"))
  106. mkt_segment = (cell_value & IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK)
  107. >> IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT;
  108. else
  109. mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK)
  110. >> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
  111. /*
  112. * Early samples without fuses written report "0 0" which may NOT
  113. * match any OPP defined in DT. So clamp to minimum OPP defined in
  114. * DT to avoid warning for "no OPPs".
  115. *
  116. * Applies to i.MX8M series SoCs.
  117. */
  118. if (mkt_segment == 0 && speed_grade == 0) {
  119. if (of_machine_is_compatible("fsl,imx8mm") ||
  120. of_machine_is_compatible("fsl,imx8mq"))
  121. speed_grade = 1;
  122. if (of_machine_is_compatible("fsl,imx8mn") ||
  123. of_machine_is_compatible("fsl,imx8mp"))
  124. speed_grade = 0xb;
  125. }
  126. supported_hw[0] = BIT(speed_grade);
  127. supported_hw[1] = BIT(mkt_segment);
  128. dev_info(&pdev->dev, "cpu speed grade %d mkt segment %d supported-hw %#x %#x\n",
  129. speed_grade, mkt_segment, supported_hw[0], supported_hw[1]);
  130. cpufreq_opp_table = dev_pm_opp_set_supported_hw(cpu_dev, supported_hw, 2);
  131. if (IS_ERR(cpufreq_opp_table)) {
  132. ret = PTR_ERR(cpufreq_opp_table);
  133. dev_err(&pdev->dev, "Failed to set supported opp: %d\n", ret);
  134. return ret;
  135. }
  136. cpufreq_dt_pdev = platform_device_register_data(
  137. &pdev->dev, "cpufreq-dt", -1, NULL, 0);
  138. if (IS_ERR(cpufreq_dt_pdev)) {
  139. dev_pm_opp_put_supported_hw(cpufreq_opp_table);
  140. ret = PTR_ERR(cpufreq_dt_pdev);
  141. dev_err(&pdev->dev, "Failed to register cpufreq-dt: %d\n", ret);
  142. return ret;
  143. }
  144. return 0;
  145. }
  146. static int imx_cpufreq_dt_remove(struct platform_device *pdev)
  147. {
  148. platform_device_unregister(cpufreq_dt_pdev);
  149. if (!of_machine_is_compatible("fsl,imx7ulp"))
  150. dev_pm_opp_put_supported_hw(cpufreq_opp_table);
  151. else
  152. clk_bulk_put(ARRAY_SIZE(imx7ulp_clks), imx7ulp_clks);
  153. return 0;
  154. }
  155. static struct platform_driver imx_cpufreq_dt_driver = {
  156. .probe = imx_cpufreq_dt_probe,
  157. .remove = imx_cpufreq_dt_remove,
  158. .driver = {
  159. .name = "imx-cpufreq-dt",
  160. },
  161. };
  162. module_platform_driver(imx_cpufreq_dt_driver);
  163. MODULE_ALIAS("platform:imx-cpufreq-dt");
  164. MODULE_DESCRIPTION("Freescale i.MX cpufreq speed grading driver");
  165. MODULE_LICENSE("GPL v2");