cpufreq-nforce2.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * (C) 2004-2006 Sebastian Witt <se.witt@gmx.net>
  4. *
  5. * Based upon reverse engineered information
  6. *
  7. * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
  8. */
  9. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/init.h>
  14. #include <linux/cpufreq.h>
  15. #include <linux/pci.h>
  16. #include <linux/delay.h>
  17. #define NFORCE2_XTAL 25
  18. #define NFORCE2_BOOTFSB 0x48
  19. #define NFORCE2_PLLENABLE 0xa8
  20. #define NFORCE2_PLLREG 0xa4
  21. #define NFORCE2_PLLADR 0xa0
  22. #define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div)
  23. #define NFORCE2_MIN_FSB 50
  24. #define NFORCE2_SAFE_DISTANCE 50
  25. /* Delay in ms between FSB changes */
  26. /* #define NFORCE2_DELAY 10 */
  27. /*
  28. * nforce2_chipset:
  29. * FSB is changed using the chipset
  30. */
  31. static struct pci_dev *nforce2_dev;
  32. /* fid:
  33. * multiplier * 10
  34. */
  35. static int fid;
  36. /* min_fsb, max_fsb:
  37. * minimum and maximum FSB (= FSB at boot time)
  38. */
  39. static int min_fsb;
  40. static int max_fsb;
  41. MODULE_AUTHOR("Sebastian Witt <se.witt@gmx.net>");
  42. MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver");
  43. MODULE_LICENSE("GPL");
  44. module_param(fid, int, 0444);
  45. module_param(min_fsb, int, 0444);
  46. MODULE_PARM_DESC(fid, "CPU multiplier to use (11.5 = 115)");
  47. MODULE_PARM_DESC(min_fsb,
  48. "Minimum FSB to use, if not defined: current FSB - 50");
  49. /**
  50. * nforce2_calc_fsb - calculate FSB
  51. * @pll: PLL value
  52. *
  53. * Calculates FSB from PLL value
  54. */
  55. static int nforce2_calc_fsb(int pll)
  56. {
  57. unsigned char mul, div;
  58. mul = (pll >> 8) & 0xff;
  59. div = pll & 0xff;
  60. if (div > 0)
  61. return NFORCE2_XTAL * mul / div;
  62. return 0;
  63. }
  64. /**
  65. * nforce2_calc_pll - calculate PLL value
  66. * @fsb: FSB
  67. *
  68. * Calculate PLL value for given FSB
  69. */
  70. static int nforce2_calc_pll(unsigned int fsb)
  71. {
  72. unsigned char xmul, xdiv;
  73. unsigned char mul = 0, div = 0;
  74. int tried = 0;
  75. /* Try to calculate multiplier and divider up to 4 times */
  76. while (((mul == 0) || (div == 0)) && (tried <= 3)) {
  77. for (xdiv = 2; xdiv <= 0x80; xdiv++)
  78. for (xmul = 1; xmul <= 0xfe; xmul++)
  79. if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) ==
  80. fsb + tried) {
  81. mul = xmul;
  82. div = xdiv;
  83. }
  84. tried++;
  85. }
  86. if ((mul == 0) || (div == 0))
  87. return -1;
  88. return NFORCE2_PLL(mul, div);
  89. }
  90. /**
  91. * nforce2_write_pll - write PLL value to chipset
  92. * @pll: PLL value
  93. *
  94. * Writes new FSB PLL value to chipset
  95. */
  96. static void nforce2_write_pll(int pll)
  97. {
  98. int temp;
  99. /* Set the pll addr. to 0x00 */
  100. pci_write_config_dword(nforce2_dev, NFORCE2_PLLADR, 0);
  101. /* Now write the value in all 64 registers */
  102. for (temp = 0; temp <= 0x3f; temp++)
  103. pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll);
  104. }
  105. /**
  106. * nforce2_fsb_read - Read FSB
  107. *
  108. * Read FSB from chipset
  109. * If bootfsb != 0, return FSB at boot-time
  110. */
  111. static unsigned int nforce2_fsb_read(int bootfsb)
  112. {
  113. struct pci_dev *nforce2_sub5;
  114. u32 fsb, temp = 0;
  115. /* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
  116. nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA, 0x01EF,
  117. PCI_ANY_ID, PCI_ANY_ID, NULL);
  118. if (!nforce2_sub5)
  119. return 0;
  120. pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
  121. fsb /= 1000000;
  122. /* Check if PLL register is already set */
  123. pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
  124. if (bootfsb || !temp)
  125. return fsb;
  126. /* Use PLL register FSB value */
  127. pci_read_config_dword(nforce2_dev, NFORCE2_PLLREG, &temp);
  128. fsb = nforce2_calc_fsb(temp);
  129. return fsb;
  130. }
  131. /**
  132. * nforce2_set_fsb - set new FSB
  133. * @fsb: New FSB
  134. *
  135. * Sets new FSB
  136. */
  137. static int nforce2_set_fsb(unsigned int fsb)
  138. {
  139. u32 temp = 0;
  140. unsigned int tfsb;
  141. int diff;
  142. int pll = 0;
  143. if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) {
  144. pr_err("FSB %d is out of range!\n", fsb);
  145. return -EINVAL;
  146. }
  147. tfsb = nforce2_fsb_read(0);
  148. if (!tfsb) {
  149. pr_err("Error while reading the FSB\n");
  150. return -EINVAL;
  151. }
  152. /* First write? Then set actual value */
  153. pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
  154. if (!temp) {
  155. pll = nforce2_calc_pll(tfsb);
  156. if (pll < 0)
  157. return -EINVAL;
  158. nforce2_write_pll(pll);
  159. }
  160. /* Enable write access */
  161. temp = 0x01;
  162. pci_write_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8)temp);
  163. diff = tfsb - fsb;
  164. if (!diff)
  165. return 0;
  166. while ((tfsb != fsb) && (tfsb <= max_fsb) && (tfsb >= min_fsb)) {
  167. if (diff < 0)
  168. tfsb++;
  169. else
  170. tfsb--;
  171. /* Calculate the PLL reg. value */
  172. pll = nforce2_calc_pll(tfsb);
  173. if (pll == -1)
  174. return -EINVAL;
  175. nforce2_write_pll(pll);
  176. #ifdef NFORCE2_DELAY
  177. mdelay(NFORCE2_DELAY);
  178. #endif
  179. }
  180. temp = 0x40;
  181. pci_write_config_byte(nforce2_dev, NFORCE2_PLLADR, (u8)temp);
  182. return 0;
  183. }
  184. /**
  185. * nforce2_get - get the CPU frequency
  186. * @cpu: CPU number
  187. *
  188. * Returns the CPU frequency
  189. */
  190. static unsigned int nforce2_get(unsigned int cpu)
  191. {
  192. if (cpu)
  193. return 0;
  194. return nforce2_fsb_read(0) * fid * 100;
  195. }
  196. /**
  197. * nforce2_target - set a new CPUFreq policy
  198. * @policy: new policy
  199. * @target_freq: the target frequency
  200. * @relation: how that frequency relates to achieved frequency
  201. * (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
  202. *
  203. * Sets a new CPUFreq policy.
  204. */
  205. static int nforce2_target(struct cpufreq_policy *policy,
  206. unsigned int target_freq, unsigned int relation)
  207. {
  208. /* unsigned long flags; */
  209. struct cpufreq_freqs freqs;
  210. unsigned int target_fsb;
  211. if ((target_freq > policy->max) || (target_freq < policy->min))
  212. return -EINVAL;
  213. target_fsb = target_freq / (fid * 100);
  214. freqs.old = nforce2_get(policy->cpu);
  215. freqs.new = target_fsb * fid * 100;
  216. if (freqs.old == freqs.new)
  217. return 0;
  218. pr_debug("Old CPU frequency %d kHz, new %d kHz\n",
  219. freqs.old, freqs.new);
  220. cpufreq_freq_transition_begin(policy, &freqs);
  221. /* Disable IRQs */
  222. /* local_irq_save(flags); */
  223. if (nforce2_set_fsb(target_fsb) < 0)
  224. pr_err("Changing FSB to %d failed\n", target_fsb);
  225. else
  226. pr_debug("Changed FSB successfully to %d\n",
  227. target_fsb);
  228. /* Enable IRQs */
  229. /* local_irq_restore(flags); */
  230. cpufreq_freq_transition_end(policy, &freqs, 0);
  231. return 0;
  232. }
  233. /**
  234. * nforce2_verify - verifies a new CPUFreq policy
  235. * @policy: new policy
  236. */
  237. static int nforce2_verify(struct cpufreq_policy_data *policy)
  238. {
  239. unsigned int fsb_pol_max;
  240. fsb_pol_max = policy->max / (fid * 100);
  241. if (policy->min < (fsb_pol_max * fid * 100))
  242. policy->max = (fsb_pol_max + 1) * fid * 100;
  243. cpufreq_verify_within_cpu_limits(policy);
  244. return 0;
  245. }
  246. static int nforce2_cpu_init(struct cpufreq_policy *policy)
  247. {
  248. unsigned int fsb;
  249. unsigned int rfid;
  250. /* capability check */
  251. if (policy->cpu != 0)
  252. return -ENODEV;
  253. /* Get current FSB */
  254. fsb = nforce2_fsb_read(0);
  255. if (!fsb)
  256. return -EIO;
  257. /* FIX: Get FID from CPU */
  258. if (!fid) {
  259. if (!cpu_khz) {
  260. pr_warn("cpu_khz not set, can't calculate multiplier!\n");
  261. return -ENODEV;
  262. }
  263. fid = cpu_khz / (fsb * 100);
  264. rfid = fid % 5;
  265. if (rfid) {
  266. if (rfid > 2)
  267. fid += 5 - rfid;
  268. else
  269. fid -= rfid;
  270. }
  271. }
  272. pr_info("FSB currently at %i MHz, FID %d.%d\n",
  273. fsb, fid / 10, fid % 10);
  274. /* Set maximum FSB to FSB at boot time */
  275. max_fsb = nforce2_fsb_read(1);
  276. if (!max_fsb)
  277. return -EIO;
  278. if (!min_fsb)
  279. min_fsb = max_fsb - NFORCE2_SAFE_DISTANCE;
  280. if (min_fsb < NFORCE2_MIN_FSB)
  281. min_fsb = NFORCE2_MIN_FSB;
  282. /* cpuinfo and default policy values */
  283. policy->min = policy->cpuinfo.min_freq = min_fsb * fid * 100;
  284. policy->max = policy->cpuinfo.max_freq = max_fsb * fid * 100;
  285. return 0;
  286. }
  287. static int nforce2_cpu_exit(struct cpufreq_policy *policy)
  288. {
  289. return 0;
  290. }
  291. static struct cpufreq_driver nforce2_driver = {
  292. .name = "nforce2",
  293. .flags = CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING,
  294. .verify = nforce2_verify,
  295. .target = nforce2_target,
  296. .get = nforce2_get,
  297. .init = nforce2_cpu_init,
  298. .exit = nforce2_cpu_exit,
  299. };
  300. #ifdef MODULE
  301. static const struct pci_device_id nforce2_ids[] = {
  302. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2 },
  303. {}
  304. };
  305. MODULE_DEVICE_TABLE(pci, nforce2_ids);
  306. #endif
  307. /**
  308. * nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
  309. *
  310. * Detects nForce2 A2 and C1 stepping
  311. *
  312. */
  313. static int nforce2_detect_chipset(void)
  314. {
  315. nforce2_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
  316. PCI_DEVICE_ID_NVIDIA_NFORCE2,
  317. PCI_ANY_ID, PCI_ANY_ID, NULL);
  318. if (nforce2_dev == NULL)
  319. return -ENODEV;
  320. pr_info("Detected nForce2 chipset revision %X\n",
  321. nforce2_dev->revision);
  322. pr_info("FSB changing is maybe unstable and can lead to crashes and data loss\n");
  323. return 0;
  324. }
  325. /**
  326. * nforce2_init - initializes the nForce2 CPUFreq driver
  327. *
  328. * Initializes the nForce2 FSB support. Returns -ENODEV on unsupported
  329. * devices, -EINVAL on problems during initialization, and zero on
  330. * success.
  331. */
  332. static int __init nforce2_init(void)
  333. {
  334. /* TODO: do we need to detect the processor? */
  335. /* detect chipset */
  336. if (nforce2_detect_chipset()) {
  337. pr_info("No nForce2 chipset\n");
  338. return -ENODEV;
  339. }
  340. return cpufreq_register_driver(&nforce2_driver);
  341. }
  342. /**
  343. * nforce2_exit - unregisters cpufreq module
  344. *
  345. * Unregisters nForce2 FSB change support.
  346. */
  347. static void __exit nforce2_exit(void)
  348. {
  349. cpufreq_unregister_driver(&nforce2_driver);
  350. }
  351. module_init(nforce2_init);
  352. module_exit(nforce2_exit);