armada-37xx-cpufreq.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * CPU frequency scaling support for Armada 37xx platform.
  4. *
  5. * Copyright (C) 2017 Marvell
  6. *
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/cpu.h>
  11. #include <linux/cpufreq.h>
  12. #include <linux/err.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/mfd/syscon.h>
  16. #include <linux/module.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_device.h>
  19. #include <linux/of_irq.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pm_opp.h>
  22. #include <linux/regmap.h>
  23. #include <linux/slab.h>
  24. #include "cpufreq-dt.h"
  25. /* Clk register set */
  26. #define ARMADA_37XX_CLK_TBG_SEL 0
  27. #define ARMADA_37XX_CLK_TBG_SEL_CPU_OFF 22
  28. /* Power management in North Bridge register set */
  29. #define ARMADA_37XX_NB_L0L1 0x18
  30. #define ARMADA_37XX_NB_L2L3 0x1C
  31. #define ARMADA_37XX_NB_TBG_DIV_OFF 13
  32. #define ARMADA_37XX_NB_TBG_DIV_MASK 0x7
  33. #define ARMADA_37XX_NB_CLK_SEL_OFF 11
  34. #define ARMADA_37XX_NB_CLK_SEL_MASK 0x1
  35. #define ARMADA_37XX_NB_CLK_SEL_TBG 0x1
  36. #define ARMADA_37XX_NB_TBG_SEL_OFF 9
  37. #define ARMADA_37XX_NB_TBG_SEL_MASK 0x3
  38. #define ARMADA_37XX_NB_VDD_SEL_OFF 6
  39. #define ARMADA_37XX_NB_VDD_SEL_MASK 0x3
  40. #define ARMADA_37XX_NB_CONFIG_SHIFT 16
  41. #define ARMADA_37XX_NB_DYN_MOD 0x24
  42. #define ARMADA_37XX_NB_CLK_SEL_EN BIT(26)
  43. #define ARMADA_37XX_NB_TBG_EN BIT(28)
  44. #define ARMADA_37XX_NB_DIV_EN BIT(29)
  45. #define ARMADA_37XX_NB_VDD_EN BIT(30)
  46. #define ARMADA_37XX_NB_DFS_EN BIT(31)
  47. #define ARMADA_37XX_NB_CPU_LOAD 0x30
  48. #define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3
  49. #define ARMADA_37XX_DVFS_LOAD_0 0
  50. #define ARMADA_37XX_DVFS_LOAD_1 1
  51. #define ARMADA_37XX_DVFS_LOAD_2 2
  52. #define ARMADA_37XX_DVFS_LOAD_3 3
  53. /* AVS register set */
  54. #define ARMADA_37XX_AVS_CTL0 0x0
  55. #define ARMADA_37XX_AVS_ENABLE BIT(30)
  56. #define ARMADA_37XX_AVS_HIGH_VDD_LIMIT 16
  57. #define ARMADA_37XX_AVS_LOW_VDD_LIMIT 22
  58. #define ARMADA_37XX_AVS_VDD_MASK 0x3F
  59. #define ARMADA_37XX_AVS_CTL2 0x8
  60. #define ARMADA_37XX_AVS_LOW_VDD_EN BIT(6)
  61. #define ARMADA_37XX_AVS_VSET(x) (0x1C + 4 * (x))
  62. /*
  63. * On Armada 37xx the Power management manages 4 level of CPU load,
  64. * each level can be associated with a CPU clock source, a CPU
  65. * divider, a VDD level, etc...
  66. */
  67. #define LOAD_LEVEL_NR 4
  68. #define MIN_VOLT_MV 1000
  69. #define MIN_VOLT_MV_FOR_L1_1000MHZ 1108
  70. #define MIN_VOLT_MV_FOR_L1_1200MHZ 1155
  71. /* AVS value for the corresponding voltage (in mV) */
  72. static int avs_map[] = {
  73. 747, 758, 770, 782, 793, 805, 817, 828, 840, 852, 863, 875, 887, 898,
  74. 910, 922, 933, 945, 957, 968, 980, 992, 1003, 1015, 1027, 1038, 1050,
  75. 1062, 1073, 1085, 1097, 1108, 1120, 1132, 1143, 1155, 1167, 1178, 1190,
  76. 1202, 1213, 1225, 1237, 1248, 1260, 1272, 1283, 1295, 1307, 1318, 1330,
  77. 1342
  78. };
  79. struct armada37xx_cpufreq_state {
  80. struct regmap *regmap;
  81. u32 nb_l0l1;
  82. u32 nb_l2l3;
  83. u32 nb_dyn_mod;
  84. u32 nb_cpu_load;
  85. };
  86. static struct armada37xx_cpufreq_state *armada37xx_cpufreq_state;
  87. struct armada_37xx_dvfs {
  88. u32 cpu_freq_max;
  89. u8 divider[LOAD_LEVEL_NR];
  90. u32 avs[LOAD_LEVEL_NR];
  91. };
  92. static struct armada_37xx_dvfs armada_37xx_dvfs[] = {
  93. /*
  94. * The cpufreq scaling for 1.2 GHz variant of the SOC is currently
  95. * unstable because we do not know how to configure it properly.
  96. */
  97. /* {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} }, */
  98. {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
  99. {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
  100. {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
  101. };
  102. static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq)
  103. {
  104. int i;
  105. for (i = 0; i < ARRAY_SIZE(armada_37xx_dvfs); i++) {
  106. if (freq == armada_37xx_dvfs[i].cpu_freq_max)
  107. return &armada_37xx_dvfs[i];
  108. }
  109. pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000);
  110. return NULL;
  111. }
  112. /*
  113. * Setup the four level managed by the hardware. Once the four level
  114. * will be configured then the DVFS will be enabled.
  115. */
  116. static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
  117. struct regmap *clk_base, u8 *divider)
  118. {
  119. u32 cpu_tbg_sel;
  120. int load_lvl;
  121. /* Determine to which TBG clock is CPU connected */
  122. regmap_read(clk_base, ARMADA_37XX_CLK_TBG_SEL, &cpu_tbg_sel);
  123. cpu_tbg_sel >>= ARMADA_37XX_CLK_TBG_SEL_CPU_OFF;
  124. cpu_tbg_sel &= ARMADA_37XX_NB_TBG_SEL_MASK;
  125. for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
  126. unsigned int reg, mask, val, offset = 0;
  127. if (load_lvl <= ARMADA_37XX_DVFS_LOAD_1)
  128. reg = ARMADA_37XX_NB_L0L1;
  129. else
  130. reg = ARMADA_37XX_NB_L2L3;
  131. if (load_lvl == ARMADA_37XX_DVFS_LOAD_0 ||
  132. load_lvl == ARMADA_37XX_DVFS_LOAD_2)
  133. offset += ARMADA_37XX_NB_CONFIG_SHIFT;
  134. /* Set cpu clock source, for all the level we use TBG */
  135. val = ARMADA_37XX_NB_CLK_SEL_TBG << ARMADA_37XX_NB_CLK_SEL_OFF;
  136. mask = (ARMADA_37XX_NB_CLK_SEL_MASK
  137. << ARMADA_37XX_NB_CLK_SEL_OFF);
  138. /* Set TBG index, for all levels we use the same TBG */
  139. val = cpu_tbg_sel << ARMADA_37XX_NB_TBG_SEL_OFF;
  140. mask = (ARMADA_37XX_NB_TBG_SEL_MASK
  141. << ARMADA_37XX_NB_TBG_SEL_OFF);
  142. /*
  143. * Set cpu divider based on the pre-computed array in
  144. * order to have balanced step.
  145. */
  146. val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF;
  147. mask |= (ARMADA_37XX_NB_TBG_DIV_MASK
  148. << ARMADA_37XX_NB_TBG_DIV_OFF);
  149. /* Set VDD divider which is actually the load level. */
  150. val |= load_lvl << ARMADA_37XX_NB_VDD_SEL_OFF;
  151. mask |= (ARMADA_37XX_NB_VDD_SEL_MASK
  152. << ARMADA_37XX_NB_VDD_SEL_OFF);
  153. val <<= offset;
  154. mask <<= offset;
  155. regmap_update_bits(base, reg, mask, val);
  156. }
  157. }
  158. /*
  159. * Find out the armada 37x supported AVS value whose voltage value is
  160. * the round-up closest to the target voltage value.
  161. */
  162. static u32 armada_37xx_avs_val_match(int target_vm)
  163. {
  164. u32 avs;
  165. /* Find out the round-up closest supported voltage value */
  166. for (avs = 0; avs < ARRAY_SIZE(avs_map); avs++)
  167. if (avs_map[avs] >= target_vm)
  168. break;
  169. /*
  170. * If all supported voltages are smaller than target one,
  171. * choose the largest supported voltage
  172. */
  173. if (avs == ARRAY_SIZE(avs_map))
  174. avs = ARRAY_SIZE(avs_map) - 1;
  175. return avs;
  176. }
  177. /*
  178. * For Armada 37xx soc, L0(VSET0) VDD AVS value is set to SVC revision
  179. * value or a default value when SVC is not supported.
  180. * - L0 can be read out from the register of AVS_CTRL_0 and L0 voltage
  181. * can be got from the mapping table of avs_map.
  182. * - L1 voltage should be about 100mv smaller than L0 voltage
  183. * - L2 & L3 voltage should be about 150mv smaller than L0 voltage.
  184. * This function calculates L1 & L2 & L3 AVS values dynamically based
  185. * on L0 voltage and fill all AVS values to the AVS value table.
  186. * When base CPU frequency is 1000 or 1200 MHz then there is additional
  187. * minimal avs value for load L1.
  188. */
  189. static void __init armada37xx_cpufreq_avs_configure(struct regmap *base,
  190. struct armada_37xx_dvfs *dvfs)
  191. {
  192. unsigned int target_vm;
  193. int load_level = 0;
  194. u32 l0_vdd_min;
  195. if (base == NULL)
  196. return;
  197. /* Get L0 VDD min value */
  198. regmap_read(base, ARMADA_37XX_AVS_CTL0, &l0_vdd_min);
  199. l0_vdd_min = (l0_vdd_min >> ARMADA_37XX_AVS_LOW_VDD_LIMIT) &
  200. ARMADA_37XX_AVS_VDD_MASK;
  201. if (l0_vdd_min >= ARRAY_SIZE(avs_map)) {
  202. pr_err("L0 VDD MIN %d is not correct.\n", l0_vdd_min);
  203. return;
  204. }
  205. dvfs->avs[0] = l0_vdd_min;
  206. if (avs_map[l0_vdd_min] <= MIN_VOLT_MV) {
  207. /*
  208. * If L0 voltage is smaller than 1000mv, then all VDD sets
  209. * use L0 voltage;
  210. */
  211. u32 avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV);
  212. for (load_level = 1; load_level < LOAD_LEVEL_NR; load_level++)
  213. dvfs->avs[load_level] = avs_min;
  214. /*
  215. * Set the avs values for load L0 and L1 when base CPU frequency
  216. * is 1000/1200 MHz to its typical initial values according to
  217. * the Armada 3700 Hardware Specifications.
  218. */
  219. if (dvfs->cpu_freq_max >= 1000*1000*1000) {
  220. if (dvfs->cpu_freq_max >= 1200*1000*1000)
  221. avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1200MHZ);
  222. else
  223. avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1000MHZ);
  224. dvfs->avs[0] = dvfs->avs[1] = avs_min;
  225. }
  226. return;
  227. }
  228. /*
  229. * L1 voltage is equal to L0 voltage - 100mv and it must be
  230. * larger than 1000mv
  231. */
  232. target_vm = avs_map[l0_vdd_min] - 100;
  233. target_vm = target_vm > MIN_VOLT_MV ? target_vm : MIN_VOLT_MV;
  234. dvfs->avs[1] = armada_37xx_avs_val_match(target_vm);
  235. /*
  236. * L2 & L3 voltage is equal to L0 voltage - 150mv and it must
  237. * be larger than 1000mv
  238. */
  239. target_vm = avs_map[l0_vdd_min] - 150;
  240. target_vm = target_vm > MIN_VOLT_MV ? target_vm : MIN_VOLT_MV;
  241. dvfs->avs[2] = dvfs->avs[3] = armada_37xx_avs_val_match(target_vm);
  242. /*
  243. * Fix the avs value for load L1 when base CPU frequency is 1000/1200 MHz,
  244. * otherwise the CPU gets stuck when switching from load L1 to load L0.
  245. * Also ensure that avs value for load L1 is not higher than for L0.
  246. */
  247. if (dvfs->cpu_freq_max >= 1000*1000*1000) {
  248. u32 avs_min_l1;
  249. if (dvfs->cpu_freq_max >= 1200*1000*1000)
  250. avs_min_l1 = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1200MHZ);
  251. else
  252. avs_min_l1 = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1000MHZ);
  253. if (avs_min_l1 > dvfs->avs[0])
  254. avs_min_l1 = dvfs->avs[0];
  255. if (dvfs->avs[1] < avs_min_l1)
  256. dvfs->avs[1] = avs_min_l1;
  257. }
  258. }
  259. static void __init armada37xx_cpufreq_avs_setup(struct regmap *base,
  260. struct armada_37xx_dvfs *dvfs)
  261. {
  262. unsigned int avs_val = 0;
  263. int load_level = 0;
  264. if (base == NULL)
  265. return;
  266. /* Disable AVS before the configuration */
  267. regmap_update_bits(base, ARMADA_37XX_AVS_CTL0,
  268. ARMADA_37XX_AVS_ENABLE, 0);
  269. /* Enable low voltage mode */
  270. regmap_update_bits(base, ARMADA_37XX_AVS_CTL2,
  271. ARMADA_37XX_AVS_LOW_VDD_EN,
  272. ARMADA_37XX_AVS_LOW_VDD_EN);
  273. for (load_level = 1; load_level < LOAD_LEVEL_NR; load_level++) {
  274. avs_val = dvfs->avs[load_level];
  275. regmap_update_bits(base, ARMADA_37XX_AVS_VSET(load_level-1),
  276. ARMADA_37XX_AVS_VDD_MASK << ARMADA_37XX_AVS_HIGH_VDD_LIMIT |
  277. ARMADA_37XX_AVS_VDD_MASK << ARMADA_37XX_AVS_LOW_VDD_LIMIT,
  278. avs_val << ARMADA_37XX_AVS_HIGH_VDD_LIMIT |
  279. avs_val << ARMADA_37XX_AVS_LOW_VDD_LIMIT);
  280. }
  281. /* Enable AVS after the configuration */
  282. regmap_update_bits(base, ARMADA_37XX_AVS_CTL0,
  283. ARMADA_37XX_AVS_ENABLE,
  284. ARMADA_37XX_AVS_ENABLE);
  285. }
  286. static void armada37xx_cpufreq_disable_dvfs(struct regmap *base)
  287. {
  288. unsigned int reg = ARMADA_37XX_NB_DYN_MOD,
  289. mask = ARMADA_37XX_NB_DFS_EN;
  290. regmap_update_bits(base, reg, mask, 0);
  291. }
  292. static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base)
  293. {
  294. unsigned int val, reg = ARMADA_37XX_NB_CPU_LOAD,
  295. mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
  296. /* Start with the highest load (0) */
  297. val = ARMADA_37XX_DVFS_LOAD_0;
  298. regmap_update_bits(base, reg, mask, val);
  299. /* Now enable DVFS for the CPUs */
  300. reg = ARMADA_37XX_NB_DYN_MOD;
  301. mask = ARMADA_37XX_NB_CLK_SEL_EN | ARMADA_37XX_NB_TBG_EN |
  302. ARMADA_37XX_NB_DIV_EN | ARMADA_37XX_NB_VDD_EN |
  303. ARMADA_37XX_NB_DFS_EN;
  304. regmap_update_bits(base, reg, mask, mask);
  305. }
  306. static int armada37xx_cpufreq_suspend(struct cpufreq_policy *policy)
  307. {
  308. struct armada37xx_cpufreq_state *state = armada37xx_cpufreq_state;
  309. regmap_read(state->regmap, ARMADA_37XX_NB_L0L1, &state->nb_l0l1);
  310. regmap_read(state->regmap, ARMADA_37XX_NB_L2L3, &state->nb_l2l3);
  311. regmap_read(state->regmap, ARMADA_37XX_NB_CPU_LOAD,
  312. &state->nb_cpu_load);
  313. regmap_read(state->regmap, ARMADA_37XX_NB_DYN_MOD, &state->nb_dyn_mod);
  314. return 0;
  315. }
  316. static int armada37xx_cpufreq_resume(struct cpufreq_policy *policy)
  317. {
  318. struct armada37xx_cpufreq_state *state = armada37xx_cpufreq_state;
  319. /* Ensure DVFS is disabled otherwise the following registers are RO */
  320. armada37xx_cpufreq_disable_dvfs(state->regmap);
  321. regmap_write(state->regmap, ARMADA_37XX_NB_L0L1, state->nb_l0l1);
  322. regmap_write(state->regmap, ARMADA_37XX_NB_L2L3, state->nb_l2l3);
  323. regmap_write(state->regmap, ARMADA_37XX_NB_CPU_LOAD,
  324. state->nb_cpu_load);
  325. /*
  326. * NB_DYN_MOD register is the one that actually enable back DVFS if it
  327. * was enabled before the suspend operation. This must be done last
  328. * otherwise other registers are not writable.
  329. */
  330. regmap_write(state->regmap, ARMADA_37XX_NB_DYN_MOD, state->nb_dyn_mod);
  331. return 0;
  332. }
  333. static int __init armada37xx_cpufreq_driver_init(void)
  334. {
  335. struct cpufreq_dt_platform_data pdata;
  336. struct armada_37xx_dvfs *dvfs;
  337. struct platform_device *pdev;
  338. unsigned long freq;
  339. unsigned int cur_frequency, base_frequency;
  340. struct regmap *nb_clk_base, *nb_pm_base, *avs_base;
  341. struct device *cpu_dev;
  342. int load_lvl, ret;
  343. struct clk *clk, *parent;
  344. nb_clk_base =
  345. syscon_regmap_lookup_by_compatible("marvell,armada-3700-periph-clock-nb");
  346. if (IS_ERR(nb_clk_base))
  347. return -ENODEV;
  348. nb_pm_base =
  349. syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
  350. if (IS_ERR(nb_pm_base))
  351. return -ENODEV;
  352. avs_base =
  353. syscon_regmap_lookup_by_compatible("marvell,armada-3700-avs");
  354. /* if AVS is not present don't use it but still try to setup dvfs */
  355. if (IS_ERR(avs_base)) {
  356. pr_info("Syscon failed for Adapting Voltage Scaling: skip it\n");
  357. avs_base = NULL;
  358. }
  359. /* Before doing any configuration on the DVFS first, disable it */
  360. armada37xx_cpufreq_disable_dvfs(nb_pm_base);
  361. /*
  362. * On CPU 0 register the operating points supported (which are
  363. * the nominal CPU frequency and full integer divisions of
  364. * it).
  365. */
  366. cpu_dev = get_cpu_device(0);
  367. if (!cpu_dev) {
  368. dev_err(cpu_dev, "Cannot get CPU\n");
  369. return -ENODEV;
  370. }
  371. clk = clk_get(cpu_dev, 0);
  372. if (IS_ERR(clk)) {
  373. dev_err(cpu_dev, "Cannot get clock for CPU0\n");
  374. return PTR_ERR(clk);
  375. }
  376. parent = clk_get_parent(clk);
  377. if (IS_ERR(parent)) {
  378. dev_err(cpu_dev, "Cannot get parent clock for CPU0\n");
  379. clk_put(clk);
  380. return PTR_ERR(parent);
  381. }
  382. /* Get parent CPU frequency */
  383. base_frequency = clk_get_rate(parent);
  384. if (!base_frequency) {
  385. dev_err(cpu_dev, "Failed to get parent clock rate for CPU\n");
  386. clk_put(clk);
  387. return -EINVAL;
  388. }
  389. /* Get nominal (current) CPU frequency */
  390. cur_frequency = clk_get_rate(clk);
  391. if (!cur_frequency) {
  392. dev_err(cpu_dev, "Failed to get clock rate for CPU\n");
  393. clk_put(clk);
  394. return -EINVAL;
  395. }
  396. dvfs = armada_37xx_cpu_freq_info_get(base_frequency);
  397. if (!dvfs) {
  398. clk_put(clk);
  399. return -EINVAL;
  400. }
  401. armada37xx_cpufreq_state = kmalloc(sizeof(*armada37xx_cpufreq_state),
  402. GFP_KERNEL);
  403. if (!armada37xx_cpufreq_state) {
  404. clk_put(clk);
  405. return -ENOMEM;
  406. }
  407. armada37xx_cpufreq_state->regmap = nb_pm_base;
  408. armada37xx_cpufreq_avs_configure(avs_base, dvfs);
  409. armada37xx_cpufreq_avs_setup(avs_base, dvfs);
  410. armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider);
  411. clk_put(clk);
  412. for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
  413. load_lvl++) {
  414. unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
  415. freq = base_frequency / dvfs->divider[load_lvl];
  416. ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
  417. if (ret)
  418. goto remove_opp;
  419. }
  420. /* Now that everything is setup, enable the DVFS at hardware level */
  421. armada37xx_cpufreq_enable_dvfs(nb_pm_base);
  422. memset(&pdata, 0, sizeof(pdata));
  423. pdata.suspend = armada37xx_cpufreq_suspend;
  424. pdata.resume = armada37xx_cpufreq_resume;
  425. pdev = platform_device_register_data(NULL, "cpufreq-dt", -1, &pdata,
  426. sizeof(pdata));
  427. ret = PTR_ERR_OR_ZERO(pdev);
  428. if (ret)
  429. goto disable_dvfs;
  430. return 0;
  431. disable_dvfs:
  432. armada37xx_cpufreq_disable_dvfs(nb_pm_base);
  433. remove_opp:
  434. /* clean-up the already added opp before leaving */
  435. while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {
  436. freq = base_frequency / dvfs->divider[load_lvl];
  437. dev_pm_opp_remove(cpu_dev, freq);
  438. }
  439. kfree(armada37xx_cpufreq_state);
  440. return ret;
  441. }
  442. /* late_initcall, to guarantee the driver is loaded after A37xx clock driver */
  443. late_initcall(armada37xx_cpufreq_driver_init);
  444. static const struct of_device_id __maybe_unused armada37xx_cpufreq_of_match[] = {
  445. { .compatible = "marvell,armada-3700-nb-pm" },
  446. { },
  447. };
  448. MODULE_DEVICE_TABLE(of, armada37xx_cpufreq_of_match);
  449. MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
  450. MODULE_DESCRIPTION("Armada 37xx cpufreq driver");
  451. MODULE_LICENSE("GPL");