ti-eqep.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2019 David Lechner <david@lechnology.com>
  4. *
  5. * Counter driver for Texas Instruments Enhanced Quadrature Encoder Pulse (eQEP)
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/counter.h>
  9. #include <linux/kernel.h>
  10. #include <linux/mod_devicetable.h>
  11. #include <linux/module.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/regmap.h>
  15. /* 32-bit registers */
  16. #define QPOSCNT 0x0
  17. #define QPOSINIT 0x4
  18. #define QPOSMAX 0x8
  19. #define QPOSCMP 0xc
  20. #define QPOSILAT 0x10
  21. #define QPOSSLAT 0x14
  22. #define QPOSLAT 0x18
  23. #define QUTMR 0x1c
  24. #define QUPRD 0x20
  25. /* 16-bit registers */
  26. #define QWDTMR 0x0 /* 0x24 */
  27. #define QWDPRD 0x2 /* 0x26 */
  28. #define QDECCTL 0x4 /* 0x28 */
  29. #define QEPCTL 0x6 /* 0x2a */
  30. #define QCAPCTL 0x8 /* 0x2c */
  31. #define QPOSCTL 0xa /* 0x2e */
  32. #define QEINT 0xc /* 0x30 */
  33. #define QFLG 0xe /* 0x32 */
  34. #define QCLR 0x10 /* 0x34 */
  35. #define QFRC 0x12 /* 0x36 */
  36. #define QEPSTS 0x14 /* 0x38 */
  37. #define QCTMR 0x16 /* 0x3a */
  38. #define QCPRD 0x18 /* 0x3c */
  39. #define QCTMRLAT 0x1a /* 0x3e */
  40. #define QCPRDLAT 0x1c /* 0x40 */
  41. #define QDECCTL_QSRC_SHIFT 14
  42. #define QDECCTL_QSRC GENMASK(15, 14)
  43. #define QDECCTL_SOEN BIT(13)
  44. #define QDECCTL_SPSEL BIT(12)
  45. #define QDECCTL_XCR BIT(11)
  46. #define QDECCTL_SWAP BIT(10)
  47. #define QDECCTL_IGATE BIT(9)
  48. #define QDECCTL_QAP BIT(8)
  49. #define QDECCTL_QBP BIT(7)
  50. #define QDECCTL_QIP BIT(6)
  51. #define QDECCTL_QSP BIT(5)
  52. #define QEPCTL_FREE_SOFT GENMASK(15, 14)
  53. #define QEPCTL_PCRM GENMASK(13, 12)
  54. #define QEPCTL_SEI GENMASK(11, 10)
  55. #define QEPCTL_IEI GENMASK(9, 8)
  56. #define QEPCTL_SWI BIT(7)
  57. #define QEPCTL_SEL BIT(6)
  58. #define QEPCTL_IEL GENMASK(5, 4)
  59. #define QEPCTL_PHEN BIT(3)
  60. #define QEPCTL_QCLM BIT(2)
  61. #define QEPCTL_UTE BIT(1)
  62. #define QEPCTL_WDE BIT(0)
  63. /* EQEP Inputs */
  64. enum {
  65. TI_EQEP_SIGNAL_QEPA, /* QEPA/XCLK */
  66. TI_EQEP_SIGNAL_QEPB, /* QEPB/XDIR */
  67. };
  68. /* Position Counter Input Modes */
  69. enum {
  70. TI_EQEP_COUNT_FUNC_QUAD_COUNT,
  71. TI_EQEP_COUNT_FUNC_DIR_COUNT,
  72. TI_EQEP_COUNT_FUNC_UP_COUNT,
  73. TI_EQEP_COUNT_FUNC_DOWN_COUNT,
  74. };
  75. enum {
  76. TI_EQEP_SYNAPSE_ACTION_BOTH_EDGES,
  77. TI_EQEP_SYNAPSE_ACTION_RISING_EDGE,
  78. TI_EQEP_SYNAPSE_ACTION_NONE,
  79. };
  80. struct ti_eqep_cnt {
  81. struct counter_device counter;
  82. struct regmap *regmap32;
  83. struct regmap *regmap16;
  84. };
  85. static int ti_eqep_count_read(struct counter_device *counter,
  86. struct counter_count *count, unsigned long *val)
  87. {
  88. struct ti_eqep_cnt *priv = counter->priv;
  89. u32 cnt;
  90. regmap_read(priv->regmap32, QPOSCNT, &cnt);
  91. *val = cnt;
  92. return 0;
  93. }
  94. static int ti_eqep_count_write(struct counter_device *counter,
  95. struct counter_count *count, unsigned long val)
  96. {
  97. struct ti_eqep_cnt *priv = counter->priv;
  98. u32 max;
  99. regmap_read(priv->regmap32, QPOSMAX, &max);
  100. if (val > max)
  101. return -EINVAL;
  102. return regmap_write(priv->regmap32, QPOSCNT, val);
  103. }
  104. static int ti_eqep_function_get(struct counter_device *counter,
  105. struct counter_count *count, size_t *function)
  106. {
  107. struct ti_eqep_cnt *priv = counter->priv;
  108. u32 qdecctl;
  109. regmap_read(priv->regmap16, QDECCTL, &qdecctl);
  110. *function = (qdecctl & QDECCTL_QSRC) >> QDECCTL_QSRC_SHIFT;
  111. return 0;
  112. }
  113. static int ti_eqep_function_set(struct counter_device *counter,
  114. struct counter_count *count, size_t function)
  115. {
  116. struct ti_eqep_cnt *priv = counter->priv;
  117. return regmap_write_bits(priv->regmap16, QDECCTL, QDECCTL_QSRC,
  118. function << QDECCTL_QSRC_SHIFT);
  119. }
  120. static int ti_eqep_action_get(struct counter_device *counter,
  121. struct counter_count *count,
  122. struct counter_synapse *synapse, size_t *action)
  123. {
  124. struct ti_eqep_cnt *priv = counter->priv;
  125. size_t function;
  126. u32 qdecctl;
  127. int err;
  128. err = ti_eqep_function_get(counter, count, &function);
  129. if (err)
  130. return err;
  131. switch (function) {
  132. case TI_EQEP_COUNT_FUNC_QUAD_COUNT:
  133. /* In quadrature mode, the rising and falling edge of both
  134. * QEPA and QEPB trigger QCLK.
  135. */
  136. *action = TI_EQEP_SYNAPSE_ACTION_BOTH_EDGES;
  137. break;
  138. case TI_EQEP_COUNT_FUNC_DIR_COUNT:
  139. /* In direction-count mode only rising edge of QEPA is counted
  140. * and QEPB gives direction.
  141. */
  142. switch (synapse->signal->id) {
  143. case TI_EQEP_SIGNAL_QEPA:
  144. *action = TI_EQEP_SYNAPSE_ACTION_RISING_EDGE;
  145. break;
  146. default:
  147. *action = TI_EQEP_SYNAPSE_ACTION_NONE;
  148. break;
  149. }
  150. break;
  151. case TI_EQEP_COUNT_FUNC_UP_COUNT:
  152. case TI_EQEP_COUNT_FUNC_DOWN_COUNT:
  153. /* In up/down-count modes only QEPA is counted and QEPB is not
  154. * used.
  155. */
  156. switch (synapse->signal->id) {
  157. case TI_EQEP_SIGNAL_QEPA:
  158. err = regmap_read(priv->regmap16, QDECCTL, &qdecctl);
  159. if (err)
  160. return err;
  161. if (qdecctl & QDECCTL_XCR)
  162. *action = TI_EQEP_SYNAPSE_ACTION_BOTH_EDGES;
  163. else
  164. *action = TI_EQEP_SYNAPSE_ACTION_RISING_EDGE;
  165. break;
  166. default:
  167. *action = TI_EQEP_SYNAPSE_ACTION_NONE;
  168. break;
  169. }
  170. break;
  171. }
  172. return 0;
  173. }
  174. static const struct counter_ops ti_eqep_counter_ops = {
  175. .count_read = ti_eqep_count_read,
  176. .count_write = ti_eqep_count_write,
  177. .function_get = ti_eqep_function_get,
  178. .function_set = ti_eqep_function_set,
  179. .action_get = ti_eqep_action_get,
  180. };
  181. static ssize_t ti_eqep_position_ceiling_read(struct counter_device *counter,
  182. struct counter_count *count,
  183. void *ext_priv, char *buf)
  184. {
  185. struct ti_eqep_cnt *priv = counter->priv;
  186. u32 qposmax;
  187. regmap_read(priv->regmap32, QPOSMAX, &qposmax);
  188. return sprintf(buf, "%u\n", qposmax);
  189. }
  190. static ssize_t ti_eqep_position_ceiling_write(struct counter_device *counter,
  191. struct counter_count *count,
  192. void *ext_priv, const char *buf,
  193. size_t len)
  194. {
  195. struct ti_eqep_cnt *priv = counter->priv;
  196. int err;
  197. u32 res;
  198. err = kstrtouint(buf, 0, &res);
  199. if (err < 0)
  200. return err;
  201. regmap_write(priv->regmap32, QPOSMAX, res);
  202. return len;
  203. }
  204. static ssize_t ti_eqep_position_enable_read(struct counter_device *counter,
  205. struct counter_count *count,
  206. void *ext_priv, char *buf)
  207. {
  208. struct ti_eqep_cnt *priv = counter->priv;
  209. u32 qepctl;
  210. regmap_read(priv->regmap16, QEPCTL, &qepctl);
  211. return sprintf(buf, "%u\n", !!(qepctl & QEPCTL_PHEN));
  212. }
  213. static ssize_t ti_eqep_position_enable_write(struct counter_device *counter,
  214. struct counter_count *count,
  215. void *ext_priv, const char *buf,
  216. size_t len)
  217. {
  218. struct ti_eqep_cnt *priv = counter->priv;
  219. int err;
  220. bool res;
  221. err = kstrtobool(buf, &res);
  222. if (err < 0)
  223. return err;
  224. regmap_write_bits(priv->regmap16, QEPCTL, QEPCTL_PHEN, res ? -1 : 0);
  225. return len;
  226. }
  227. static struct counter_count_ext ti_eqep_position_ext[] = {
  228. {
  229. .name = "ceiling",
  230. .read = ti_eqep_position_ceiling_read,
  231. .write = ti_eqep_position_ceiling_write,
  232. },
  233. {
  234. .name = "enable",
  235. .read = ti_eqep_position_enable_read,
  236. .write = ti_eqep_position_enable_write,
  237. },
  238. };
  239. static struct counter_signal ti_eqep_signals[] = {
  240. [TI_EQEP_SIGNAL_QEPA] = {
  241. .id = TI_EQEP_SIGNAL_QEPA,
  242. .name = "QEPA"
  243. },
  244. [TI_EQEP_SIGNAL_QEPB] = {
  245. .id = TI_EQEP_SIGNAL_QEPB,
  246. .name = "QEPB"
  247. },
  248. };
  249. static const enum counter_count_function ti_eqep_position_functions[] = {
  250. [TI_EQEP_COUNT_FUNC_QUAD_COUNT] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
  251. [TI_EQEP_COUNT_FUNC_DIR_COUNT] = COUNTER_COUNT_FUNCTION_PULSE_DIRECTION,
  252. [TI_EQEP_COUNT_FUNC_UP_COUNT] = COUNTER_COUNT_FUNCTION_INCREASE,
  253. [TI_EQEP_COUNT_FUNC_DOWN_COUNT] = COUNTER_COUNT_FUNCTION_DECREASE,
  254. };
  255. static const enum counter_synapse_action ti_eqep_position_synapse_actions[] = {
  256. [TI_EQEP_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
  257. [TI_EQEP_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
  258. [TI_EQEP_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
  259. };
  260. static struct counter_synapse ti_eqep_position_synapses[] = {
  261. {
  262. .actions_list = ti_eqep_position_synapse_actions,
  263. .num_actions = ARRAY_SIZE(ti_eqep_position_synapse_actions),
  264. .signal = &ti_eqep_signals[TI_EQEP_SIGNAL_QEPA],
  265. },
  266. {
  267. .actions_list = ti_eqep_position_synapse_actions,
  268. .num_actions = ARRAY_SIZE(ti_eqep_position_synapse_actions),
  269. .signal = &ti_eqep_signals[TI_EQEP_SIGNAL_QEPB],
  270. },
  271. };
  272. static struct counter_count ti_eqep_counts[] = {
  273. {
  274. .id = 0,
  275. .name = "QPOSCNT",
  276. .functions_list = ti_eqep_position_functions,
  277. .num_functions = ARRAY_SIZE(ti_eqep_position_functions),
  278. .synapses = ti_eqep_position_synapses,
  279. .num_synapses = ARRAY_SIZE(ti_eqep_position_synapses),
  280. .ext = ti_eqep_position_ext,
  281. .num_ext = ARRAY_SIZE(ti_eqep_position_ext),
  282. },
  283. };
  284. static const struct regmap_config ti_eqep_regmap32_config = {
  285. .name = "32-bit",
  286. .reg_bits = 32,
  287. .val_bits = 32,
  288. .reg_stride = 4,
  289. .max_register = QUPRD,
  290. };
  291. static const struct regmap_config ti_eqep_regmap16_config = {
  292. .name = "16-bit",
  293. .reg_bits = 16,
  294. .val_bits = 16,
  295. .reg_stride = 2,
  296. .max_register = QCPRDLAT,
  297. };
  298. static int ti_eqep_probe(struct platform_device *pdev)
  299. {
  300. struct device *dev = &pdev->dev;
  301. struct ti_eqep_cnt *priv;
  302. void __iomem *base;
  303. int err;
  304. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  305. if (!priv)
  306. return -ENOMEM;
  307. base = devm_platform_ioremap_resource(pdev, 0);
  308. if (IS_ERR(base))
  309. return PTR_ERR(base);
  310. priv->regmap32 = devm_regmap_init_mmio(dev, base,
  311. &ti_eqep_regmap32_config);
  312. if (IS_ERR(priv->regmap32))
  313. return PTR_ERR(priv->regmap32);
  314. priv->regmap16 = devm_regmap_init_mmio(dev, base + 0x24,
  315. &ti_eqep_regmap16_config);
  316. if (IS_ERR(priv->regmap16))
  317. return PTR_ERR(priv->regmap16);
  318. priv->counter.name = dev_name(dev);
  319. priv->counter.parent = dev;
  320. priv->counter.ops = &ti_eqep_counter_ops;
  321. priv->counter.counts = ti_eqep_counts;
  322. priv->counter.num_counts = ARRAY_SIZE(ti_eqep_counts);
  323. priv->counter.signals = ti_eqep_signals;
  324. priv->counter.num_signals = ARRAY_SIZE(ti_eqep_signals);
  325. priv->counter.priv = priv;
  326. platform_set_drvdata(pdev, priv);
  327. /*
  328. * Need to make sure power is turned on. On AM33xx, this comes from the
  329. * parent PWMSS bus driver. On AM17xx, this comes from the PSC power
  330. * domain.
  331. */
  332. pm_runtime_enable(dev);
  333. pm_runtime_get_sync(dev);
  334. err = counter_register(&priv->counter);
  335. if (err < 0) {
  336. pm_runtime_put_sync(dev);
  337. pm_runtime_disable(dev);
  338. return err;
  339. }
  340. return 0;
  341. }
  342. static int ti_eqep_remove(struct platform_device *pdev)
  343. {
  344. struct ti_eqep_cnt *priv = platform_get_drvdata(pdev);
  345. struct device *dev = &pdev->dev;
  346. counter_unregister(&priv->counter);
  347. pm_runtime_put_sync(dev);
  348. pm_runtime_disable(dev);
  349. return 0;
  350. }
  351. static const struct of_device_id ti_eqep_of_match[] = {
  352. { .compatible = "ti,am3352-eqep", },
  353. { },
  354. };
  355. MODULE_DEVICE_TABLE(of, ti_eqep_of_match);
  356. static struct platform_driver ti_eqep_driver = {
  357. .probe = ti_eqep_probe,
  358. .remove = ti_eqep_remove,
  359. .driver = {
  360. .name = "ti-eqep-cnt",
  361. .of_match_table = ti_eqep_of_match,
  362. },
  363. };
  364. module_platform_driver(ti_eqep_driver);
  365. MODULE_AUTHOR("David Lechner <david@lechnology.com>");
  366. MODULE_DESCRIPTION("TI eQEP counter driver");
  367. MODULE_LICENSE("GPL v2");