104-quad-8.c 44 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Counter driver for the ACCES 104-QUAD-8
  4. * Copyright (C) 2016 William Breathitt Gray
  5. *
  6. * This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/counter.h>
  10. #include <linux/device.h>
  11. #include <linux/errno.h>
  12. #include <linux/iio/iio.h>
  13. #include <linux/iio/types.h>
  14. #include <linux/io.h>
  15. #include <linux/ioport.h>
  16. #include <linux/isa.h>
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/moduleparam.h>
  20. #include <linux/types.h>
  21. #define QUAD8_EXTENT 32
  22. static unsigned int base[max_num_isa_dev(QUAD8_EXTENT)];
  23. static unsigned int num_quad8;
  24. module_param_array(base, uint, &num_quad8, 0);
  25. MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
  26. #define QUAD8_NUM_COUNTERS 8
  27. /**
  28. * struct quad8_iio - IIO device private data structure
  29. * @counter: instance of the counter_device
  30. * @fck_prescaler: array of filter clock prescaler configurations
  31. * @preset: array of preset values
  32. * @count_mode: array of count mode configurations
  33. * @quadrature_mode: array of quadrature mode configurations
  34. * @quadrature_scale: array of quadrature mode scale configurations
  35. * @ab_enable: array of A and B inputs enable configurations
  36. * @preset_enable: array of set_to_preset_on_index attribute configurations
  37. * @synchronous_mode: array of index function synchronous mode configurations
  38. * @index_polarity: array of index function polarity configurations
  39. * @cable_fault_enable: differential encoder cable status enable configurations
  40. * @base: base port address of the IIO device
  41. */
  42. struct quad8_iio {
  43. struct mutex lock;
  44. struct counter_device counter;
  45. unsigned int fck_prescaler[QUAD8_NUM_COUNTERS];
  46. unsigned int preset[QUAD8_NUM_COUNTERS];
  47. unsigned int count_mode[QUAD8_NUM_COUNTERS];
  48. unsigned int quadrature_mode[QUAD8_NUM_COUNTERS];
  49. unsigned int quadrature_scale[QUAD8_NUM_COUNTERS];
  50. unsigned int ab_enable[QUAD8_NUM_COUNTERS];
  51. unsigned int preset_enable[QUAD8_NUM_COUNTERS];
  52. unsigned int synchronous_mode[QUAD8_NUM_COUNTERS];
  53. unsigned int index_polarity[QUAD8_NUM_COUNTERS];
  54. unsigned int cable_fault_enable;
  55. unsigned int base;
  56. };
  57. #define QUAD8_REG_CHAN_OP 0x11
  58. #define QUAD8_REG_INDEX_INPUT_LEVELS 0x16
  59. #define QUAD8_DIFF_ENCODER_CABLE_STATUS 0x17
  60. /* Borrow Toggle flip-flop */
  61. #define QUAD8_FLAG_BT BIT(0)
  62. /* Carry Toggle flip-flop */
  63. #define QUAD8_FLAG_CT BIT(1)
  64. /* Error flag */
  65. #define QUAD8_FLAG_E BIT(4)
  66. /* Up/Down flag */
  67. #define QUAD8_FLAG_UD BIT(5)
  68. /* Reset and Load Signal Decoders */
  69. #define QUAD8_CTR_RLD 0x00
  70. /* Counter Mode Register */
  71. #define QUAD8_CTR_CMR 0x20
  72. /* Input / Output Control Register */
  73. #define QUAD8_CTR_IOR 0x40
  74. /* Index Control Register */
  75. #define QUAD8_CTR_IDR 0x60
  76. /* Reset Byte Pointer (three byte data pointer) */
  77. #define QUAD8_RLD_RESET_BP 0x01
  78. /* Reset Counter */
  79. #define QUAD8_RLD_RESET_CNTR 0x02
  80. /* Reset Borrow Toggle, Carry Toggle, Compare Toggle, and Sign flags */
  81. #define QUAD8_RLD_RESET_FLAGS 0x04
  82. /* Reset Error flag */
  83. #define QUAD8_RLD_RESET_E 0x06
  84. /* Preset Register to Counter */
  85. #define QUAD8_RLD_PRESET_CNTR 0x08
  86. /* Transfer Counter to Output Latch */
  87. #define QUAD8_RLD_CNTR_OUT 0x10
  88. /* Transfer Preset Register LSB to FCK Prescaler */
  89. #define QUAD8_RLD_PRESET_PSC 0x18
  90. #define QUAD8_CHAN_OP_ENABLE_COUNTERS 0x00
  91. #define QUAD8_CHAN_OP_RESET_COUNTERS 0x01
  92. #define QUAD8_CMR_QUADRATURE_X1 0x08
  93. #define QUAD8_CMR_QUADRATURE_X2 0x10
  94. #define QUAD8_CMR_QUADRATURE_X4 0x18
  95. static int quad8_read_raw(struct iio_dev *indio_dev,
  96. struct iio_chan_spec const *chan, int *val, int *val2, long mask)
  97. {
  98. struct quad8_iio *const priv = iio_priv(indio_dev);
  99. const int base_offset = priv->base + 2 * chan->channel;
  100. unsigned int flags;
  101. unsigned int borrow;
  102. unsigned int carry;
  103. int i;
  104. switch (mask) {
  105. case IIO_CHAN_INFO_RAW:
  106. if (chan->type == IIO_INDEX) {
  107. *val = !!(inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS)
  108. & BIT(chan->channel));
  109. return IIO_VAL_INT;
  110. }
  111. flags = inb(base_offset + 1);
  112. borrow = flags & QUAD8_FLAG_BT;
  113. carry = !!(flags & QUAD8_FLAG_CT);
  114. /* Borrow XOR Carry effectively doubles count range */
  115. *val = (borrow ^ carry) << 24;
  116. mutex_lock(&priv->lock);
  117. /* Reset Byte Pointer; transfer Counter to Output Latch */
  118. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
  119. base_offset + 1);
  120. for (i = 0; i < 3; i++)
  121. *val |= (unsigned int)inb(base_offset) << (8 * i);
  122. mutex_unlock(&priv->lock);
  123. return IIO_VAL_INT;
  124. case IIO_CHAN_INFO_ENABLE:
  125. *val = priv->ab_enable[chan->channel];
  126. return IIO_VAL_INT;
  127. case IIO_CHAN_INFO_SCALE:
  128. *val = 1;
  129. *val2 = priv->quadrature_scale[chan->channel];
  130. return IIO_VAL_FRACTIONAL_LOG2;
  131. }
  132. return -EINVAL;
  133. }
  134. static int quad8_write_raw(struct iio_dev *indio_dev,
  135. struct iio_chan_spec const *chan, int val, int val2, long mask)
  136. {
  137. struct quad8_iio *const priv = iio_priv(indio_dev);
  138. const int base_offset = priv->base + 2 * chan->channel;
  139. int i;
  140. unsigned int ior_cfg;
  141. switch (mask) {
  142. case IIO_CHAN_INFO_RAW:
  143. if (chan->type == IIO_INDEX)
  144. return -EINVAL;
  145. /* Only 24-bit values are supported */
  146. if ((unsigned int)val > 0xFFFFFF)
  147. return -EINVAL;
  148. mutex_lock(&priv->lock);
  149. /* Reset Byte Pointer */
  150. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
  151. /* Counter can only be set via Preset Register */
  152. for (i = 0; i < 3; i++)
  153. outb(val >> (8 * i), base_offset);
  154. /* Transfer Preset Register to Counter */
  155. outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1);
  156. /* Reset Byte Pointer */
  157. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
  158. /* Set Preset Register back to original value */
  159. val = priv->preset[chan->channel];
  160. for (i = 0; i < 3; i++)
  161. outb(val >> (8 * i), base_offset);
  162. /* Reset Borrow, Carry, Compare, and Sign flags */
  163. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
  164. /* Reset Error flag */
  165. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
  166. mutex_unlock(&priv->lock);
  167. return 0;
  168. case IIO_CHAN_INFO_ENABLE:
  169. /* only boolean values accepted */
  170. if (val < 0 || val > 1)
  171. return -EINVAL;
  172. mutex_lock(&priv->lock);
  173. priv->ab_enable[chan->channel] = val;
  174. ior_cfg = val | priv->preset_enable[chan->channel] << 1;
  175. /* Load I/O control configuration */
  176. outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
  177. mutex_unlock(&priv->lock);
  178. return 0;
  179. case IIO_CHAN_INFO_SCALE:
  180. mutex_lock(&priv->lock);
  181. /* Quadrature scaling only available in quadrature mode */
  182. if (!priv->quadrature_mode[chan->channel] &&
  183. (val2 || val != 1)) {
  184. mutex_unlock(&priv->lock);
  185. return -EINVAL;
  186. }
  187. /* Only three gain states (1, 0.5, 0.25) */
  188. if (val == 1 && !val2)
  189. priv->quadrature_scale[chan->channel] = 0;
  190. else if (!val)
  191. switch (val2) {
  192. case 500000:
  193. priv->quadrature_scale[chan->channel] = 1;
  194. break;
  195. case 250000:
  196. priv->quadrature_scale[chan->channel] = 2;
  197. break;
  198. default:
  199. mutex_unlock(&priv->lock);
  200. return -EINVAL;
  201. }
  202. else {
  203. mutex_unlock(&priv->lock);
  204. return -EINVAL;
  205. }
  206. mutex_unlock(&priv->lock);
  207. return 0;
  208. }
  209. return -EINVAL;
  210. }
  211. static const struct iio_info quad8_info = {
  212. .read_raw = quad8_read_raw,
  213. .write_raw = quad8_write_raw
  214. };
  215. static ssize_t quad8_read_preset(struct iio_dev *indio_dev, uintptr_t private,
  216. const struct iio_chan_spec *chan, char *buf)
  217. {
  218. const struct quad8_iio *const priv = iio_priv(indio_dev);
  219. return snprintf(buf, PAGE_SIZE, "%u\n", priv->preset[chan->channel]);
  220. }
  221. static ssize_t quad8_write_preset(struct iio_dev *indio_dev, uintptr_t private,
  222. const struct iio_chan_spec *chan, const char *buf, size_t len)
  223. {
  224. struct quad8_iio *const priv = iio_priv(indio_dev);
  225. const int base_offset = priv->base + 2 * chan->channel;
  226. unsigned int preset;
  227. int ret;
  228. int i;
  229. ret = kstrtouint(buf, 0, &preset);
  230. if (ret)
  231. return ret;
  232. /* Only 24-bit values are supported */
  233. if (preset > 0xFFFFFF)
  234. return -EINVAL;
  235. mutex_lock(&priv->lock);
  236. priv->preset[chan->channel] = preset;
  237. /* Reset Byte Pointer */
  238. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
  239. /* Set Preset Register */
  240. for (i = 0; i < 3; i++)
  241. outb(preset >> (8 * i), base_offset);
  242. mutex_unlock(&priv->lock);
  243. return len;
  244. }
  245. static ssize_t quad8_read_set_to_preset_on_index(struct iio_dev *indio_dev,
  246. uintptr_t private, const struct iio_chan_spec *chan, char *buf)
  247. {
  248. const struct quad8_iio *const priv = iio_priv(indio_dev);
  249. return snprintf(buf, PAGE_SIZE, "%u\n",
  250. !priv->preset_enable[chan->channel]);
  251. }
  252. static ssize_t quad8_write_set_to_preset_on_index(struct iio_dev *indio_dev,
  253. uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
  254. size_t len)
  255. {
  256. struct quad8_iio *const priv = iio_priv(indio_dev);
  257. const int base_offset = priv->base + 2 * chan->channel + 1;
  258. bool preset_enable;
  259. int ret;
  260. unsigned int ior_cfg;
  261. ret = kstrtobool(buf, &preset_enable);
  262. if (ret)
  263. return ret;
  264. /* Preset enable is active low in Input/Output Control register */
  265. preset_enable = !preset_enable;
  266. mutex_lock(&priv->lock);
  267. priv->preset_enable[chan->channel] = preset_enable;
  268. ior_cfg = priv->ab_enable[chan->channel] |
  269. (unsigned int)preset_enable << 1;
  270. /* Load I/O control configuration to Input / Output Control Register */
  271. outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
  272. mutex_unlock(&priv->lock);
  273. return len;
  274. }
  275. static const char *const quad8_noise_error_states[] = {
  276. "No excessive noise is present at the count inputs",
  277. "Excessive noise is present at the count inputs"
  278. };
  279. static int quad8_get_noise_error(struct iio_dev *indio_dev,
  280. const struct iio_chan_spec *chan)
  281. {
  282. struct quad8_iio *const priv = iio_priv(indio_dev);
  283. const int base_offset = priv->base + 2 * chan->channel + 1;
  284. return !!(inb(base_offset) & QUAD8_FLAG_E);
  285. }
  286. static const struct iio_enum quad8_noise_error_enum = {
  287. .items = quad8_noise_error_states,
  288. .num_items = ARRAY_SIZE(quad8_noise_error_states),
  289. .get = quad8_get_noise_error
  290. };
  291. static const char *const quad8_count_direction_states[] = {
  292. "down",
  293. "up"
  294. };
  295. static int quad8_get_count_direction(struct iio_dev *indio_dev,
  296. const struct iio_chan_spec *chan)
  297. {
  298. struct quad8_iio *const priv = iio_priv(indio_dev);
  299. const int base_offset = priv->base + 2 * chan->channel + 1;
  300. return !!(inb(base_offset) & QUAD8_FLAG_UD);
  301. }
  302. static const struct iio_enum quad8_count_direction_enum = {
  303. .items = quad8_count_direction_states,
  304. .num_items = ARRAY_SIZE(quad8_count_direction_states),
  305. .get = quad8_get_count_direction
  306. };
  307. static const char *const quad8_count_modes[] = {
  308. "normal",
  309. "range limit",
  310. "non-recycle",
  311. "modulo-n"
  312. };
  313. static int quad8_set_count_mode(struct iio_dev *indio_dev,
  314. const struct iio_chan_spec *chan, unsigned int cnt_mode)
  315. {
  316. struct quad8_iio *const priv = iio_priv(indio_dev);
  317. unsigned int mode_cfg = cnt_mode << 1;
  318. const int base_offset = priv->base + 2 * chan->channel + 1;
  319. mutex_lock(&priv->lock);
  320. priv->count_mode[chan->channel] = cnt_mode;
  321. /* Add quadrature mode configuration */
  322. if (priv->quadrature_mode[chan->channel])
  323. mode_cfg |= (priv->quadrature_scale[chan->channel] + 1) << 3;
  324. /* Load mode configuration to Counter Mode Register */
  325. outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
  326. mutex_unlock(&priv->lock);
  327. return 0;
  328. }
  329. static int quad8_get_count_mode(struct iio_dev *indio_dev,
  330. const struct iio_chan_spec *chan)
  331. {
  332. const struct quad8_iio *const priv = iio_priv(indio_dev);
  333. return priv->count_mode[chan->channel];
  334. }
  335. static const struct iio_enum quad8_count_mode_enum = {
  336. .items = quad8_count_modes,
  337. .num_items = ARRAY_SIZE(quad8_count_modes),
  338. .set = quad8_set_count_mode,
  339. .get = quad8_get_count_mode
  340. };
  341. static const char *const quad8_synchronous_modes[] = {
  342. "non-synchronous",
  343. "synchronous"
  344. };
  345. static int quad8_set_synchronous_mode(struct iio_dev *indio_dev,
  346. const struct iio_chan_spec *chan, unsigned int synchronous_mode)
  347. {
  348. struct quad8_iio *const priv = iio_priv(indio_dev);
  349. const int base_offset = priv->base + 2 * chan->channel + 1;
  350. unsigned int idr_cfg = synchronous_mode;
  351. mutex_lock(&priv->lock);
  352. idr_cfg |= priv->index_polarity[chan->channel] << 1;
  353. /* Index function must be non-synchronous in non-quadrature mode */
  354. if (synchronous_mode && !priv->quadrature_mode[chan->channel]) {
  355. mutex_unlock(&priv->lock);
  356. return -EINVAL;
  357. }
  358. priv->synchronous_mode[chan->channel] = synchronous_mode;
  359. /* Load Index Control configuration to Index Control Register */
  360. outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
  361. mutex_unlock(&priv->lock);
  362. return 0;
  363. }
  364. static int quad8_get_synchronous_mode(struct iio_dev *indio_dev,
  365. const struct iio_chan_spec *chan)
  366. {
  367. const struct quad8_iio *const priv = iio_priv(indio_dev);
  368. return priv->synchronous_mode[chan->channel];
  369. }
  370. static const struct iio_enum quad8_synchronous_mode_enum = {
  371. .items = quad8_synchronous_modes,
  372. .num_items = ARRAY_SIZE(quad8_synchronous_modes),
  373. .set = quad8_set_synchronous_mode,
  374. .get = quad8_get_synchronous_mode
  375. };
  376. static const char *const quad8_quadrature_modes[] = {
  377. "non-quadrature",
  378. "quadrature"
  379. };
  380. static int quad8_set_quadrature_mode(struct iio_dev *indio_dev,
  381. const struct iio_chan_spec *chan, unsigned int quadrature_mode)
  382. {
  383. struct quad8_iio *const priv = iio_priv(indio_dev);
  384. const int base_offset = priv->base + 2 * chan->channel + 1;
  385. unsigned int mode_cfg;
  386. mutex_lock(&priv->lock);
  387. mode_cfg = priv->count_mode[chan->channel] << 1;
  388. if (quadrature_mode)
  389. mode_cfg |= (priv->quadrature_scale[chan->channel] + 1) << 3;
  390. else {
  391. /* Quadrature scaling only available in quadrature mode */
  392. priv->quadrature_scale[chan->channel] = 0;
  393. /* Synchronous function not supported in non-quadrature mode */
  394. if (priv->synchronous_mode[chan->channel])
  395. quad8_set_synchronous_mode(indio_dev, chan, 0);
  396. }
  397. priv->quadrature_mode[chan->channel] = quadrature_mode;
  398. /* Load mode configuration to Counter Mode Register */
  399. outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
  400. mutex_unlock(&priv->lock);
  401. return 0;
  402. }
  403. static int quad8_get_quadrature_mode(struct iio_dev *indio_dev,
  404. const struct iio_chan_spec *chan)
  405. {
  406. const struct quad8_iio *const priv = iio_priv(indio_dev);
  407. return priv->quadrature_mode[chan->channel];
  408. }
  409. static const struct iio_enum quad8_quadrature_mode_enum = {
  410. .items = quad8_quadrature_modes,
  411. .num_items = ARRAY_SIZE(quad8_quadrature_modes),
  412. .set = quad8_set_quadrature_mode,
  413. .get = quad8_get_quadrature_mode
  414. };
  415. static const char *const quad8_index_polarity_modes[] = {
  416. "negative",
  417. "positive"
  418. };
  419. static int quad8_set_index_polarity(struct iio_dev *indio_dev,
  420. const struct iio_chan_spec *chan, unsigned int index_polarity)
  421. {
  422. struct quad8_iio *const priv = iio_priv(indio_dev);
  423. const int base_offset = priv->base + 2 * chan->channel + 1;
  424. unsigned int idr_cfg = index_polarity << 1;
  425. mutex_lock(&priv->lock);
  426. idr_cfg |= priv->synchronous_mode[chan->channel];
  427. priv->index_polarity[chan->channel] = index_polarity;
  428. /* Load Index Control configuration to Index Control Register */
  429. outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
  430. mutex_unlock(&priv->lock);
  431. return 0;
  432. }
  433. static int quad8_get_index_polarity(struct iio_dev *indio_dev,
  434. const struct iio_chan_spec *chan)
  435. {
  436. const struct quad8_iio *const priv = iio_priv(indio_dev);
  437. return priv->index_polarity[chan->channel];
  438. }
  439. static const struct iio_enum quad8_index_polarity_enum = {
  440. .items = quad8_index_polarity_modes,
  441. .num_items = ARRAY_SIZE(quad8_index_polarity_modes),
  442. .set = quad8_set_index_polarity,
  443. .get = quad8_get_index_polarity
  444. };
  445. static const struct iio_chan_spec_ext_info quad8_count_ext_info[] = {
  446. {
  447. .name = "preset",
  448. .shared = IIO_SEPARATE,
  449. .read = quad8_read_preset,
  450. .write = quad8_write_preset
  451. },
  452. {
  453. .name = "set_to_preset_on_index",
  454. .shared = IIO_SEPARATE,
  455. .read = quad8_read_set_to_preset_on_index,
  456. .write = quad8_write_set_to_preset_on_index
  457. },
  458. IIO_ENUM("noise_error", IIO_SEPARATE, &quad8_noise_error_enum),
  459. IIO_ENUM_AVAILABLE("noise_error", &quad8_noise_error_enum),
  460. IIO_ENUM("count_direction", IIO_SEPARATE, &quad8_count_direction_enum),
  461. IIO_ENUM_AVAILABLE("count_direction", &quad8_count_direction_enum),
  462. IIO_ENUM("count_mode", IIO_SEPARATE, &quad8_count_mode_enum),
  463. IIO_ENUM_AVAILABLE("count_mode", &quad8_count_mode_enum),
  464. IIO_ENUM("quadrature_mode", IIO_SEPARATE, &quad8_quadrature_mode_enum),
  465. IIO_ENUM_AVAILABLE("quadrature_mode", &quad8_quadrature_mode_enum),
  466. {}
  467. };
  468. static const struct iio_chan_spec_ext_info quad8_index_ext_info[] = {
  469. IIO_ENUM("synchronous_mode", IIO_SEPARATE,
  470. &quad8_synchronous_mode_enum),
  471. IIO_ENUM_AVAILABLE("synchronous_mode", &quad8_synchronous_mode_enum),
  472. IIO_ENUM("index_polarity", IIO_SEPARATE, &quad8_index_polarity_enum),
  473. IIO_ENUM_AVAILABLE("index_polarity", &quad8_index_polarity_enum),
  474. {}
  475. };
  476. #define QUAD8_COUNT_CHAN(_chan) { \
  477. .type = IIO_COUNT, \
  478. .channel = (_chan), \
  479. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  480. BIT(IIO_CHAN_INFO_ENABLE) | BIT(IIO_CHAN_INFO_SCALE), \
  481. .ext_info = quad8_count_ext_info, \
  482. .indexed = 1 \
  483. }
  484. #define QUAD8_INDEX_CHAN(_chan) { \
  485. .type = IIO_INDEX, \
  486. .channel = (_chan), \
  487. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  488. .ext_info = quad8_index_ext_info, \
  489. .indexed = 1 \
  490. }
  491. static const struct iio_chan_spec quad8_channels[] = {
  492. QUAD8_COUNT_CHAN(0), QUAD8_INDEX_CHAN(0),
  493. QUAD8_COUNT_CHAN(1), QUAD8_INDEX_CHAN(1),
  494. QUAD8_COUNT_CHAN(2), QUAD8_INDEX_CHAN(2),
  495. QUAD8_COUNT_CHAN(3), QUAD8_INDEX_CHAN(3),
  496. QUAD8_COUNT_CHAN(4), QUAD8_INDEX_CHAN(4),
  497. QUAD8_COUNT_CHAN(5), QUAD8_INDEX_CHAN(5),
  498. QUAD8_COUNT_CHAN(6), QUAD8_INDEX_CHAN(6),
  499. QUAD8_COUNT_CHAN(7), QUAD8_INDEX_CHAN(7)
  500. };
  501. static int quad8_signal_read(struct counter_device *counter,
  502. struct counter_signal *signal, enum counter_signal_value *val)
  503. {
  504. const struct quad8_iio *const priv = counter->priv;
  505. unsigned int state;
  506. /* Only Index signal levels can be read */
  507. if (signal->id < 16)
  508. return -EINVAL;
  509. state = inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS)
  510. & BIT(signal->id - 16);
  511. *val = (state) ? COUNTER_SIGNAL_HIGH : COUNTER_SIGNAL_LOW;
  512. return 0;
  513. }
  514. static int quad8_count_read(struct counter_device *counter,
  515. struct counter_count *count, unsigned long *val)
  516. {
  517. struct quad8_iio *const priv = counter->priv;
  518. const int base_offset = priv->base + 2 * count->id;
  519. unsigned int flags;
  520. unsigned int borrow;
  521. unsigned int carry;
  522. int i;
  523. flags = inb(base_offset + 1);
  524. borrow = flags & QUAD8_FLAG_BT;
  525. carry = !!(flags & QUAD8_FLAG_CT);
  526. /* Borrow XOR Carry effectively doubles count range */
  527. *val = (unsigned long)(borrow ^ carry) << 24;
  528. mutex_lock(&priv->lock);
  529. /* Reset Byte Pointer; transfer Counter to Output Latch */
  530. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
  531. base_offset + 1);
  532. for (i = 0; i < 3; i++)
  533. *val |= (unsigned long)inb(base_offset) << (8 * i);
  534. mutex_unlock(&priv->lock);
  535. return 0;
  536. }
  537. static int quad8_count_write(struct counter_device *counter,
  538. struct counter_count *count, unsigned long val)
  539. {
  540. struct quad8_iio *const priv = counter->priv;
  541. const int base_offset = priv->base + 2 * count->id;
  542. int i;
  543. /* Only 24-bit values are supported */
  544. if (val > 0xFFFFFF)
  545. return -EINVAL;
  546. mutex_lock(&priv->lock);
  547. /* Reset Byte Pointer */
  548. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
  549. /* Counter can only be set via Preset Register */
  550. for (i = 0; i < 3; i++)
  551. outb(val >> (8 * i), base_offset);
  552. /* Transfer Preset Register to Counter */
  553. outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1);
  554. /* Reset Byte Pointer */
  555. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
  556. /* Set Preset Register back to original value */
  557. val = priv->preset[count->id];
  558. for (i = 0; i < 3; i++)
  559. outb(val >> (8 * i), base_offset);
  560. /* Reset Borrow, Carry, Compare, and Sign flags */
  561. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
  562. /* Reset Error flag */
  563. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
  564. mutex_unlock(&priv->lock);
  565. return 0;
  566. }
  567. enum quad8_count_function {
  568. QUAD8_COUNT_FUNCTION_PULSE_DIRECTION = 0,
  569. QUAD8_COUNT_FUNCTION_QUADRATURE_X1,
  570. QUAD8_COUNT_FUNCTION_QUADRATURE_X2,
  571. QUAD8_COUNT_FUNCTION_QUADRATURE_X4
  572. };
  573. static enum counter_count_function quad8_count_functions_list[] = {
  574. [QUAD8_COUNT_FUNCTION_PULSE_DIRECTION] = COUNTER_COUNT_FUNCTION_PULSE_DIRECTION,
  575. [QUAD8_COUNT_FUNCTION_QUADRATURE_X1] = COUNTER_COUNT_FUNCTION_QUADRATURE_X1_A,
  576. [QUAD8_COUNT_FUNCTION_QUADRATURE_X2] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_A,
  577. [QUAD8_COUNT_FUNCTION_QUADRATURE_X4] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4
  578. };
  579. static int quad8_function_get(struct counter_device *counter,
  580. struct counter_count *count, size_t *function)
  581. {
  582. struct quad8_iio *const priv = counter->priv;
  583. const int id = count->id;
  584. mutex_lock(&priv->lock);
  585. if (priv->quadrature_mode[id])
  586. switch (priv->quadrature_scale[id]) {
  587. case 0:
  588. *function = QUAD8_COUNT_FUNCTION_QUADRATURE_X1;
  589. break;
  590. case 1:
  591. *function = QUAD8_COUNT_FUNCTION_QUADRATURE_X2;
  592. break;
  593. case 2:
  594. *function = QUAD8_COUNT_FUNCTION_QUADRATURE_X4;
  595. break;
  596. }
  597. else
  598. *function = QUAD8_COUNT_FUNCTION_PULSE_DIRECTION;
  599. mutex_unlock(&priv->lock);
  600. return 0;
  601. }
  602. static int quad8_function_set(struct counter_device *counter,
  603. struct counter_count *count, size_t function)
  604. {
  605. struct quad8_iio *const priv = counter->priv;
  606. const int id = count->id;
  607. unsigned int *const quadrature_mode = priv->quadrature_mode + id;
  608. unsigned int *const scale = priv->quadrature_scale + id;
  609. unsigned int *const synchronous_mode = priv->synchronous_mode + id;
  610. const int base_offset = priv->base + 2 * id + 1;
  611. unsigned int mode_cfg;
  612. unsigned int idr_cfg;
  613. mutex_lock(&priv->lock);
  614. mode_cfg = priv->count_mode[id] << 1;
  615. idr_cfg = priv->index_polarity[id] << 1;
  616. if (function == QUAD8_COUNT_FUNCTION_PULSE_DIRECTION) {
  617. *quadrature_mode = 0;
  618. /* Quadrature scaling only available in quadrature mode */
  619. *scale = 0;
  620. /* Synchronous function not supported in non-quadrature mode */
  621. if (*synchronous_mode) {
  622. *synchronous_mode = 0;
  623. /* Disable synchronous function mode */
  624. outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
  625. }
  626. } else {
  627. *quadrature_mode = 1;
  628. switch (function) {
  629. case QUAD8_COUNT_FUNCTION_QUADRATURE_X1:
  630. *scale = 0;
  631. mode_cfg |= QUAD8_CMR_QUADRATURE_X1;
  632. break;
  633. case QUAD8_COUNT_FUNCTION_QUADRATURE_X2:
  634. *scale = 1;
  635. mode_cfg |= QUAD8_CMR_QUADRATURE_X2;
  636. break;
  637. case QUAD8_COUNT_FUNCTION_QUADRATURE_X4:
  638. *scale = 2;
  639. mode_cfg |= QUAD8_CMR_QUADRATURE_X4;
  640. break;
  641. }
  642. }
  643. /* Load mode configuration to Counter Mode Register */
  644. outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
  645. mutex_unlock(&priv->lock);
  646. return 0;
  647. }
  648. static void quad8_direction_get(struct counter_device *counter,
  649. struct counter_count *count, enum counter_count_direction *direction)
  650. {
  651. const struct quad8_iio *const priv = counter->priv;
  652. unsigned int ud_flag;
  653. const unsigned int flag_addr = priv->base + 2 * count->id + 1;
  654. /* U/D flag: nonzero = up, zero = down */
  655. ud_flag = inb(flag_addr) & QUAD8_FLAG_UD;
  656. *direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD :
  657. COUNTER_COUNT_DIRECTION_BACKWARD;
  658. }
  659. enum quad8_synapse_action {
  660. QUAD8_SYNAPSE_ACTION_NONE = 0,
  661. QUAD8_SYNAPSE_ACTION_RISING_EDGE,
  662. QUAD8_SYNAPSE_ACTION_FALLING_EDGE,
  663. QUAD8_SYNAPSE_ACTION_BOTH_EDGES
  664. };
  665. static enum counter_synapse_action quad8_index_actions_list[] = {
  666. [QUAD8_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
  667. [QUAD8_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE
  668. };
  669. static enum counter_synapse_action quad8_synapse_actions_list[] = {
  670. [QUAD8_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
  671. [QUAD8_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
  672. [QUAD8_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
  673. [QUAD8_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES
  674. };
  675. static int quad8_action_get(struct counter_device *counter,
  676. struct counter_count *count, struct counter_synapse *synapse,
  677. size_t *action)
  678. {
  679. struct quad8_iio *const priv = counter->priv;
  680. int err;
  681. size_t function = 0;
  682. const size_t signal_a_id = count->synapses[0].signal->id;
  683. enum counter_count_direction direction;
  684. /* Handle Index signals */
  685. if (synapse->signal->id >= 16) {
  686. if (priv->preset_enable[count->id])
  687. *action = QUAD8_SYNAPSE_ACTION_RISING_EDGE;
  688. else
  689. *action = QUAD8_SYNAPSE_ACTION_NONE;
  690. return 0;
  691. }
  692. err = quad8_function_get(counter, count, &function);
  693. if (err)
  694. return err;
  695. /* Default action mode */
  696. *action = QUAD8_SYNAPSE_ACTION_NONE;
  697. /* Determine action mode based on current count function mode */
  698. switch (function) {
  699. case QUAD8_COUNT_FUNCTION_PULSE_DIRECTION:
  700. if (synapse->signal->id == signal_a_id)
  701. *action = QUAD8_SYNAPSE_ACTION_RISING_EDGE;
  702. break;
  703. case QUAD8_COUNT_FUNCTION_QUADRATURE_X1:
  704. if (synapse->signal->id == signal_a_id) {
  705. quad8_direction_get(counter, count, &direction);
  706. if (direction == COUNTER_COUNT_DIRECTION_FORWARD)
  707. *action = QUAD8_SYNAPSE_ACTION_RISING_EDGE;
  708. else
  709. *action = QUAD8_SYNAPSE_ACTION_FALLING_EDGE;
  710. }
  711. break;
  712. case QUAD8_COUNT_FUNCTION_QUADRATURE_X2:
  713. if (synapse->signal->id == signal_a_id)
  714. *action = QUAD8_SYNAPSE_ACTION_BOTH_EDGES;
  715. break;
  716. case QUAD8_COUNT_FUNCTION_QUADRATURE_X4:
  717. *action = QUAD8_SYNAPSE_ACTION_BOTH_EDGES;
  718. break;
  719. }
  720. return 0;
  721. }
  722. static const struct counter_ops quad8_ops = {
  723. .signal_read = quad8_signal_read,
  724. .count_read = quad8_count_read,
  725. .count_write = quad8_count_write,
  726. .function_get = quad8_function_get,
  727. .function_set = quad8_function_set,
  728. .action_get = quad8_action_get
  729. };
  730. static int quad8_index_polarity_get(struct counter_device *counter,
  731. struct counter_signal *signal, size_t *index_polarity)
  732. {
  733. const struct quad8_iio *const priv = counter->priv;
  734. const size_t channel_id = signal->id - 16;
  735. *index_polarity = priv->index_polarity[channel_id];
  736. return 0;
  737. }
  738. static int quad8_index_polarity_set(struct counter_device *counter,
  739. struct counter_signal *signal, size_t index_polarity)
  740. {
  741. struct quad8_iio *const priv = counter->priv;
  742. const size_t channel_id = signal->id - 16;
  743. const int base_offset = priv->base + 2 * channel_id + 1;
  744. unsigned int idr_cfg = index_polarity << 1;
  745. mutex_lock(&priv->lock);
  746. idr_cfg |= priv->synchronous_mode[channel_id];
  747. priv->index_polarity[channel_id] = index_polarity;
  748. /* Load Index Control configuration to Index Control Register */
  749. outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
  750. mutex_unlock(&priv->lock);
  751. return 0;
  752. }
  753. static struct counter_signal_enum_ext quad8_index_pol_enum = {
  754. .items = quad8_index_polarity_modes,
  755. .num_items = ARRAY_SIZE(quad8_index_polarity_modes),
  756. .get = quad8_index_polarity_get,
  757. .set = quad8_index_polarity_set
  758. };
  759. static int quad8_synchronous_mode_get(struct counter_device *counter,
  760. struct counter_signal *signal, size_t *synchronous_mode)
  761. {
  762. const struct quad8_iio *const priv = counter->priv;
  763. const size_t channel_id = signal->id - 16;
  764. *synchronous_mode = priv->synchronous_mode[channel_id];
  765. return 0;
  766. }
  767. static int quad8_synchronous_mode_set(struct counter_device *counter,
  768. struct counter_signal *signal, size_t synchronous_mode)
  769. {
  770. struct quad8_iio *const priv = counter->priv;
  771. const size_t channel_id = signal->id - 16;
  772. const int base_offset = priv->base + 2 * channel_id + 1;
  773. unsigned int idr_cfg = synchronous_mode;
  774. mutex_lock(&priv->lock);
  775. idr_cfg |= priv->index_polarity[channel_id] << 1;
  776. /* Index function must be non-synchronous in non-quadrature mode */
  777. if (synchronous_mode && !priv->quadrature_mode[channel_id]) {
  778. mutex_unlock(&priv->lock);
  779. return -EINVAL;
  780. }
  781. priv->synchronous_mode[channel_id] = synchronous_mode;
  782. /* Load Index Control configuration to Index Control Register */
  783. outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
  784. mutex_unlock(&priv->lock);
  785. return 0;
  786. }
  787. static struct counter_signal_enum_ext quad8_syn_mode_enum = {
  788. .items = quad8_synchronous_modes,
  789. .num_items = ARRAY_SIZE(quad8_synchronous_modes),
  790. .get = quad8_synchronous_mode_get,
  791. .set = quad8_synchronous_mode_set
  792. };
  793. static ssize_t quad8_count_floor_read(struct counter_device *counter,
  794. struct counter_count *count, void *private, char *buf)
  795. {
  796. /* Only a floor of 0 is supported */
  797. return sprintf(buf, "0\n");
  798. }
  799. static int quad8_count_mode_get(struct counter_device *counter,
  800. struct counter_count *count, size_t *cnt_mode)
  801. {
  802. const struct quad8_iio *const priv = counter->priv;
  803. /* Map 104-QUAD-8 count mode to Generic Counter count mode */
  804. switch (priv->count_mode[count->id]) {
  805. case 0:
  806. *cnt_mode = COUNTER_COUNT_MODE_NORMAL;
  807. break;
  808. case 1:
  809. *cnt_mode = COUNTER_COUNT_MODE_RANGE_LIMIT;
  810. break;
  811. case 2:
  812. *cnt_mode = COUNTER_COUNT_MODE_NON_RECYCLE;
  813. break;
  814. case 3:
  815. *cnt_mode = COUNTER_COUNT_MODE_MODULO_N;
  816. break;
  817. }
  818. return 0;
  819. }
  820. static int quad8_count_mode_set(struct counter_device *counter,
  821. struct counter_count *count, size_t cnt_mode)
  822. {
  823. struct quad8_iio *const priv = counter->priv;
  824. unsigned int mode_cfg;
  825. const int base_offset = priv->base + 2 * count->id + 1;
  826. /* Map Generic Counter count mode to 104-QUAD-8 count mode */
  827. switch (cnt_mode) {
  828. case COUNTER_COUNT_MODE_NORMAL:
  829. cnt_mode = 0;
  830. break;
  831. case COUNTER_COUNT_MODE_RANGE_LIMIT:
  832. cnt_mode = 1;
  833. break;
  834. case COUNTER_COUNT_MODE_NON_RECYCLE:
  835. cnt_mode = 2;
  836. break;
  837. case COUNTER_COUNT_MODE_MODULO_N:
  838. cnt_mode = 3;
  839. break;
  840. }
  841. mutex_lock(&priv->lock);
  842. priv->count_mode[count->id] = cnt_mode;
  843. /* Set count mode configuration value */
  844. mode_cfg = cnt_mode << 1;
  845. /* Add quadrature mode configuration */
  846. if (priv->quadrature_mode[count->id])
  847. mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3;
  848. /* Load mode configuration to Counter Mode Register */
  849. outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
  850. mutex_unlock(&priv->lock);
  851. return 0;
  852. }
  853. static struct counter_count_enum_ext quad8_cnt_mode_enum = {
  854. .items = counter_count_mode_str,
  855. .num_items = ARRAY_SIZE(counter_count_mode_str),
  856. .get = quad8_count_mode_get,
  857. .set = quad8_count_mode_set
  858. };
  859. static ssize_t quad8_count_direction_read(struct counter_device *counter,
  860. struct counter_count *count, void *priv, char *buf)
  861. {
  862. enum counter_count_direction dir;
  863. quad8_direction_get(counter, count, &dir);
  864. return sprintf(buf, "%s\n", counter_count_direction_str[dir]);
  865. }
  866. static ssize_t quad8_count_enable_read(struct counter_device *counter,
  867. struct counter_count *count, void *private, char *buf)
  868. {
  869. const struct quad8_iio *const priv = counter->priv;
  870. return sprintf(buf, "%u\n", priv->ab_enable[count->id]);
  871. }
  872. static ssize_t quad8_count_enable_write(struct counter_device *counter,
  873. struct counter_count *count, void *private, const char *buf, size_t len)
  874. {
  875. struct quad8_iio *const priv = counter->priv;
  876. const int base_offset = priv->base + 2 * count->id;
  877. int err;
  878. bool ab_enable;
  879. unsigned int ior_cfg;
  880. err = kstrtobool(buf, &ab_enable);
  881. if (err)
  882. return err;
  883. mutex_lock(&priv->lock);
  884. priv->ab_enable[count->id] = ab_enable;
  885. ior_cfg = ab_enable | priv->preset_enable[count->id] << 1;
  886. /* Load I/O control configuration */
  887. outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
  888. mutex_unlock(&priv->lock);
  889. return len;
  890. }
  891. static int quad8_error_noise_get(struct counter_device *counter,
  892. struct counter_count *count, size_t *noise_error)
  893. {
  894. const struct quad8_iio *const priv = counter->priv;
  895. const int base_offset = priv->base + 2 * count->id + 1;
  896. *noise_error = !!(inb(base_offset) & QUAD8_FLAG_E);
  897. return 0;
  898. }
  899. static struct counter_count_enum_ext quad8_error_noise_enum = {
  900. .items = quad8_noise_error_states,
  901. .num_items = ARRAY_SIZE(quad8_noise_error_states),
  902. .get = quad8_error_noise_get
  903. };
  904. static ssize_t quad8_count_preset_read(struct counter_device *counter,
  905. struct counter_count *count, void *private, char *buf)
  906. {
  907. const struct quad8_iio *const priv = counter->priv;
  908. return sprintf(buf, "%u\n", priv->preset[count->id]);
  909. }
  910. static void quad8_preset_register_set(struct quad8_iio *quad8iio, int id,
  911. unsigned int preset)
  912. {
  913. const unsigned int base_offset = quad8iio->base + 2 * id;
  914. int i;
  915. quad8iio->preset[id] = preset;
  916. /* Reset Byte Pointer */
  917. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
  918. /* Set Preset Register */
  919. for (i = 0; i < 3; i++)
  920. outb(preset >> (8 * i), base_offset);
  921. }
  922. static ssize_t quad8_count_preset_write(struct counter_device *counter,
  923. struct counter_count *count, void *private, const char *buf, size_t len)
  924. {
  925. struct quad8_iio *const priv = counter->priv;
  926. unsigned int preset;
  927. int ret;
  928. ret = kstrtouint(buf, 0, &preset);
  929. if (ret)
  930. return ret;
  931. /* Only 24-bit values are supported */
  932. if (preset > 0xFFFFFF)
  933. return -EINVAL;
  934. mutex_lock(&priv->lock);
  935. quad8_preset_register_set(priv, count->id, preset);
  936. mutex_unlock(&priv->lock);
  937. return len;
  938. }
  939. static ssize_t quad8_count_ceiling_read(struct counter_device *counter,
  940. struct counter_count *count, void *private, char *buf)
  941. {
  942. struct quad8_iio *const priv = counter->priv;
  943. mutex_lock(&priv->lock);
  944. /* Range Limit and Modulo-N count modes use preset value as ceiling */
  945. switch (priv->count_mode[count->id]) {
  946. case 1:
  947. case 3:
  948. mutex_unlock(&priv->lock);
  949. return sprintf(buf, "%u\n", priv->preset[count->id]);
  950. }
  951. mutex_unlock(&priv->lock);
  952. /* By default 0x1FFFFFF (25 bits unsigned) is maximum count */
  953. return sprintf(buf, "33554431\n");
  954. }
  955. static ssize_t quad8_count_ceiling_write(struct counter_device *counter,
  956. struct counter_count *count, void *private, const char *buf, size_t len)
  957. {
  958. struct quad8_iio *const priv = counter->priv;
  959. unsigned int ceiling;
  960. int ret;
  961. ret = kstrtouint(buf, 0, &ceiling);
  962. if (ret)
  963. return ret;
  964. /* Only 24-bit values are supported */
  965. if (ceiling > 0xFFFFFF)
  966. return -EINVAL;
  967. mutex_lock(&priv->lock);
  968. /* Range Limit and Modulo-N count modes use preset value as ceiling */
  969. switch (priv->count_mode[count->id]) {
  970. case 1:
  971. case 3:
  972. quad8_preset_register_set(priv, count->id, ceiling);
  973. mutex_unlock(&priv->lock);
  974. return len;
  975. }
  976. mutex_unlock(&priv->lock);
  977. return -EINVAL;
  978. }
  979. static ssize_t quad8_count_preset_enable_read(struct counter_device *counter,
  980. struct counter_count *count, void *private, char *buf)
  981. {
  982. const struct quad8_iio *const priv = counter->priv;
  983. return sprintf(buf, "%u\n", !priv->preset_enable[count->id]);
  984. }
  985. static ssize_t quad8_count_preset_enable_write(struct counter_device *counter,
  986. struct counter_count *count, void *private, const char *buf, size_t len)
  987. {
  988. struct quad8_iio *const priv = counter->priv;
  989. const int base_offset = priv->base + 2 * count->id + 1;
  990. bool preset_enable;
  991. int ret;
  992. unsigned int ior_cfg;
  993. ret = kstrtobool(buf, &preset_enable);
  994. if (ret)
  995. return ret;
  996. /* Preset enable is active low in Input/Output Control register */
  997. preset_enable = !preset_enable;
  998. mutex_lock(&priv->lock);
  999. priv->preset_enable[count->id] = preset_enable;
  1000. ior_cfg = priv->ab_enable[count->id] | (unsigned int)preset_enable << 1;
  1001. /* Load I/O control configuration to Input / Output Control Register */
  1002. outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
  1003. mutex_unlock(&priv->lock);
  1004. return len;
  1005. }
  1006. static ssize_t quad8_signal_cable_fault_read(struct counter_device *counter,
  1007. struct counter_signal *signal,
  1008. void *private, char *buf)
  1009. {
  1010. struct quad8_iio *const priv = counter->priv;
  1011. const size_t channel_id = signal->id / 2;
  1012. bool disabled;
  1013. unsigned int status;
  1014. unsigned int fault;
  1015. mutex_lock(&priv->lock);
  1016. disabled = !(priv->cable_fault_enable & BIT(channel_id));
  1017. if (disabled) {
  1018. mutex_unlock(&priv->lock);
  1019. return -EINVAL;
  1020. }
  1021. /* Logic 0 = cable fault */
  1022. status = inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
  1023. mutex_unlock(&priv->lock);
  1024. /* Mask respective channel and invert logic */
  1025. fault = !(status & BIT(channel_id));
  1026. return sprintf(buf, "%u\n", fault);
  1027. }
  1028. static ssize_t quad8_signal_cable_fault_enable_read(
  1029. struct counter_device *counter, struct counter_signal *signal,
  1030. void *private, char *buf)
  1031. {
  1032. const struct quad8_iio *const priv = counter->priv;
  1033. const size_t channel_id = signal->id / 2;
  1034. const unsigned int enb = !!(priv->cable_fault_enable & BIT(channel_id));
  1035. return sprintf(buf, "%u\n", enb);
  1036. }
  1037. static ssize_t quad8_signal_cable_fault_enable_write(
  1038. struct counter_device *counter, struct counter_signal *signal,
  1039. void *private, const char *buf, size_t len)
  1040. {
  1041. struct quad8_iio *const priv = counter->priv;
  1042. const size_t channel_id = signal->id / 2;
  1043. bool enable;
  1044. int ret;
  1045. unsigned int cable_fault_enable;
  1046. ret = kstrtobool(buf, &enable);
  1047. if (ret)
  1048. return ret;
  1049. mutex_lock(&priv->lock);
  1050. if (enable)
  1051. priv->cable_fault_enable |= BIT(channel_id);
  1052. else
  1053. priv->cable_fault_enable &= ~BIT(channel_id);
  1054. /* Enable is active low in Differential Encoder Cable Status register */
  1055. cable_fault_enable = ~priv->cable_fault_enable;
  1056. outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
  1057. mutex_unlock(&priv->lock);
  1058. return len;
  1059. }
  1060. static ssize_t quad8_signal_fck_prescaler_read(struct counter_device *counter,
  1061. struct counter_signal *signal, void *private, char *buf)
  1062. {
  1063. const struct quad8_iio *const priv = counter->priv;
  1064. const size_t channel_id = signal->id / 2;
  1065. return sprintf(buf, "%u\n", priv->fck_prescaler[channel_id]);
  1066. }
  1067. static ssize_t quad8_signal_fck_prescaler_write(struct counter_device *counter,
  1068. struct counter_signal *signal, void *private, const char *buf,
  1069. size_t len)
  1070. {
  1071. struct quad8_iio *const priv = counter->priv;
  1072. const size_t channel_id = signal->id / 2;
  1073. const int base_offset = priv->base + 2 * channel_id;
  1074. u8 prescaler;
  1075. int ret;
  1076. ret = kstrtou8(buf, 0, &prescaler);
  1077. if (ret)
  1078. return ret;
  1079. mutex_lock(&priv->lock);
  1080. priv->fck_prescaler[channel_id] = prescaler;
  1081. /* Reset Byte Pointer */
  1082. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
  1083. /* Set filter clock factor */
  1084. outb(prescaler, base_offset);
  1085. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
  1086. base_offset + 1);
  1087. mutex_unlock(&priv->lock);
  1088. return len;
  1089. }
  1090. static const struct counter_signal_ext quad8_signal_ext[] = {
  1091. {
  1092. .name = "cable_fault",
  1093. .read = quad8_signal_cable_fault_read
  1094. },
  1095. {
  1096. .name = "cable_fault_enable",
  1097. .read = quad8_signal_cable_fault_enable_read,
  1098. .write = quad8_signal_cable_fault_enable_write
  1099. },
  1100. {
  1101. .name = "filter_clock_prescaler",
  1102. .read = quad8_signal_fck_prescaler_read,
  1103. .write = quad8_signal_fck_prescaler_write
  1104. }
  1105. };
  1106. static const struct counter_signal_ext quad8_index_ext[] = {
  1107. COUNTER_SIGNAL_ENUM("index_polarity", &quad8_index_pol_enum),
  1108. COUNTER_SIGNAL_ENUM_AVAILABLE("index_polarity", &quad8_index_pol_enum),
  1109. COUNTER_SIGNAL_ENUM("synchronous_mode", &quad8_syn_mode_enum),
  1110. COUNTER_SIGNAL_ENUM_AVAILABLE("synchronous_mode", &quad8_syn_mode_enum)
  1111. };
  1112. #define QUAD8_QUAD_SIGNAL(_id, _name) { \
  1113. .id = (_id), \
  1114. .name = (_name), \
  1115. .ext = quad8_signal_ext, \
  1116. .num_ext = ARRAY_SIZE(quad8_signal_ext) \
  1117. }
  1118. #define QUAD8_INDEX_SIGNAL(_id, _name) { \
  1119. .id = (_id), \
  1120. .name = (_name), \
  1121. .ext = quad8_index_ext, \
  1122. .num_ext = ARRAY_SIZE(quad8_index_ext) \
  1123. }
  1124. static struct counter_signal quad8_signals[] = {
  1125. QUAD8_QUAD_SIGNAL(0, "Channel 1 Quadrature A"),
  1126. QUAD8_QUAD_SIGNAL(1, "Channel 1 Quadrature B"),
  1127. QUAD8_QUAD_SIGNAL(2, "Channel 2 Quadrature A"),
  1128. QUAD8_QUAD_SIGNAL(3, "Channel 2 Quadrature B"),
  1129. QUAD8_QUAD_SIGNAL(4, "Channel 3 Quadrature A"),
  1130. QUAD8_QUAD_SIGNAL(5, "Channel 3 Quadrature B"),
  1131. QUAD8_QUAD_SIGNAL(6, "Channel 4 Quadrature A"),
  1132. QUAD8_QUAD_SIGNAL(7, "Channel 4 Quadrature B"),
  1133. QUAD8_QUAD_SIGNAL(8, "Channel 5 Quadrature A"),
  1134. QUAD8_QUAD_SIGNAL(9, "Channel 5 Quadrature B"),
  1135. QUAD8_QUAD_SIGNAL(10, "Channel 6 Quadrature A"),
  1136. QUAD8_QUAD_SIGNAL(11, "Channel 6 Quadrature B"),
  1137. QUAD8_QUAD_SIGNAL(12, "Channel 7 Quadrature A"),
  1138. QUAD8_QUAD_SIGNAL(13, "Channel 7 Quadrature B"),
  1139. QUAD8_QUAD_SIGNAL(14, "Channel 8 Quadrature A"),
  1140. QUAD8_QUAD_SIGNAL(15, "Channel 8 Quadrature B"),
  1141. QUAD8_INDEX_SIGNAL(16, "Channel 1 Index"),
  1142. QUAD8_INDEX_SIGNAL(17, "Channel 2 Index"),
  1143. QUAD8_INDEX_SIGNAL(18, "Channel 3 Index"),
  1144. QUAD8_INDEX_SIGNAL(19, "Channel 4 Index"),
  1145. QUAD8_INDEX_SIGNAL(20, "Channel 5 Index"),
  1146. QUAD8_INDEX_SIGNAL(21, "Channel 6 Index"),
  1147. QUAD8_INDEX_SIGNAL(22, "Channel 7 Index"),
  1148. QUAD8_INDEX_SIGNAL(23, "Channel 8 Index")
  1149. };
  1150. #define QUAD8_COUNT_SYNAPSES(_id) { \
  1151. { \
  1152. .actions_list = quad8_synapse_actions_list, \
  1153. .num_actions = ARRAY_SIZE(quad8_synapse_actions_list), \
  1154. .signal = quad8_signals + 2 * (_id) \
  1155. }, \
  1156. { \
  1157. .actions_list = quad8_synapse_actions_list, \
  1158. .num_actions = ARRAY_SIZE(quad8_synapse_actions_list), \
  1159. .signal = quad8_signals + 2 * (_id) + 1 \
  1160. }, \
  1161. { \
  1162. .actions_list = quad8_index_actions_list, \
  1163. .num_actions = ARRAY_SIZE(quad8_index_actions_list), \
  1164. .signal = quad8_signals + 2 * (_id) + 16 \
  1165. } \
  1166. }
  1167. static struct counter_synapse quad8_count_synapses[][3] = {
  1168. QUAD8_COUNT_SYNAPSES(0), QUAD8_COUNT_SYNAPSES(1),
  1169. QUAD8_COUNT_SYNAPSES(2), QUAD8_COUNT_SYNAPSES(3),
  1170. QUAD8_COUNT_SYNAPSES(4), QUAD8_COUNT_SYNAPSES(5),
  1171. QUAD8_COUNT_SYNAPSES(6), QUAD8_COUNT_SYNAPSES(7)
  1172. };
  1173. static const struct counter_count_ext quad8_count_ext[] = {
  1174. {
  1175. .name = "ceiling",
  1176. .read = quad8_count_ceiling_read,
  1177. .write = quad8_count_ceiling_write
  1178. },
  1179. {
  1180. .name = "floor",
  1181. .read = quad8_count_floor_read
  1182. },
  1183. COUNTER_COUNT_ENUM("count_mode", &quad8_cnt_mode_enum),
  1184. COUNTER_COUNT_ENUM_AVAILABLE("count_mode", &quad8_cnt_mode_enum),
  1185. {
  1186. .name = "direction",
  1187. .read = quad8_count_direction_read
  1188. },
  1189. {
  1190. .name = "enable",
  1191. .read = quad8_count_enable_read,
  1192. .write = quad8_count_enable_write
  1193. },
  1194. COUNTER_COUNT_ENUM("error_noise", &quad8_error_noise_enum),
  1195. COUNTER_COUNT_ENUM_AVAILABLE("error_noise", &quad8_error_noise_enum),
  1196. {
  1197. .name = "preset",
  1198. .read = quad8_count_preset_read,
  1199. .write = quad8_count_preset_write
  1200. },
  1201. {
  1202. .name = "preset_enable",
  1203. .read = quad8_count_preset_enable_read,
  1204. .write = quad8_count_preset_enable_write
  1205. }
  1206. };
  1207. #define QUAD8_COUNT(_id, _cntname) { \
  1208. .id = (_id), \
  1209. .name = (_cntname), \
  1210. .functions_list = quad8_count_functions_list, \
  1211. .num_functions = ARRAY_SIZE(quad8_count_functions_list), \
  1212. .synapses = quad8_count_synapses[(_id)], \
  1213. .num_synapses = 2, \
  1214. .ext = quad8_count_ext, \
  1215. .num_ext = ARRAY_SIZE(quad8_count_ext) \
  1216. }
  1217. static struct counter_count quad8_counts[] = {
  1218. QUAD8_COUNT(0, "Channel 1 Count"),
  1219. QUAD8_COUNT(1, "Channel 2 Count"),
  1220. QUAD8_COUNT(2, "Channel 3 Count"),
  1221. QUAD8_COUNT(3, "Channel 4 Count"),
  1222. QUAD8_COUNT(4, "Channel 5 Count"),
  1223. QUAD8_COUNT(5, "Channel 6 Count"),
  1224. QUAD8_COUNT(6, "Channel 7 Count"),
  1225. QUAD8_COUNT(7, "Channel 8 Count")
  1226. };
  1227. static int quad8_probe(struct device *dev, unsigned int id)
  1228. {
  1229. struct iio_dev *indio_dev;
  1230. struct quad8_iio *quad8iio;
  1231. int i, j;
  1232. unsigned int base_offset;
  1233. int err;
  1234. if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) {
  1235. dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
  1236. base[id], base[id] + QUAD8_EXTENT);
  1237. return -EBUSY;
  1238. }
  1239. /* Allocate IIO device; this also allocates driver data structure */
  1240. indio_dev = devm_iio_device_alloc(dev, sizeof(*quad8iio));
  1241. if (!indio_dev)
  1242. return -ENOMEM;
  1243. /* Initialize IIO device */
  1244. indio_dev->info = &quad8_info;
  1245. indio_dev->modes = INDIO_DIRECT_MODE;
  1246. indio_dev->num_channels = ARRAY_SIZE(quad8_channels);
  1247. indio_dev->channels = quad8_channels;
  1248. indio_dev->name = dev_name(dev);
  1249. /* Initialize Counter device and driver data */
  1250. quad8iio = iio_priv(indio_dev);
  1251. quad8iio->counter.name = dev_name(dev);
  1252. quad8iio->counter.parent = dev;
  1253. quad8iio->counter.ops = &quad8_ops;
  1254. quad8iio->counter.counts = quad8_counts;
  1255. quad8iio->counter.num_counts = ARRAY_SIZE(quad8_counts);
  1256. quad8iio->counter.signals = quad8_signals;
  1257. quad8iio->counter.num_signals = ARRAY_SIZE(quad8_signals);
  1258. quad8iio->counter.priv = quad8iio;
  1259. quad8iio->base = base[id];
  1260. /* Initialize mutex */
  1261. mutex_init(&quad8iio->lock);
  1262. /* Reset all counters and disable interrupt function */
  1263. outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
  1264. /* Set initial configuration for all counters */
  1265. for (i = 0; i < QUAD8_NUM_COUNTERS; i++) {
  1266. base_offset = base[id] + 2 * i;
  1267. /* Reset Byte Pointer */
  1268. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
  1269. /* Reset filter clock factor */
  1270. outb(0, base_offset);
  1271. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
  1272. base_offset + 1);
  1273. /* Reset Byte Pointer */
  1274. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
  1275. /* Reset Preset Register */
  1276. for (j = 0; j < 3; j++)
  1277. outb(0x00, base_offset);
  1278. /* Reset Borrow, Carry, Compare, and Sign flags */
  1279. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
  1280. /* Reset Error flag */
  1281. outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
  1282. /* Binary encoding; Normal count; non-quadrature mode */
  1283. outb(QUAD8_CTR_CMR, base_offset + 1);
  1284. /* Disable A and B inputs; preset on index; FLG1 as Carry */
  1285. outb(QUAD8_CTR_IOR, base_offset + 1);
  1286. /* Disable index function; negative index polarity */
  1287. outb(QUAD8_CTR_IDR, base_offset + 1);
  1288. }
  1289. /* Disable Differential Encoder Cable Status for all channels */
  1290. outb(0xFF, base[id] + QUAD8_DIFF_ENCODER_CABLE_STATUS);
  1291. /* Enable all counters */
  1292. outb(QUAD8_CHAN_OP_ENABLE_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
  1293. /* Register IIO device */
  1294. err = devm_iio_device_register(dev, indio_dev);
  1295. if (err)
  1296. return err;
  1297. /* Register Counter device */
  1298. return devm_counter_register(dev, &quad8iio->counter);
  1299. }
  1300. static struct isa_driver quad8_driver = {
  1301. .probe = quad8_probe,
  1302. .driver = {
  1303. .name = "104-quad-8"
  1304. }
  1305. };
  1306. module_isa_driver(quad8_driver, num_quad8);
  1307. MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
  1308. MODULE_DESCRIPTION("ACCES 104-QUAD-8 IIO driver");
  1309. MODULE_LICENSE("GPL v2");