timer-vf-pit.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2012-2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <linux/interrupt.h>
  6. #include <linux/clockchips.h>
  7. #include <linux/clk.h>
  8. #include <linux/of_address.h>
  9. #include <linux/of_irq.h>
  10. #include <linux/sched_clock.h>
  11. /*
  12. * Each pit takes 0x10 Bytes register space
  13. */
  14. #define PITMCR 0x00
  15. #define PIT0_OFFSET 0x100
  16. #define PITn_OFFSET(n) (PIT0_OFFSET + 0x10 * (n))
  17. #define PITLDVAL 0x00
  18. #define PITCVAL 0x04
  19. #define PITTCTRL 0x08
  20. #define PITTFLG 0x0c
  21. #define PITMCR_MDIS (0x1 << 1)
  22. #define PITTCTRL_TEN (0x1 << 0)
  23. #define PITTCTRL_TIE (0x1 << 1)
  24. #define PITCTRL_CHN (0x1 << 2)
  25. #define PITTFLG_TIF 0x1
  26. static void __iomem *clksrc_base;
  27. static void __iomem *clkevt_base;
  28. static unsigned long cycle_per_jiffy;
  29. static inline void pit_timer_enable(void)
  30. {
  31. __raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
  32. }
  33. static inline void pit_timer_disable(void)
  34. {
  35. __raw_writel(0, clkevt_base + PITTCTRL);
  36. }
  37. static inline void pit_irq_acknowledge(void)
  38. {
  39. __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
  40. }
  41. static u64 notrace pit_read_sched_clock(void)
  42. {
  43. return ~__raw_readl(clksrc_base + PITCVAL);
  44. }
  45. static int __init pit_clocksource_init(unsigned long rate)
  46. {
  47. /* set the max load value and start the clock source counter */
  48. __raw_writel(0, clksrc_base + PITTCTRL);
  49. __raw_writel(~0UL, clksrc_base + PITLDVAL);
  50. __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
  51. sched_clock_register(pit_read_sched_clock, 32, rate);
  52. return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate,
  53. 300, 32, clocksource_mmio_readl_down);
  54. }
  55. static int pit_set_next_event(unsigned long delta,
  56. struct clock_event_device *unused)
  57. {
  58. /*
  59. * set a new value to PITLDVAL register will not restart the timer,
  60. * to abort the current cycle and start a timer period with the new
  61. * value, the timer must be disabled and enabled again.
  62. * and the PITLAVAL should be set to delta minus one according to pit
  63. * hardware requirement.
  64. */
  65. pit_timer_disable();
  66. __raw_writel(delta - 1, clkevt_base + PITLDVAL);
  67. pit_timer_enable();
  68. return 0;
  69. }
  70. static int pit_shutdown(struct clock_event_device *evt)
  71. {
  72. pit_timer_disable();
  73. return 0;
  74. }
  75. static int pit_set_periodic(struct clock_event_device *evt)
  76. {
  77. pit_set_next_event(cycle_per_jiffy, evt);
  78. return 0;
  79. }
  80. static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
  81. {
  82. struct clock_event_device *evt = dev_id;
  83. pit_irq_acknowledge();
  84. /*
  85. * pit hardware doesn't support oneshot, it will generate an interrupt
  86. * and reload the counter value from PITLDVAL when PITCVAL reach zero,
  87. * and start the counter again. So software need to disable the timer
  88. * to stop the counter loop in ONESHOT mode.
  89. */
  90. if (likely(clockevent_state_oneshot(evt)))
  91. pit_timer_disable();
  92. evt->event_handler(evt);
  93. return IRQ_HANDLED;
  94. }
  95. static struct clock_event_device clockevent_pit = {
  96. .name = "VF pit timer",
  97. .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  98. .set_state_shutdown = pit_shutdown,
  99. .set_state_periodic = pit_set_periodic,
  100. .set_next_event = pit_set_next_event,
  101. .rating = 300,
  102. };
  103. static int __init pit_clockevent_init(unsigned long rate, int irq)
  104. {
  105. __raw_writel(0, clkevt_base + PITTCTRL);
  106. __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
  107. BUG_ON(request_irq(irq, pit_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
  108. "VF pit timer", &clockevent_pit));
  109. clockevent_pit.cpumask = cpumask_of(0);
  110. clockevent_pit.irq = irq;
  111. /*
  112. * The value for the LDVAL register trigger is calculated as:
  113. * LDVAL trigger = (period / clock period) - 1
  114. * The pit is a 32-bit down count timer, when the conter value
  115. * reaches 0, it will generate an interrupt, thus the minimal
  116. * LDVAL trigger value is 1. And then the min_delta is
  117. * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit.
  118. */
  119. clockevents_config_and_register(&clockevent_pit, rate, 2, 0xffffffff);
  120. return 0;
  121. }
  122. static int __init pit_timer_init(struct device_node *np)
  123. {
  124. struct clk *pit_clk;
  125. void __iomem *timer_base;
  126. unsigned long clk_rate;
  127. int irq, ret;
  128. timer_base = of_iomap(np, 0);
  129. if (!timer_base) {
  130. pr_err("Failed to iomap\n");
  131. return -ENXIO;
  132. }
  133. /*
  134. * PIT0 and PIT1 can be chained to build a 64-bit timer,
  135. * so choose PIT2 as clocksource, PIT3 as clockevent device,
  136. * and leave PIT0 and PIT1 unused for anyone else who needs them.
  137. */
  138. clksrc_base = timer_base + PITn_OFFSET(2);
  139. clkevt_base = timer_base + PITn_OFFSET(3);
  140. irq = irq_of_parse_and_map(np, 0);
  141. if (irq <= 0)
  142. return -EINVAL;
  143. pit_clk = of_clk_get(np, 0);
  144. if (IS_ERR(pit_clk))
  145. return PTR_ERR(pit_clk);
  146. ret = clk_prepare_enable(pit_clk);
  147. if (ret)
  148. return ret;
  149. clk_rate = clk_get_rate(pit_clk);
  150. cycle_per_jiffy = clk_rate / (HZ);
  151. /* enable the pit module */
  152. __raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
  153. ret = pit_clocksource_init(clk_rate);
  154. if (ret)
  155. return ret;
  156. return pit_clockevent_init(clk_rate, irq);
  157. }
  158. TIMER_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);