timer-u300.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2007-2009 ST-Ericsson AB
  4. * Timer COH 901 328, runs the OS timer interrupt.
  5. * Author: Linus Walleij <linus.walleij@stericsson.com>
  6. */
  7. #include <linux/interrupt.h>
  8. #include <linux/time.h>
  9. #include <linux/timex.h>
  10. #include <linux/clockchips.h>
  11. #include <linux/clocksource.h>
  12. #include <linux/types.h>
  13. #include <linux/io.h>
  14. #include <linux/clk.h>
  15. #include <linux/err.h>
  16. #include <linux/irq.h>
  17. #include <linux/delay.h>
  18. #include <linux/of_address.h>
  19. #include <linux/of_irq.h>
  20. #include <linux/sched_clock.h>
  21. /* Generic stuff */
  22. #include <asm/mach/map.h>
  23. #include <asm/mach/time.h>
  24. /*
  25. * APP side special timer registers
  26. * This timer contains four timers which can fire an interrupt each.
  27. * OS (operating system) timer @ 32768 Hz
  28. * DD (device driver) timer @ 1 kHz
  29. * GP1 (general purpose 1) timer @ 1MHz
  30. * GP2 (general purpose 2) timer @ 1MHz
  31. */
  32. /* Reset OS Timer 32bit (-/W) */
  33. #define U300_TIMER_APP_ROST (0x0000)
  34. #define U300_TIMER_APP_ROST_TIMER_RESET (0x00000000)
  35. /* Enable OS Timer 32bit (-/W) */
  36. #define U300_TIMER_APP_EOST (0x0004)
  37. #define U300_TIMER_APP_EOST_TIMER_ENABLE (0x00000000)
  38. /* Disable OS Timer 32bit (-/W) */
  39. #define U300_TIMER_APP_DOST (0x0008)
  40. #define U300_TIMER_APP_DOST_TIMER_DISABLE (0x00000000)
  41. /* OS Timer Mode Register 32bit (-/W) */
  42. #define U300_TIMER_APP_SOSTM (0x000c)
  43. #define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS (0x00000000)
  44. #define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT (0x00000001)
  45. /* OS Timer Status Register 32bit (R/-) */
  46. #define U300_TIMER_APP_OSTS (0x0010)
  47. #define U300_TIMER_APP_OSTS_TIMER_STATE_MASK (0x0000000F)
  48. #define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE (0x00000001)
  49. #define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE (0x00000002)
  50. #define U300_TIMER_APP_OSTS_ENABLE_IND (0x00000010)
  51. #define U300_TIMER_APP_OSTS_MODE_MASK (0x00000020)
  52. #define U300_TIMER_APP_OSTS_MODE_CONTINUOUS (0x00000000)
  53. #define U300_TIMER_APP_OSTS_MODE_ONE_SHOT (0x00000020)
  54. #define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND (0x00000040)
  55. #define U300_TIMER_APP_OSTS_IRQ_PENDING_IND (0x00000080)
  56. /* OS Timer Current Count Register 32bit (R/-) */
  57. #define U300_TIMER_APP_OSTCC (0x0014)
  58. /* OS Timer Terminal Count Register 32bit (R/W) */
  59. #define U300_TIMER_APP_OSTTC (0x0018)
  60. /* OS Timer Interrupt Enable Register 32bit (-/W) */
  61. #define U300_TIMER_APP_OSTIE (0x001c)
  62. #define U300_TIMER_APP_OSTIE_IRQ_DISABLE (0x00000000)
  63. #define U300_TIMER_APP_OSTIE_IRQ_ENABLE (0x00000001)
  64. /* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
  65. #define U300_TIMER_APP_OSTIA (0x0020)
  66. #define U300_TIMER_APP_OSTIA_IRQ_ACK (0x00000080)
  67. /* Reset DD Timer 32bit (-/W) */
  68. #define U300_TIMER_APP_RDDT (0x0040)
  69. #define U300_TIMER_APP_RDDT_TIMER_RESET (0x00000000)
  70. /* Enable DD Timer 32bit (-/W) */
  71. #define U300_TIMER_APP_EDDT (0x0044)
  72. #define U300_TIMER_APP_EDDT_TIMER_ENABLE (0x00000000)
  73. /* Disable DD Timer 32bit (-/W) */
  74. #define U300_TIMER_APP_DDDT (0x0048)
  75. #define U300_TIMER_APP_DDDT_TIMER_DISABLE (0x00000000)
  76. /* DD Timer Mode Register 32bit (-/W) */
  77. #define U300_TIMER_APP_SDDTM (0x004c)
  78. #define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS (0x00000000)
  79. #define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT (0x00000001)
  80. /* DD Timer Status Register 32bit (R/-) */
  81. #define U300_TIMER_APP_DDTS (0x0050)
  82. #define U300_TIMER_APP_DDTS_TIMER_STATE_MASK (0x0000000F)
  83. #define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE (0x00000001)
  84. #define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE (0x00000002)
  85. #define U300_TIMER_APP_DDTS_ENABLE_IND (0x00000010)
  86. #define U300_TIMER_APP_DDTS_MODE_MASK (0x00000020)
  87. #define U300_TIMER_APP_DDTS_MODE_CONTINUOUS (0x00000000)
  88. #define U300_TIMER_APP_DDTS_MODE_ONE_SHOT (0x00000020)
  89. #define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND (0x00000040)
  90. #define U300_TIMER_APP_DDTS_IRQ_PENDING_IND (0x00000080)
  91. /* DD Timer Current Count Register 32bit (R/-) */
  92. #define U300_TIMER_APP_DDTCC (0x0054)
  93. /* DD Timer Terminal Count Register 32bit (R/W) */
  94. #define U300_TIMER_APP_DDTTC (0x0058)
  95. /* DD Timer Interrupt Enable Register 32bit (-/W) */
  96. #define U300_TIMER_APP_DDTIE (0x005c)
  97. #define U300_TIMER_APP_DDTIE_IRQ_DISABLE (0x00000000)
  98. #define U300_TIMER_APP_DDTIE_IRQ_ENABLE (0x00000001)
  99. /* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
  100. #define U300_TIMER_APP_DDTIA (0x0060)
  101. #define U300_TIMER_APP_DDTIA_IRQ_ACK (0x00000080)
  102. /* Reset GP1 Timer 32bit (-/W) */
  103. #define U300_TIMER_APP_RGPT1 (0x0080)
  104. #define U300_TIMER_APP_RGPT1_TIMER_RESET (0x00000000)
  105. /* Enable GP1 Timer 32bit (-/W) */
  106. #define U300_TIMER_APP_EGPT1 (0x0084)
  107. #define U300_TIMER_APP_EGPT1_TIMER_ENABLE (0x00000000)
  108. /* Disable GP1 Timer 32bit (-/W) */
  109. #define U300_TIMER_APP_DGPT1 (0x0088)
  110. #define U300_TIMER_APP_DGPT1_TIMER_DISABLE (0x00000000)
  111. /* GP1 Timer Mode Register 32bit (-/W) */
  112. #define U300_TIMER_APP_SGPT1M (0x008c)
  113. #define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS (0x00000000)
  114. #define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT (0x00000001)
  115. /* GP1 Timer Status Register 32bit (R/-) */
  116. #define U300_TIMER_APP_GPT1S (0x0090)
  117. #define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK (0x0000000F)
  118. #define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE (0x00000001)
  119. #define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE (0x00000002)
  120. #define U300_TIMER_APP_GPT1S_ENABLE_IND (0x00000010)
  121. #define U300_TIMER_APP_GPT1S_MODE_MASK (0x00000020)
  122. #define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS (0x00000000)
  123. #define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT (0x00000020)
  124. #define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND (0x00000040)
  125. #define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND (0x00000080)
  126. /* GP1 Timer Current Count Register 32bit (R/-) */
  127. #define U300_TIMER_APP_GPT1CC (0x0094)
  128. /* GP1 Timer Terminal Count Register 32bit (R/W) */
  129. #define U300_TIMER_APP_GPT1TC (0x0098)
  130. /* GP1 Timer Interrupt Enable Register 32bit (-/W) */
  131. #define U300_TIMER_APP_GPT1IE (0x009c)
  132. #define U300_TIMER_APP_GPT1IE_IRQ_DISABLE (0x00000000)
  133. #define U300_TIMER_APP_GPT1IE_IRQ_ENABLE (0x00000001)
  134. /* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
  135. #define U300_TIMER_APP_GPT1IA (0x00a0)
  136. #define U300_TIMER_APP_GPT1IA_IRQ_ACK (0x00000080)
  137. /* Reset GP2 Timer 32bit (-/W) */
  138. #define U300_TIMER_APP_RGPT2 (0x00c0)
  139. #define U300_TIMER_APP_RGPT2_TIMER_RESET (0x00000000)
  140. /* Enable GP2 Timer 32bit (-/W) */
  141. #define U300_TIMER_APP_EGPT2 (0x00c4)
  142. #define U300_TIMER_APP_EGPT2_TIMER_ENABLE (0x00000000)
  143. /* Disable GP2 Timer 32bit (-/W) */
  144. #define U300_TIMER_APP_DGPT2 (0x00c8)
  145. #define U300_TIMER_APP_DGPT2_TIMER_DISABLE (0x00000000)
  146. /* GP2 Timer Mode Register 32bit (-/W) */
  147. #define U300_TIMER_APP_SGPT2M (0x00cc)
  148. #define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS (0x00000000)
  149. #define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT (0x00000001)
  150. /* GP2 Timer Status Register 32bit (R/-) */
  151. #define U300_TIMER_APP_GPT2S (0x00d0)
  152. #define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK (0x0000000F)
  153. #define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE (0x00000001)
  154. #define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE (0x00000002)
  155. #define U300_TIMER_APP_GPT2S_ENABLE_IND (0x00000010)
  156. #define U300_TIMER_APP_GPT2S_MODE_MASK (0x00000020)
  157. #define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS (0x00000000)
  158. #define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT (0x00000020)
  159. #define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND (0x00000040)
  160. #define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND (0x00000080)
  161. /* GP2 Timer Current Count Register 32bit (R/-) */
  162. #define U300_TIMER_APP_GPT2CC (0x00d4)
  163. /* GP2 Timer Terminal Count Register 32bit (R/W) */
  164. #define U300_TIMER_APP_GPT2TC (0x00d8)
  165. /* GP2 Timer Interrupt Enable Register 32bit (-/W) */
  166. #define U300_TIMER_APP_GPT2IE (0x00dc)
  167. #define U300_TIMER_APP_GPT2IE_IRQ_DISABLE (0x00000000)
  168. #define U300_TIMER_APP_GPT2IE_IRQ_ENABLE (0x00000001)
  169. /* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
  170. #define U300_TIMER_APP_GPT2IA (0x00e0)
  171. #define U300_TIMER_APP_GPT2IA_IRQ_ACK (0x00000080)
  172. /* Clock request control register - all four timers */
  173. #define U300_TIMER_APP_CRC (0x100)
  174. #define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001)
  175. static void __iomem *u300_timer_base;
  176. struct u300_clockevent_data {
  177. struct clock_event_device cevd;
  178. unsigned ticks_per_jiffy;
  179. };
  180. static int u300_shutdown(struct clock_event_device *evt)
  181. {
  182. /* Disable interrupts on GP1 */
  183. writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
  184. u300_timer_base + U300_TIMER_APP_GPT1IE);
  185. /* Disable GP1 */
  186. writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
  187. u300_timer_base + U300_TIMER_APP_DGPT1);
  188. return 0;
  189. }
  190. /*
  191. * If we have oneshot timer active, the oneshot scheduling function
  192. * u300_set_next_event() is called immediately after.
  193. */
  194. static int u300_set_oneshot(struct clock_event_device *evt)
  195. {
  196. /* Just return; here? */
  197. /*
  198. * The actual event will be programmed by the next event hook,
  199. * so we just set a dummy value somewhere at the end of the
  200. * universe here.
  201. */
  202. /* Disable interrupts on GPT1 */
  203. writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
  204. u300_timer_base + U300_TIMER_APP_GPT1IE);
  205. /* Disable GP1 while we're reprogramming it. */
  206. writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
  207. u300_timer_base + U300_TIMER_APP_DGPT1);
  208. /*
  209. * Expire far in the future, u300_set_next_event() will be
  210. * called soon...
  211. */
  212. writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
  213. /* We run one shot per tick here! */
  214. writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
  215. u300_timer_base + U300_TIMER_APP_SGPT1M);
  216. /* Enable interrupts for this timer */
  217. writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
  218. u300_timer_base + U300_TIMER_APP_GPT1IE);
  219. /* Enable timer */
  220. writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
  221. u300_timer_base + U300_TIMER_APP_EGPT1);
  222. return 0;
  223. }
  224. static int u300_set_periodic(struct clock_event_device *evt)
  225. {
  226. struct u300_clockevent_data *cevdata =
  227. container_of(evt, struct u300_clockevent_data, cevd);
  228. /* Disable interrupts on GPT1 */
  229. writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
  230. u300_timer_base + U300_TIMER_APP_GPT1IE);
  231. /* Disable GP1 while we're reprogramming it. */
  232. writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
  233. u300_timer_base + U300_TIMER_APP_DGPT1);
  234. /*
  235. * Set the periodic mode to a certain number of ticks per
  236. * jiffy.
  237. */
  238. writel(cevdata->ticks_per_jiffy,
  239. u300_timer_base + U300_TIMER_APP_GPT1TC);
  240. /*
  241. * Set continuous mode, so the timer keeps triggering
  242. * interrupts.
  243. */
  244. writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
  245. u300_timer_base + U300_TIMER_APP_SGPT1M);
  246. /* Enable timer interrupts */
  247. writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
  248. u300_timer_base + U300_TIMER_APP_GPT1IE);
  249. /* Then enable the OS timer again */
  250. writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
  251. u300_timer_base + U300_TIMER_APP_EGPT1);
  252. return 0;
  253. }
  254. /*
  255. * The app timer in one shot mode obviously has to be reprogrammed
  256. * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
  257. * the interrupt disable + timer disable commands with a reset command,
  258. * it will fail miserably. Apparently (and I found this the hard way)
  259. * the timer is very sensitive to the instruction order, though you don't
  260. * get that impression from the data sheet.
  261. */
  262. static int u300_set_next_event(unsigned long cycles,
  263. struct clock_event_device *evt)
  264. {
  265. /* Disable interrupts on GPT1 */
  266. writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
  267. u300_timer_base + U300_TIMER_APP_GPT1IE);
  268. /* Disable GP1 while we're reprogramming it. */
  269. writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
  270. u300_timer_base + U300_TIMER_APP_DGPT1);
  271. /* Reset the General Purpose timer 1. */
  272. writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
  273. u300_timer_base + U300_TIMER_APP_RGPT1);
  274. /* IRQ in n * cycles */
  275. writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
  276. /*
  277. * We run one shot per tick here! (This is necessary to reconfigure,
  278. * the timer will tilt if you don't!)
  279. */
  280. writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
  281. u300_timer_base + U300_TIMER_APP_SGPT1M);
  282. /* Enable timer interrupts */
  283. writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
  284. u300_timer_base + U300_TIMER_APP_GPT1IE);
  285. /* Then enable the OS timer again */
  286. writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
  287. u300_timer_base + U300_TIMER_APP_EGPT1);
  288. return 0;
  289. }
  290. static struct u300_clockevent_data u300_clockevent_data = {
  291. /* Use general purpose timer 1 as clock event */
  292. .cevd = {
  293. .name = "GPT1",
  294. /* Reasonably fast and accurate clock event */
  295. .rating = 300,
  296. .features = CLOCK_EVT_FEAT_PERIODIC |
  297. CLOCK_EVT_FEAT_ONESHOT,
  298. .set_next_event = u300_set_next_event,
  299. .set_state_shutdown = u300_shutdown,
  300. .set_state_periodic = u300_set_periodic,
  301. .set_state_oneshot = u300_set_oneshot,
  302. },
  303. };
  304. /* Clock event timer interrupt handler */
  305. static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
  306. {
  307. struct clock_event_device *evt = &u300_clockevent_data.cevd;
  308. /* ACK/Clear timer IRQ for the APP GPT1 Timer */
  309. writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
  310. u300_timer_base + U300_TIMER_APP_GPT1IA);
  311. evt->event_handler(evt);
  312. return IRQ_HANDLED;
  313. }
  314. /*
  315. * Override the global weak sched_clock symbol with this
  316. * local implementation which uses the clocksource to get some
  317. * better resolution when scheduling the kernel. We accept that
  318. * this wraps around for now, since it is just a relative time
  319. * stamp. (Inspired by OMAP implementation.)
  320. */
  321. static u64 notrace u300_read_sched_clock(void)
  322. {
  323. return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
  324. }
  325. static unsigned long u300_read_current_timer(void)
  326. {
  327. return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
  328. }
  329. static struct delay_timer u300_delay_timer;
  330. /*
  331. * This sets up the system timers, clock source and clock event.
  332. */
  333. static int __init u300_timer_init_of(struct device_node *np)
  334. {
  335. unsigned int irq;
  336. struct clk *clk;
  337. unsigned long rate;
  338. int ret;
  339. u300_timer_base = of_iomap(np, 0);
  340. if (!u300_timer_base) {
  341. pr_err("could not ioremap system timer\n");
  342. return -ENXIO;
  343. }
  344. /* Get the IRQ for the GP1 timer */
  345. irq = irq_of_parse_and_map(np, 2);
  346. if (!irq) {
  347. pr_err("no IRQ for system timer\n");
  348. return -EINVAL;
  349. }
  350. pr_info("U300 GP1 timer @ base: %p, IRQ: %u\n", u300_timer_base, irq);
  351. /* Clock the interrupt controller */
  352. clk = of_clk_get(np, 0);
  353. if (IS_ERR(clk))
  354. return PTR_ERR(clk);
  355. ret = clk_prepare_enable(clk);
  356. if (ret)
  357. return ret;
  358. rate = clk_get_rate(clk);
  359. u300_clockevent_data.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
  360. sched_clock_register(u300_read_sched_clock, 32, rate);
  361. u300_delay_timer.read_current_timer = &u300_read_current_timer;
  362. u300_delay_timer.freq = rate;
  363. register_current_timer_delay(&u300_delay_timer);
  364. /*
  365. * Disable the "OS" and "DD" timers - these are designed for Symbian!
  366. * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
  367. */
  368. writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
  369. u300_timer_base + U300_TIMER_APP_CRC);
  370. writel(U300_TIMER_APP_ROST_TIMER_RESET,
  371. u300_timer_base + U300_TIMER_APP_ROST);
  372. writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
  373. u300_timer_base + U300_TIMER_APP_DOST);
  374. writel(U300_TIMER_APP_RDDT_TIMER_RESET,
  375. u300_timer_base + U300_TIMER_APP_RDDT);
  376. writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
  377. u300_timer_base + U300_TIMER_APP_DDDT);
  378. /* Reset the General Purpose timer 1. */
  379. writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
  380. u300_timer_base + U300_TIMER_APP_RGPT1);
  381. /* Set up the IRQ handler */
  382. ret = request_irq(irq, u300_timer_interrupt,
  383. IRQF_TIMER | IRQF_IRQPOLL, "U300 Timer Tick", NULL);
  384. if (ret)
  385. return ret;
  386. /* Reset the General Purpose timer 2 */
  387. writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
  388. u300_timer_base + U300_TIMER_APP_RGPT2);
  389. /* Set this timer to run around forever */
  390. writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
  391. /* Set continuous mode so it wraps around */
  392. writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
  393. u300_timer_base + U300_TIMER_APP_SGPT2M);
  394. /* Disable timer interrupts */
  395. writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
  396. u300_timer_base + U300_TIMER_APP_GPT2IE);
  397. /* Then enable the GP2 timer to use as a free running us counter */
  398. writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
  399. u300_timer_base + U300_TIMER_APP_EGPT2);
  400. /* Use general purpose timer 2 as clock source */
  401. ret = clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
  402. "GPT2", rate, 300, 32, clocksource_mmio_readl_up);
  403. if (ret) {
  404. pr_err("timer: failed to initialize U300 clock source\n");
  405. return ret;
  406. }
  407. /* Configure and register the clockevent */
  408. clockevents_config_and_register(&u300_clockevent_data.cevd, rate,
  409. 1, 0xffffffff);
  410. /*
  411. * TODO: init and register the rest of the timers too, they can be
  412. * used by hrtimers!
  413. */
  414. return 0;
  415. }
  416. TIMER_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
  417. u300_timer_init_of);