timer-tegra.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2010 Google, Inc.
  4. *
  5. * Author:
  6. * Colin Cross <ccross@google.com>
  7. */
  8. #define pr_fmt(fmt) "tegra-timer: " fmt
  9. #include <linux/clk.h>
  10. #include <linux/clockchips.h>
  11. #include <linux/cpu.h>
  12. #include <linux/cpumask.h>
  13. #include <linux/delay.h>
  14. #include <linux/err.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/percpu.h>
  19. #include <linux/sched_clock.h>
  20. #include <linux/time.h>
  21. #include "timer-of.h"
  22. #define RTC_SECONDS 0x08
  23. #define RTC_SHADOW_SECONDS 0x0c
  24. #define RTC_MILLISECONDS 0x10
  25. #define TIMERUS_CNTR_1US 0x10
  26. #define TIMERUS_USEC_CFG 0x14
  27. #define TIMERUS_CNTR_FREEZE 0x4c
  28. #define TIMER_PTV 0x0
  29. #define TIMER_PTV_EN BIT(31)
  30. #define TIMER_PTV_PER BIT(30)
  31. #define TIMER_PCR 0x4
  32. #define TIMER_PCR_INTR_CLR BIT(30)
  33. #define TIMER1_BASE 0x00
  34. #define TIMER2_BASE 0x08
  35. #define TIMER3_BASE 0x50
  36. #define TIMER4_BASE 0x58
  37. #define TIMER10_BASE 0x90
  38. #define TIMER1_IRQ_IDX 0
  39. #define TIMER10_IRQ_IDX 10
  40. #define TIMER_1MHz 1000000
  41. static u32 usec_config;
  42. static void __iomem *timer_reg_base;
  43. static int tegra_timer_set_next_event(unsigned long cycles,
  44. struct clock_event_device *evt)
  45. {
  46. void __iomem *reg_base = timer_of_base(to_timer_of(evt));
  47. /*
  48. * Tegra's timer uses n+1 scheme for the counter, i.e. timer will
  49. * fire after one tick if 0 is loaded.
  50. *
  51. * The minimum and maximum numbers of oneshot ticks are defined
  52. * by clockevents_config_and_register(1, 0x1fffffff + 1) invocation
  53. * below in the code. Hence the cycles (ticks) can't be outside of
  54. * a range supportable by hardware.
  55. */
  56. writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV);
  57. return 0;
  58. }
  59. static int tegra_timer_shutdown(struct clock_event_device *evt)
  60. {
  61. void __iomem *reg_base = timer_of_base(to_timer_of(evt));
  62. writel_relaxed(0, reg_base + TIMER_PTV);
  63. return 0;
  64. }
  65. static int tegra_timer_set_periodic(struct clock_event_device *evt)
  66. {
  67. void __iomem *reg_base = timer_of_base(to_timer_of(evt));
  68. unsigned long period = timer_of_period(to_timer_of(evt));
  69. writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1),
  70. reg_base + TIMER_PTV);
  71. return 0;
  72. }
  73. static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
  74. {
  75. struct clock_event_device *evt = dev_id;
  76. void __iomem *reg_base = timer_of_base(to_timer_of(evt));
  77. writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
  78. evt->event_handler(evt);
  79. return IRQ_HANDLED;
  80. }
  81. static void tegra_timer_suspend(struct clock_event_device *evt)
  82. {
  83. void __iomem *reg_base = timer_of_base(to_timer_of(evt));
  84. writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
  85. }
  86. static void tegra_timer_resume(struct clock_event_device *evt)
  87. {
  88. writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
  89. }
  90. static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
  91. .flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
  92. .clkevt = {
  93. .name = "tegra_timer",
  94. .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
  95. .set_next_event = tegra_timer_set_next_event,
  96. .set_state_shutdown = tegra_timer_shutdown,
  97. .set_state_periodic = tegra_timer_set_periodic,
  98. .set_state_oneshot = tegra_timer_shutdown,
  99. .tick_resume = tegra_timer_shutdown,
  100. .suspend = tegra_timer_suspend,
  101. .resume = tegra_timer_resume,
  102. },
  103. };
  104. static int tegra_timer_setup(unsigned int cpu)
  105. {
  106. struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
  107. writel_relaxed(0, timer_of_base(to) + TIMER_PTV);
  108. writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR);
  109. irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
  110. enable_irq(to->clkevt.irq);
  111. /*
  112. * Tegra's timer uses n+1 scheme for the counter, i.e. timer will
  113. * fire after one tick if 0 is loaded and thus minimum number of
  114. * ticks is 1. In result both of the clocksource's tick limits are
  115. * higher than a minimum and maximum that hardware register can
  116. * take by 1, this is then taken into account by set_next_event
  117. * callback.
  118. */
  119. clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
  120. 1, /* min */
  121. 0x1fffffff + 1); /* max 29 bits + 1 */
  122. return 0;
  123. }
  124. static int tegra_timer_stop(unsigned int cpu)
  125. {
  126. struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
  127. to->clkevt.set_state_shutdown(&to->clkevt);
  128. disable_irq_nosync(to->clkevt.irq);
  129. return 0;
  130. }
  131. static u64 notrace tegra_read_sched_clock(void)
  132. {
  133. return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
  134. }
  135. #ifdef CONFIG_ARM
  136. static unsigned long tegra_delay_timer_read_counter_long(void)
  137. {
  138. return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
  139. }
  140. static struct delay_timer tegra_delay_timer = {
  141. .read_current_timer = tegra_delay_timer_read_counter_long,
  142. .freq = TIMER_1MHz,
  143. };
  144. #endif
  145. static struct timer_of suspend_rtc_to = {
  146. .flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
  147. };
  148. /*
  149. * tegra_rtc_read - Reads the Tegra RTC registers
  150. * Care must be taken that this function is not called while the
  151. * tegra_rtc driver could be executing to avoid race conditions
  152. * on the RTC shadow register
  153. */
  154. static u64 tegra_rtc_read_ms(struct clocksource *cs)
  155. {
  156. void __iomem *reg_base = timer_of_base(&suspend_rtc_to);
  157. u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS);
  158. u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS);
  159. return (u64)s * MSEC_PER_SEC + ms;
  160. }
  161. static struct clocksource suspend_rtc_clocksource = {
  162. .name = "tegra_suspend_timer",
  163. .rating = 200,
  164. .read = tegra_rtc_read_ms,
  165. .mask = CLOCKSOURCE_MASK(32),
  166. .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
  167. };
  168. static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20)
  169. {
  170. if (tegra20) {
  171. switch (cpu) {
  172. case 0:
  173. return TIMER1_BASE;
  174. case 1:
  175. return TIMER2_BASE;
  176. case 2:
  177. return TIMER3_BASE;
  178. default:
  179. return TIMER4_BASE;
  180. }
  181. }
  182. return TIMER10_BASE + cpu * 8;
  183. }
  184. static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20)
  185. {
  186. if (tegra20)
  187. return TIMER1_IRQ_IDX + cpu;
  188. return TIMER10_IRQ_IDX + cpu;
  189. }
  190. static inline unsigned long tegra_rate_for_timer(struct timer_of *to,
  191. bool tegra20)
  192. {
  193. /*
  194. * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the
  195. * parent clock.
  196. */
  197. if (tegra20)
  198. return TIMER_1MHz;
  199. return timer_of_rate(to);
  200. }
  201. static int __init tegra_init_timer(struct device_node *np, bool tegra20,
  202. int rating)
  203. {
  204. struct timer_of *to;
  205. int cpu, ret;
  206. to = this_cpu_ptr(&tegra_to);
  207. ret = timer_of_init(np, to);
  208. if (ret)
  209. goto out;
  210. timer_reg_base = timer_of_base(to);
  211. /*
  212. * Configure microsecond timers to have 1MHz clock
  213. * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
  214. * Uses n+1 scheme
  215. */
  216. switch (timer_of_rate(to)) {
  217. case 12000000:
  218. usec_config = 0x000b; /* (11+1)/(0+1) */
  219. break;
  220. case 12800000:
  221. usec_config = 0x043f; /* (63+1)/(4+1) */
  222. break;
  223. case 13000000:
  224. usec_config = 0x000c; /* (12+1)/(0+1) */
  225. break;
  226. case 16800000:
  227. usec_config = 0x0453; /* (83+1)/(4+1) */
  228. break;
  229. case 19200000:
  230. usec_config = 0x045f; /* (95+1)/(4+1) */
  231. break;
  232. case 26000000:
  233. usec_config = 0x0019; /* (25+1)/(0+1) */
  234. break;
  235. case 38400000:
  236. usec_config = 0x04bf; /* (191+1)/(4+1) */
  237. break;
  238. case 48000000:
  239. usec_config = 0x002f; /* (47+1)/(0+1) */
  240. break;
  241. default:
  242. ret = -EINVAL;
  243. goto out;
  244. }
  245. writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
  246. for_each_possible_cpu(cpu) {
  247. struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu);
  248. unsigned long flags = IRQF_TIMER | IRQF_NOBALANCING;
  249. unsigned long rate = tegra_rate_for_timer(to, tegra20);
  250. unsigned int base = tegra_base_for_cpu(cpu, tegra20);
  251. unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20);
  252. unsigned int irq = irq_of_parse_and_map(np, idx);
  253. if (!irq) {
  254. pr_err("failed to map irq for cpu%d\n", cpu);
  255. ret = -EINVAL;
  256. goto out_irq;
  257. }
  258. cpu_to->clkevt.irq = irq;
  259. cpu_to->clkevt.rating = rating;
  260. cpu_to->clkevt.cpumask = cpumask_of(cpu);
  261. cpu_to->of_base.base = timer_reg_base + base;
  262. cpu_to->of_clk.period = rate / HZ;
  263. cpu_to->of_clk.rate = rate;
  264. irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
  265. ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, flags,
  266. cpu_to->clkevt.name, &cpu_to->clkevt);
  267. if (ret) {
  268. pr_err("failed to set up irq for cpu%d: %d\n",
  269. cpu, ret);
  270. irq_dispose_mapping(cpu_to->clkevt.irq);
  271. cpu_to->clkevt.irq = 0;
  272. goto out_irq;
  273. }
  274. }
  275. sched_clock_register(tegra_read_sched_clock, 32, TIMER_1MHz);
  276. ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
  277. "timer_us", TIMER_1MHz, 300, 32,
  278. clocksource_mmio_readl_up);
  279. if (ret)
  280. pr_err("failed to register clocksource: %d\n", ret);
  281. #ifdef CONFIG_ARM
  282. register_current_timer_delay(&tegra_delay_timer);
  283. #endif
  284. ret = cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
  285. "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
  286. tegra_timer_stop);
  287. if (ret)
  288. pr_err("failed to set up cpu hp state: %d\n", ret);
  289. return ret;
  290. out_irq:
  291. for_each_possible_cpu(cpu) {
  292. struct timer_of *cpu_to;
  293. cpu_to = per_cpu_ptr(&tegra_to, cpu);
  294. if (cpu_to->clkevt.irq) {
  295. free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
  296. irq_dispose_mapping(cpu_to->clkevt.irq);
  297. }
  298. }
  299. to->of_base.base = timer_reg_base;
  300. out:
  301. timer_of_cleanup(to);
  302. return ret;
  303. }
  304. static int __init tegra210_init_timer(struct device_node *np)
  305. {
  306. /*
  307. * Arch-timer can't survive across power cycle of CPU core and
  308. * after CPUPORESET signal due to a system design shortcoming,
  309. * hence tegra-timer is more preferable on Tegra210.
  310. */
  311. return tegra_init_timer(np, false, 460);
  312. }
  313. TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer);
  314. static int __init tegra20_init_timer(struct device_node *np)
  315. {
  316. int rating;
  317. /*
  318. * Tegra20 and Tegra30 have Cortex A9 CPU that has a TWD timer,
  319. * that timer runs off the CPU clock and hence is subjected to
  320. * a jitter caused by DVFS clock rate changes. Tegra-timer is
  321. * more preferable for older Tegra's, while later SoC generations
  322. * have arch-timer as a main per-CPU timer and it is not affected
  323. * by DVFS changes.
  324. */
  325. if (of_machine_is_compatible("nvidia,tegra20") ||
  326. of_machine_is_compatible("nvidia,tegra30"))
  327. rating = 460;
  328. else
  329. rating = 330;
  330. return tegra_init_timer(np, true, rating);
  331. }
  332. TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
  333. static int __init tegra20_init_rtc(struct device_node *np)
  334. {
  335. int ret;
  336. ret = timer_of_init(np, &suspend_rtc_to);
  337. if (ret)
  338. return ret;
  339. return clocksource_register_hz(&suspend_rtc_clocksource, 1000);
  340. }
  341. TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);