timer-sun5i.c 9.4 KB

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  1. /*
  2. * Allwinner SoCs hstimer driver.
  3. *
  4. * Copyright (C) 2013 Maxime Ripard
  5. *
  6. * Maxime Ripard <maxime.ripard@free-electrons.com>
  7. *
  8. * This file is licensed under the terms of the GNU General Public
  9. * License version 2. This program is licensed "as is" without any
  10. * warranty of any kind, whether express or implied.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/clockchips.h>
  14. #include <linux/clocksource.h>
  15. #include <linux/delay.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/irq.h>
  18. #include <linux/irqreturn.h>
  19. #include <linux/reset.h>
  20. #include <linux/slab.h>
  21. #include <linux/of.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #define TIMER_IRQ_EN_REG 0x00
  25. #define TIMER_IRQ_EN(val) BIT(val)
  26. #define TIMER_IRQ_ST_REG 0x04
  27. #define TIMER_CTL_REG(val) (0x20 * (val) + 0x10)
  28. #define TIMER_CTL_ENABLE BIT(0)
  29. #define TIMER_CTL_RELOAD BIT(1)
  30. #define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
  31. #define TIMER_CTL_ONESHOT BIT(7)
  32. #define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14)
  33. #define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18)
  34. #define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c)
  35. #define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20)
  36. #define TIMER_SYNC_TICKS 3
  37. struct sun5i_timer {
  38. void __iomem *base;
  39. struct clk *clk;
  40. struct notifier_block clk_rate_cb;
  41. u32 ticks_per_jiffy;
  42. };
  43. #define to_sun5i_timer(x) \
  44. container_of(x, struct sun5i_timer, clk_rate_cb)
  45. struct sun5i_timer_clksrc {
  46. struct sun5i_timer timer;
  47. struct clocksource clksrc;
  48. };
  49. #define to_sun5i_timer_clksrc(x) \
  50. container_of(x, struct sun5i_timer_clksrc, clksrc)
  51. struct sun5i_timer_clkevt {
  52. struct sun5i_timer timer;
  53. struct clock_event_device clkevt;
  54. };
  55. #define to_sun5i_timer_clkevt(x) \
  56. container_of(x, struct sun5i_timer_clkevt, clkevt)
  57. /*
  58. * When we disable a timer, we need to wait at least for 2 cycles of
  59. * the timer source clock. We will use for that the clocksource timer
  60. * that is already setup and runs at the same frequency than the other
  61. * timers, and we never will be disabled.
  62. */
  63. static void sun5i_clkevt_sync(struct sun5i_timer_clkevt *ce)
  64. {
  65. u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1));
  66. while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
  67. cpu_relax();
  68. }
  69. static void sun5i_clkevt_time_stop(struct sun5i_timer_clkevt *ce, u8 timer)
  70. {
  71. u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
  72. writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer));
  73. sun5i_clkevt_sync(ce);
  74. }
  75. static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay)
  76. {
  77. writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer));
  78. }
  79. static void sun5i_clkevt_time_start(struct sun5i_timer_clkevt *ce, u8 timer, bool periodic)
  80. {
  81. u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
  82. if (periodic)
  83. val &= ~TIMER_CTL_ONESHOT;
  84. else
  85. val |= TIMER_CTL_ONESHOT;
  86. writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
  87. ce->timer.base + TIMER_CTL_REG(timer));
  88. }
  89. static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt)
  90. {
  91. struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
  92. sun5i_clkevt_time_stop(ce, 0);
  93. return 0;
  94. }
  95. static int sun5i_clkevt_set_oneshot(struct clock_event_device *clkevt)
  96. {
  97. struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
  98. sun5i_clkevt_time_stop(ce, 0);
  99. sun5i_clkevt_time_start(ce, 0, false);
  100. return 0;
  101. }
  102. static int sun5i_clkevt_set_periodic(struct clock_event_device *clkevt)
  103. {
  104. struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
  105. sun5i_clkevt_time_stop(ce, 0);
  106. sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy);
  107. sun5i_clkevt_time_start(ce, 0, true);
  108. return 0;
  109. }
  110. static int sun5i_clkevt_next_event(unsigned long evt,
  111. struct clock_event_device *clkevt)
  112. {
  113. struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
  114. sun5i_clkevt_time_stop(ce, 0);
  115. sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS);
  116. sun5i_clkevt_time_start(ce, 0, false);
  117. return 0;
  118. }
  119. static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
  120. {
  121. struct sun5i_timer_clkevt *ce = (struct sun5i_timer_clkevt *)dev_id;
  122. writel(0x1, ce->timer.base + TIMER_IRQ_ST_REG);
  123. ce->clkevt.event_handler(&ce->clkevt);
  124. return IRQ_HANDLED;
  125. }
  126. static u64 sun5i_clksrc_read(struct clocksource *clksrc)
  127. {
  128. struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc);
  129. return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1));
  130. }
  131. static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
  132. unsigned long event, void *data)
  133. {
  134. struct clk_notifier_data *ndata = data;
  135. struct sun5i_timer *timer = to_sun5i_timer(nb);
  136. struct sun5i_timer_clksrc *cs = container_of(timer, struct sun5i_timer_clksrc, timer);
  137. switch (event) {
  138. case PRE_RATE_CHANGE:
  139. clocksource_unregister(&cs->clksrc);
  140. break;
  141. case POST_RATE_CHANGE:
  142. clocksource_register_hz(&cs->clksrc, ndata->new_rate);
  143. break;
  144. default:
  145. break;
  146. }
  147. return NOTIFY_DONE;
  148. }
  149. static int __init sun5i_setup_clocksource(struct device_node *node,
  150. void __iomem *base,
  151. struct clk *clk, int irq)
  152. {
  153. struct sun5i_timer_clksrc *cs;
  154. unsigned long rate;
  155. int ret;
  156. cs = kzalloc(sizeof(*cs), GFP_KERNEL);
  157. if (!cs)
  158. return -ENOMEM;
  159. ret = clk_prepare_enable(clk);
  160. if (ret) {
  161. pr_err("Couldn't enable parent clock\n");
  162. goto err_free;
  163. }
  164. rate = clk_get_rate(clk);
  165. if (!rate) {
  166. pr_err("Couldn't get parent clock rate\n");
  167. ret = -EINVAL;
  168. goto err_disable_clk;
  169. }
  170. cs->timer.base = base;
  171. cs->timer.clk = clk;
  172. cs->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clksrc;
  173. cs->timer.clk_rate_cb.next = NULL;
  174. ret = clk_notifier_register(clk, &cs->timer.clk_rate_cb);
  175. if (ret) {
  176. pr_err("Unable to register clock notifier.\n");
  177. goto err_disable_clk;
  178. }
  179. writel(~0, base + TIMER_INTVAL_LO_REG(1));
  180. writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
  181. base + TIMER_CTL_REG(1));
  182. cs->clksrc.name = node->name;
  183. cs->clksrc.rating = 340;
  184. cs->clksrc.read = sun5i_clksrc_read;
  185. cs->clksrc.mask = CLOCKSOURCE_MASK(32);
  186. cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
  187. ret = clocksource_register_hz(&cs->clksrc, rate);
  188. if (ret) {
  189. pr_err("Couldn't register clock source.\n");
  190. goto err_remove_notifier;
  191. }
  192. return 0;
  193. err_remove_notifier:
  194. clk_notifier_unregister(clk, &cs->timer.clk_rate_cb);
  195. err_disable_clk:
  196. clk_disable_unprepare(clk);
  197. err_free:
  198. kfree(cs);
  199. return ret;
  200. }
  201. static int sun5i_rate_cb_clkevt(struct notifier_block *nb,
  202. unsigned long event, void *data)
  203. {
  204. struct clk_notifier_data *ndata = data;
  205. struct sun5i_timer *timer = to_sun5i_timer(nb);
  206. struct sun5i_timer_clkevt *ce = container_of(timer, struct sun5i_timer_clkevt, timer);
  207. if (event == POST_RATE_CHANGE) {
  208. clockevents_update_freq(&ce->clkevt, ndata->new_rate);
  209. ce->timer.ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ);
  210. }
  211. return NOTIFY_DONE;
  212. }
  213. static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem *base,
  214. struct clk *clk, int irq)
  215. {
  216. struct sun5i_timer_clkevt *ce;
  217. unsigned long rate;
  218. int ret;
  219. u32 val;
  220. ce = kzalloc(sizeof(*ce), GFP_KERNEL);
  221. if (!ce)
  222. return -ENOMEM;
  223. ret = clk_prepare_enable(clk);
  224. if (ret) {
  225. pr_err("Couldn't enable parent clock\n");
  226. goto err_free;
  227. }
  228. rate = clk_get_rate(clk);
  229. if (!rate) {
  230. pr_err("Couldn't get parent clock rate\n");
  231. ret = -EINVAL;
  232. goto err_disable_clk;
  233. }
  234. ce->timer.base = base;
  235. ce->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
  236. ce->timer.clk = clk;
  237. ce->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clkevt;
  238. ce->timer.clk_rate_cb.next = NULL;
  239. ret = clk_notifier_register(clk, &ce->timer.clk_rate_cb);
  240. if (ret) {
  241. pr_err("Unable to register clock notifier.\n");
  242. goto err_disable_clk;
  243. }
  244. ce->clkevt.name = node->name;
  245. ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
  246. ce->clkevt.set_next_event = sun5i_clkevt_next_event;
  247. ce->clkevt.set_state_shutdown = sun5i_clkevt_shutdown;
  248. ce->clkevt.set_state_periodic = sun5i_clkevt_set_periodic;
  249. ce->clkevt.set_state_oneshot = sun5i_clkevt_set_oneshot;
  250. ce->clkevt.tick_resume = sun5i_clkevt_shutdown;
  251. ce->clkevt.rating = 340;
  252. ce->clkevt.irq = irq;
  253. ce->clkevt.cpumask = cpu_possible_mask;
  254. /* Enable timer0 interrupt */
  255. val = readl(base + TIMER_IRQ_EN_REG);
  256. writel(val | TIMER_IRQ_EN(0), base + TIMER_IRQ_EN_REG);
  257. clockevents_config_and_register(&ce->clkevt, rate,
  258. TIMER_SYNC_TICKS, 0xffffffff);
  259. ret = request_irq(irq, sun5i_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
  260. "sun5i_timer0", ce);
  261. if (ret) {
  262. pr_err("Unable to register interrupt\n");
  263. goto err_remove_notifier;
  264. }
  265. return 0;
  266. err_remove_notifier:
  267. clk_notifier_unregister(clk, &ce->timer.clk_rate_cb);
  268. err_disable_clk:
  269. clk_disable_unprepare(clk);
  270. err_free:
  271. kfree(ce);
  272. return ret;
  273. }
  274. static int __init sun5i_timer_init(struct device_node *node)
  275. {
  276. struct reset_control *rstc;
  277. void __iomem *timer_base;
  278. struct clk *clk;
  279. int irq, ret;
  280. timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
  281. if (IS_ERR(timer_base)) {
  282. pr_err("Can't map registers\n");
  283. return PTR_ERR(timer_base);
  284. }
  285. irq = irq_of_parse_and_map(node, 0);
  286. if (irq <= 0) {
  287. pr_err("Can't parse IRQ\n");
  288. return -EINVAL;
  289. }
  290. clk = of_clk_get(node, 0);
  291. if (IS_ERR(clk)) {
  292. pr_err("Can't get timer clock\n");
  293. return PTR_ERR(clk);
  294. }
  295. rstc = of_reset_control_get(node, NULL);
  296. if (!IS_ERR(rstc))
  297. reset_control_deassert(rstc);
  298. ret = sun5i_setup_clocksource(node, timer_base, clk, irq);
  299. if (ret)
  300. return ret;
  301. return sun5i_setup_clockevent(node, timer_base, clk, irq);
  302. }
  303. TIMER_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
  304. sun5i_timer_init);
  305. TIMER_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
  306. sun5i_timer_init);