timer-sun4i.c 6.2 KB

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  1. /*
  2. * Allwinner A1X SoCs timer handling.
  3. *
  4. * Copyright (C) 2012 Maxime Ripard
  5. *
  6. * Maxime Ripard <maxime.ripard@free-electrons.com>
  7. *
  8. * Based on code from
  9. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  10. * Benn Huang <benn@allwinnertech.com>
  11. *
  12. * This file is licensed under the terms of the GNU General Public
  13. * License version 2. This program is licensed "as is" without any
  14. * warranty of any kind, whether express or implied.
  15. */
  16. #include <linux/clk.h>
  17. #include <linux/clockchips.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/irq.h>
  20. #include <linux/irqreturn.h>
  21. #include <linux/sched_clock.h>
  22. #include <linux/of.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_irq.h>
  25. #include "timer-of.h"
  26. #define TIMER_IRQ_EN_REG 0x00
  27. #define TIMER_IRQ_EN(val) BIT(val)
  28. #define TIMER_IRQ_ST_REG 0x04
  29. #define TIMER_CTL_REG(val) (0x10 * val + 0x10)
  30. #define TIMER_CTL_ENABLE BIT(0)
  31. #define TIMER_CTL_RELOAD BIT(1)
  32. #define TIMER_CTL_CLK_SRC(val) (((val) & 0x3) << 2)
  33. #define TIMER_CTL_CLK_SRC_OSC24M (1)
  34. #define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
  35. #define TIMER_CTL_ONESHOT BIT(7)
  36. #define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14)
  37. #define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
  38. #define TIMER_SYNC_TICKS 3
  39. /*
  40. * When we disable a timer, we need to wait at least for 2 cycles of
  41. * the timer source clock. We will use for that the clocksource timer
  42. * that is already setup and runs at the same frequency than the other
  43. * timers, and we never will be disabled.
  44. */
  45. static void sun4i_clkevt_sync(void __iomem *base)
  46. {
  47. u32 old = readl(base + TIMER_CNTVAL_REG(1));
  48. while ((old - readl(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
  49. cpu_relax();
  50. }
  51. static void sun4i_clkevt_time_stop(void __iomem *base, u8 timer)
  52. {
  53. u32 val = readl(base + TIMER_CTL_REG(timer));
  54. writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer));
  55. sun4i_clkevt_sync(base);
  56. }
  57. static void sun4i_clkevt_time_setup(void __iomem *base, u8 timer,
  58. unsigned long delay)
  59. {
  60. writel(delay, base + TIMER_INTVAL_REG(timer));
  61. }
  62. static void sun4i_clkevt_time_start(void __iomem *base, u8 timer,
  63. bool periodic)
  64. {
  65. u32 val = readl(base + TIMER_CTL_REG(timer));
  66. if (periodic)
  67. val &= ~TIMER_CTL_ONESHOT;
  68. else
  69. val |= TIMER_CTL_ONESHOT;
  70. writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
  71. base + TIMER_CTL_REG(timer));
  72. }
  73. static int sun4i_clkevt_shutdown(struct clock_event_device *evt)
  74. {
  75. struct timer_of *to = to_timer_of(evt);
  76. sun4i_clkevt_time_stop(timer_of_base(to), 0);
  77. return 0;
  78. }
  79. static int sun4i_clkevt_set_oneshot(struct clock_event_device *evt)
  80. {
  81. struct timer_of *to = to_timer_of(evt);
  82. sun4i_clkevt_time_stop(timer_of_base(to), 0);
  83. sun4i_clkevt_time_start(timer_of_base(to), 0, false);
  84. return 0;
  85. }
  86. static int sun4i_clkevt_set_periodic(struct clock_event_device *evt)
  87. {
  88. struct timer_of *to = to_timer_of(evt);
  89. sun4i_clkevt_time_stop(timer_of_base(to), 0);
  90. sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to));
  91. sun4i_clkevt_time_start(timer_of_base(to), 0, true);
  92. return 0;
  93. }
  94. static int sun4i_clkevt_next_event(unsigned long evt,
  95. struct clock_event_device *clkevt)
  96. {
  97. struct timer_of *to = to_timer_of(clkevt);
  98. sun4i_clkevt_time_stop(timer_of_base(to), 0);
  99. sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS);
  100. sun4i_clkevt_time_start(timer_of_base(to), 0, false);
  101. return 0;
  102. }
  103. static void sun4i_timer_clear_interrupt(void __iomem *base)
  104. {
  105. writel(TIMER_IRQ_EN(0), base + TIMER_IRQ_ST_REG);
  106. }
  107. static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
  108. {
  109. struct clock_event_device *evt = (struct clock_event_device *)dev_id;
  110. struct timer_of *to = to_timer_of(evt);
  111. sun4i_timer_clear_interrupt(timer_of_base(to));
  112. evt->event_handler(evt);
  113. return IRQ_HANDLED;
  114. }
  115. static struct timer_of to = {
  116. .flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE,
  117. .clkevt = {
  118. .name = "sun4i_tick",
  119. .rating = 350,
  120. .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  121. .set_state_shutdown = sun4i_clkevt_shutdown,
  122. .set_state_periodic = sun4i_clkevt_set_periodic,
  123. .set_state_oneshot = sun4i_clkevt_set_oneshot,
  124. .tick_resume = sun4i_clkevt_shutdown,
  125. .set_next_event = sun4i_clkevt_next_event,
  126. .cpumask = cpu_possible_mask,
  127. },
  128. .of_irq = {
  129. .handler = sun4i_timer_interrupt,
  130. .flags = IRQF_TIMER | IRQF_IRQPOLL,
  131. },
  132. };
  133. static u64 notrace sun4i_timer_sched_read(void)
  134. {
  135. return ~readl(timer_of_base(&to) + TIMER_CNTVAL_REG(1));
  136. }
  137. static int __init sun4i_timer_init(struct device_node *node)
  138. {
  139. int ret;
  140. u32 val;
  141. ret = timer_of_init(node, &to);
  142. if (ret)
  143. return ret;
  144. writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1));
  145. writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
  146. TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
  147. timer_of_base(&to) + TIMER_CTL_REG(1));
  148. /*
  149. * sched_clock_register does not have priorities, and on sun6i and
  150. * later there is a better sched_clock registered by arm_arch_timer.c
  151. */
  152. if (of_machine_is_compatible("allwinner,sun4i-a10") ||
  153. of_machine_is_compatible("allwinner,sun5i-a13") ||
  154. of_machine_is_compatible("allwinner,sun5i-a10s") ||
  155. of_machine_is_compatible("allwinner,suniv-f1c100s"))
  156. sched_clock_register(sun4i_timer_sched_read, 32,
  157. timer_of_rate(&to));
  158. ret = clocksource_mmio_init(timer_of_base(&to) + TIMER_CNTVAL_REG(1),
  159. node->name, timer_of_rate(&to), 350, 32,
  160. clocksource_mmio_readl_down);
  161. if (ret) {
  162. pr_err("Failed to register clocksource\n");
  163. return ret;
  164. }
  165. writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
  166. timer_of_base(&to) + TIMER_CTL_REG(0));
  167. /* Make sure timer is stopped before playing with interrupts */
  168. sun4i_clkevt_time_stop(timer_of_base(&to), 0);
  169. /* clear timer0 interrupt */
  170. sun4i_timer_clear_interrupt(timer_of_base(&to));
  171. clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
  172. TIMER_SYNC_TICKS, 0xffffffff);
  173. /* Enable timer0 interrupt */
  174. val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG);
  175. writel(val | TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG);
  176. return ret;
  177. }
  178. TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
  179. sun4i_timer_init);
  180. TIMER_OF_DECLARE(sun8i_a23, "allwinner,sun8i-a23-timer",
  181. sun4i_timer_init);
  182. TIMER_OF_DECLARE(sun8i_v3s, "allwinner,sun8i-v3s-timer",
  183. sun4i_timer_init);
  184. TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
  185. sun4i_timer_init);