timer-riscv.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2012 Regents of the University of California
  4. * Copyright (C) 2017 SiFive
  5. *
  6. * All RISC-V systems have a timer attached to every hart. These timers can
  7. * either be read from the "time" and "timeh" CSRs, and can use the SBI to
  8. * setup events, or directly accessed using MMIO registers.
  9. */
  10. #include <linux/clocksource.h>
  11. #include <linux/clockchips.h>
  12. #include <linux/cpu.h>
  13. #include <linux/delay.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/sched_clock.h>
  17. #include <linux/io-64-nonatomic-lo-hi.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/of_irq.h>
  20. #include <asm/smp.h>
  21. #include <asm/sbi.h>
  22. #include <asm/timex.h>
  23. static int riscv_clock_next_event(unsigned long delta,
  24. struct clock_event_device *ce)
  25. {
  26. csr_set(CSR_IE, IE_TIE);
  27. sbi_set_timer(get_cycles64() + delta);
  28. return 0;
  29. }
  30. static unsigned int riscv_clock_event_irq;
  31. static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
  32. .name = "riscv_timer_clockevent",
  33. .features = CLOCK_EVT_FEAT_ONESHOT,
  34. .rating = 100,
  35. .set_next_event = riscv_clock_next_event,
  36. };
  37. /*
  38. * It is guaranteed that all the timers across all the harts are synchronized
  39. * within one tick of each other, so while this could technically go
  40. * backwards when hopping between CPUs, practically it won't happen.
  41. */
  42. static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
  43. {
  44. return get_cycles64();
  45. }
  46. static u64 notrace riscv_sched_clock(void)
  47. {
  48. return get_cycles64();
  49. }
  50. static struct clocksource riscv_clocksource = {
  51. .name = "riscv_clocksource",
  52. .rating = 300,
  53. .mask = CLOCKSOURCE_MASK(64),
  54. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  55. .read = riscv_clocksource_rdtime,
  56. };
  57. static int riscv_timer_starting_cpu(unsigned int cpu)
  58. {
  59. struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
  60. ce->cpumask = cpumask_of(cpu);
  61. ce->irq = riscv_clock_event_irq;
  62. clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
  63. enable_percpu_irq(riscv_clock_event_irq,
  64. irq_get_trigger_type(riscv_clock_event_irq));
  65. return 0;
  66. }
  67. static int riscv_timer_dying_cpu(unsigned int cpu)
  68. {
  69. disable_percpu_irq(riscv_clock_event_irq);
  70. return 0;
  71. }
  72. /* called directly from the low-level interrupt handler */
  73. static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
  74. {
  75. struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
  76. csr_clear(CSR_IE, IE_TIE);
  77. evdev->event_handler(evdev);
  78. return IRQ_HANDLED;
  79. }
  80. static int __init riscv_timer_init_dt(struct device_node *n)
  81. {
  82. int cpuid, hartid, error;
  83. struct device_node *child;
  84. struct irq_domain *domain;
  85. hartid = riscv_of_processor_hartid(n);
  86. if (hartid < 0) {
  87. pr_warn("Not valid hartid for node [%pOF] error = [%d]\n",
  88. n, hartid);
  89. return hartid;
  90. }
  91. cpuid = riscv_hartid_to_cpuid(hartid);
  92. if (cpuid < 0) {
  93. pr_warn("Invalid cpuid for hartid [%d]\n", hartid);
  94. return cpuid;
  95. }
  96. if (cpuid != smp_processor_id())
  97. return 0;
  98. domain = NULL;
  99. child = of_get_compatible_child(n, "riscv,cpu-intc");
  100. if (!child) {
  101. pr_err("Failed to find INTC node [%pOF]\n", n);
  102. return -ENODEV;
  103. }
  104. domain = irq_find_host(child);
  105. of_node_put(child);
  106. if (!domain) {
  107. pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
  108. return -ENODEV;
  109. }
  110. riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
  111. if (!riscv_clock_event_irq) {
  112. pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
  113. return -ENODEV;
  114. }
  115. pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
  116. __func__, cpuid, hartid);
  117. error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
  118. if (error) {
  119. pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
  120. error, cpuid);
  121. return error;
  122. }
  123. sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
  124. error = request_percpu_irq(riscv_clock_event_irq,
  125. riscv_timer_interrupt,
  126. "riscv-timer", &riscv_clock_event);
  127. if (error) {
  128. pr_err("registering percpu irq failed [%d]\n", error);
  129. return error;
  130. }
  131. error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
  132. "clockevents/riscv/timer:starting",
  133. riscv_timer_starting_cpu, riscv_timer_dying_cpu);
  134. if (error)
  135. pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
  136. error);
  137. return error;
  138. }
  139. TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);