timer-oxnas-rps.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * drivers/clocksource/timer-oxnas-rps.c
  4. *
  5. * Copyright (C) 2009 Oxford Semiconductor Ltd
  6. * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
  7. * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
  8. */
  9. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10. #include <linux/init.h>
  11. #include <linux/irq.h>
  12. #include <linux/io.h>
  13. #include <linux/clk.h>
  14. #include <linux/slab.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/of_irq.h>
  17. #include <linux/of_address.h>
  18. #include <linux/clockchips.h>
  19. #include <linux/sched_clock.h>
  20. /* TIMER1 used as tick
  21. * TIMER2 used as clocksource
  22. */
  23. /* Registers definitions */
  24. #define TIMER_LOAD_REG 0x0
  25. #define TIMER_CURR_REG 0x4
  26. #define TIMER_CTRL_REG 0x8
  27. #define TIMER_CLRINT_REG 0xC
  28. #define TIMER_BITS 24
  29. #define TIMER_MAX_VAL (BIT(TIMER_BITS) - 1)
  30. #define TIMER_PERIODIC BIT(6)
  31. #define TIMER_ENABLE BIT(7)
  32. #define TIMER_DIV1 (0)
  33. #define TIMER_DIV16 (1 << 2)
  34. #define TIMER_DIV256 (2 << 2)
  35. #define TIMER1_REG_OFFSET 0
  36. #define TIMER2_REG_OFFSET 0x20
  37. /* Clockevent & Clocksource data */
  38. struct oxnas_rps_timer {
  39. struct clock_event_device clkevent;
  40. void __iomem *clksrc_base;
  41. void __iomem *clkevt_base;
  42. unsigned long timer_period;
  43. unsigned int timer_prescaler;
  44. struct clk *clk;
  45. int irq;
  46. };
  47. static irqreturn_t oxnas_rps_timer_irq(int irq, void *dev_id)
  48. {
  49. struct oxnas_rps_timer *rps = dev_id;
  50. writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG);
  51. rps->clkevent.event_handler(&rps->clkevent);
  52. return IRQ_HANDLED;
  53. }
  54. static void oxnas_rps_timer_config(struct oxnas_rps_timer *rps,
  55. unsigned long period,
  56. unsigned int periodic)
  57. {
  58. uint32_t cfg = rps->timer_prescaler;
  59. if (period)
  60. cfg |= TIMER_ENABLE;
  61. if (periodic)
  62. cfg |= TIMER_PERIODIC;
  63. writel_relaxed(period, rps->clkevt_base + TIMER_LOAD_REG);
  64. writel_relaxed(cfg, rps->clkevt_base + TIMER_CTRL_REG);
  65. }
  66. static int oxnas_rps_timer_shutdown(struct clock_event_device *evt)
  67. {
  68. struct oxnas_rps_timer *rps =
  69. container_of(evt, struct oxnas_rps_timer, clkevent);
  70. oxnas_rps_timer_config(rps, 0, 0);
  71. return 0;
  72. }
  73. static int oxnas_rps_timer_set_periodic(struct clock_event_device *evt)
  74. {
  75. struct oxnas_rps_timer *rps =
  76. container_of(evt, struct oxnas_rps_timer, clkevent);
  77. oxnas_rps_timer_config(rps, rps->timer_period, 1);
  78. return 0;
  79. }
  80. static int oxnas_rps_timer_set_oneshot(struct clock_event_device *evt)
  81. {
  82. struct oxnas_rps_timer *rps =
  83. container_of(evt, struct oxnas_rps_timer, clkevent);
  84. oxnas_rps_timer_config(rps, rps->timer_period, 0);
  85. return 0;
  86. }
  87. static int oxnas_rps_timer_next_event(unsigned long delta,
  88. struct clock_event_device *evt)
  89. {
  90. struct oxnas_rps_timer *rps =
  91. container_of(evt, struct oxnas_rps_timer, clkevent);
  92. oxnas_rps_timer_config(rps, delta, 0);
  93. return 0;
  94. }
  95. static int __init oxnas_rps_clockevent_init(struct oxnas_rps_timer *rps)
  96. {
  97. ulong clk_rate = clk_get_rate(rps->clk);
  98. ulong timer_rate;
  99. /* Start with prescaler 1 */
  100. rps->timer_prescaler = TIMER_DIV1;
  101. rps->timer_period = DIV_ROUND_UP(clk_rate, HZ);
  102. timer_rate = clk_rate;
  103. if (rps->timer_period > TIMER_MAX_VAL) {
  104. rps->timer_prescaler = TIMER_DIV16;
  105. timer_rate = clk_rate / 16;
  106. rps->timer_period = DIV_ROUND_UP(timer_rate, HZ);
  107. }
  108. if (rps->timer_period > TIMER_MAX_VAL) {
  109. rps->timer_prescaler = TIMER_DIV256;
  110. timer_rate = clk_rate / 256;
  111. rps->timer_period = DIV_ROUND_UP(timer_rate, HZ);
  112. }
  113. rps->clkevent.name = "oxnas-rps";
  114. rps->clkevent.features = CLOCK_EVT_FEAT_PERIODIC |
  115. CLOCK_EVT_FEAT_ONESHOT |
  116. CLOCK_EVT_FEAT_DYNIRQ;
  117. rps->clkevent.tick_resume = oxnas_rps_timer_shutdown;
  118. rps->clkevent.set_state_shutdown = oxnas_rps_timer_shutdown;
  119. rps->clkevent.set_state_periodic = oxnas_rps_timer_set_periodic;
  120. rps->clkevent.set_state_oneshot = oxnas_rps_timer_set_oneshot;
  121. rps->clkevent.set_next_event = oxnas_rps_timer_next_event;
  122. rps->clkevent.rating = 200;
  123. rps->clkevent.cpumask = cpu_possible_mask;
  124. rps->clkevent.irq = rps->irq;
  125. clockevents_config_and_register(&rps->clkevent,
  126. timer_rate,
  127. 1,
  128. TIMER_MAX_VAL);
  129. pr_info("Registered clock event rate %luHz prescaler %x period %lu\n",
  130. clk_rate,
  131. rps->timer_prescaler,
  132. rps->timer_period);
  133. return 0;
  134. }
  135. /* Clocksource */
  136. static void __iomem *timer_sched_base;
  137. static u64 notrace oxnas_rps_read_sched_clock(void)
  138. {
  139. return ~readl_relaxed(timer_sched_base);
  140. }
  141. static int __init oxnas_rps_clocksource_init(struct oxnas_rps_timer *rps)
  142. {
  143. ulong clk_rate = clk_get_rate(rps->clk);
  144. int ret;
  145. /* use prescale 16 */
  146. clk_rate = clk_rate / 16;
  147. writel_relaxed(TIMER_MAX_VAL, rps->clksrc_base + TIMER_LOAD_REG);
  148. writel_relaxed(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16,
  149. rps->clksrc_base + TIMER_CTRL_REG);
  150. timer_sched_base = rps->clksrc_base + TIMER_CURR_REG;
  151. sched_clock_register(oxnas_rps_read_sched_clock,
  152. TIMER_BITS, clk_rate);
  153. ret = clocksource_mmio_init(timer_sched_base,
  154. "oxnas_rps_clocksource_timer",
  155. clk_rate, 250, TIMER_BITS,
  156. clocksource_mmio_readl_down);
  157. if (WARN_ON(ret)) {
  158. pr_err("can't register clocksource\n");
  159. return ret;
  160. }
  161. pr_info("Registered clocksource rate %luHz\n", clk_rate);
  162. return 0;
  163. }
  164. static int __init oxnas_rps_timer_init(struct device_node *np)
  165. {
  166. struct oxnas_rps_timer *rps;
  167. void __iomem *base;
  168. int ret;
  169. rps = kzalloc(sizeof(*rps), GFP_KERNEL);
  170. if (!rps)
  171. return -ENOMEM;
  172. rps->clk = of_clk_get(np, 0);
  173. if (IS_ERR(rps->clk)) {
  174. ret = PTR_ERR(rps->clk);
  175. goto err_alloc;
  176. }
  177. ret = clk_prepare_enable(rps->clk);
  178. if (ret)
  179. goto err_clk;
  180. base = of_iomap(np, 0);
  181. if (!base) {
  182. ret = -ENXIO;
  183. goto err_clk_prepare;
  184. }
  185. rps->irq = irq_of_parse_and_map(np, 0);
  186. if (rps->irq < 0) {
  187. ret = -EINVAL;
  188. goto err_iomap;
  189. }
  190. rps->clkevt_base = base + TIMER1_REG_OFFSET;
  191. rps->clksrc_base = base + TIMER2_REG_OFFSET;
  192. /* Disable timers */
  193. writel_relaxed(0, rps->clkevt_base + TIMER_CTRL_REG);
  194. writel_relaxed(0, rps->clksrc_base + TIMER_CTRL_REG);
  195. writel_relaxed(0, rps->clkevt_base + TIMER_LOAD_REG);
  196. writel_relaxed(0, rps->clksrc_base + TIMER_LOAD_REG);
  197. writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG);
  198. writel_relaxed(0, rps->clksrc_base + TIMER_CLRINT_REG);
  199. ret = request_irq(rps->irq, oxnas_rps_timer_irq,
  200. IRQF_TIMER | IRQF_IRQPOLL,
  201. "rps-timer", rps);
  202. if (ret)
  203. goto err_iomap;
  204. ret = oxnas_rps_clocksource_init(rps);
  205. if (ret)
  206. goto err_irqreq;
  207. ret = oxnas_rps_clockevent_init(rps);
  208. if (ret)
  209. goto err_irqreq;
  210. return 0;
  211. err_irqreq:
  212. free_irq(rps->irq, rps);
  213. err_iomap:
  214. iounmap(base);
  215. err_clk_prepare:
  216. clk_disable_unprepare(rps->clk);
  217. err_clk:
  218. clk_put(rps->clk);
  219. err_alloc:
  220. kfree(rps);
  221. return ret;
  222. }
  223. TIMER_OF_DECLARE(ox810se_rps,
  224. "oxsemi,ox810se-rps-timer", oxnas_rps_timer_init);
  225. TIMER_OF_DECLARE(ox820_rps,
  226. "oxsemi,ox820-rps-timer", oxnas_rps_timer_init);