timer-owl.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Actions Semi Owl timer
  4. *
  5. * Copyright 2012 Actions Semi Inc.
  6. * Author: Actions Semi, Inc.
  7. *
  8. * Copyright (c) 2017 SUSE Linux GmbH
  9. * Author: Andreas Färber
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/clockchips.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqreturn.h>
  16. #include <linux/sched_clock.h>
  17. #include <linux/of.h>
  18. #include <linux/of_address.h>
  19. #include <linux/of_irq.h>
  20. #define OWL_Tx_CTL 0x0
  21. #define OWL_Tx_CMP 0x4
  22. #define OWL_Tx_VAL 0x8
  23. #define OWL_Tx_CTL_PD BIT(0)
  24. #define OWL_Tx_CTL_INTEN BIT(1)
  25. #define OWL_Tx_CTL_EN BIT(2)
  26. static void __iomem *owl_timer_base;
  27. static void __iomem *owl_clksrc_base;
  28. static void __iomem *owl_clkevt_base;
  29. static inline void owl_timer_reset(void __iomem *base)
  30. {
  31. writel(0, base + OWL_Tx_CTL);
  32. writel(0, base + OWL_Tx_VAL);
  33. writel(0, base + OWL_Tx_CMP);
  34. }
  35. static inline void owl_timer_set_enabled(void __iomem *base, bool enabled)
  36. {
  37. u32 ctl = readl(base + OWL_Tx_CTL);
  38. /* PD bit is cleared when set */
  39. ctl &= ~OWL_Tx_CTL_PD;
  40. if (enabled)
  41. ctl |= OWL_Tx_CTL_EN;
  42. else
  43. ctl &= ~OWL_Tx_CTL_EN;
  44. writel(ctl, base + OWL_Tx_CTL);
  45. }
  46. static u64 notrace owl_timer_sched_read(void)
  47. {
  48. return (u64)readl(owl_clksrc_base + OWL_Tx_VAL);
  49. }
  50. static int owl_timer_set_state_shutdown(struct clock_event_device *evt)
  51. {
  52. owl_timer_set_enabled(owl_clkevt_base, false);
  53. return 0;
  54. }
  55. static int owl_timer_set_state_oneshot(struct clock_event_device *evt)
  56. {
  57. owl_timer_reset(owl_clkevt_base);
  58. return 0;
  59. }
  60. static int owl_timer_tick_resume(struct clock_event_device *evt)
  61. {
  62. return 0;
  63. }
  64. static int owl_timer_set_next_event(unsigned long evt,
  65. struct clock_event_device *ev)
  66. {
  67. void __iomem *base = owl_clkevt_base;
  68. owl_timer_set_enabled(base, false);
  69. writel(OWL_Tx_CTL_INTEN, base + OWL_Tx_CTL);
  70. writel(0, base + OWL_Tx_VAL);
  71. writel(evt, base + OWL_Tx_CMP);
  72. owl_timer_set_enabled(base, true);
  73. return 0;
  74. }
  75. static struct clock_event_device owl_clockevent = {
  76. .name = "owl_tick",
  77. .rating = 200,
  78. .features = CLOCK_EVT_FEAT_ONESHOT |
  79. CLOCK_EVT_FEAT_DYNIRQ,
  80. .set_state_shutdown = owl_timer_set_state_shutdown,
  81. .set_state_oneshot = owl_timer_set_state_oneshot,
  82. .tick_resume = owl_timer_tick_resume,
  83. .set_next_event = owl_timer_set_next_event,
  84. };
  85. static irqreturn_t owl_timer1_interrupt(int irq, void *dev_id)
  86. {
  87. struct clock_event_device *evt = (struct clock_event_device *)dev_id;
  88. writel(OWL_Tx_CTL_PD, owl_clkevt_base + OWL_Tx_CTL);
  89. evt->event_handler(evt);
  90. return IRQ_HANDLED;
  91. }
  92. static int __init owl_timer_init(struct device_node *node)
  93. {
  94. struct clk *clk;
  95. unsigned long rate;
  96. int timer1_irq, ret;
  97. owl_timer_base = of_io_request_and_map(node, 0, "owl-timer");
  98. if (IS_ERR(owl_timer_base)) {
  99. pr_err("Can't map timer registers\n");
  100. return PTR_ERR(owl_timer_base);
  101. }
  102. owl_clksrc_base = owl_timer_base + 0x08;
  103. owl_clkevt_base = owl_timer_base + 0x14;
  104. timer1_irq = of_irq_get_byname(node, "timer1");
  105. if (timer1_irq <= 0) {
  106. pr_err("Can't parse timer1 IRQ\n");
  107. return -EINVAL;
  108. }
  109. clk = of_clk_get(node, 0);
  110. if (IS_ERR(clk)) {
  111. ret = PTR_ERR(clk);
  112. pr_err("Failed to get clock for clocksource (%d)\n", ret);
  113. return ret;
  114. }
  115. rate = clk_get_rate(clk);
  116. owl_timer_reset(owl_clksrc_base);
  117. owl_timer_set_enabled(owl_clksrc_base, true);
  118. sched_clock_register(owl_timer_sched_read, 32, rate);
  119. ret = clocksource_mmio_init(owl_clksrc_base + OWL_Tx_VAL, node->name,
  120. rate, 200, 32, clocksource_mmio_readl_up);
  121. if (ret) {
  122. pr_err("Failed to register clocksource (%d)\n", ret);
  123. return ret;
  124. }
  125. owl_timer_reset(owl_clkevt_base);
  126. ret = request_irq(timer1_irq, owl_timer1_interrupt, IRQF_TIMER,
  127. "owl-timer", &owl_clockevent);
  128. if (ret) {
  129. pr_err("failed to request irq %d\n", timer1_irq);
  130. return ret;
  131. }
  132. owl_clockevent.cpumask = cpumask_of(0);
  133. owl_clockevent.irq = timer1_irq;
  134. clockevents_config_and_register(&owl_clockevent, rate,
  135. 0xf, 0xffffffff);
  136. return 0;
  137. }
  138. TIMER_OF_DECLARE(owl_s500, "actions,s500-timer", owl_timer_init);
  139. TIMER_OF_DECLARE(owl_s700, "actions,s700-timer", owl_timer_init);
  140. TIMER_OF_DECLARE(owl_s900, "actions,s900-timer", owl_timer_init);