timer-mediatek.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Mediatek SoCs General-Purpose Timer handling.
  4. *
  5. * Copyright (C) 2014 Matthias Brugger
  6. *
  7. * Matthias Brugger <matthias.bgg@gmail.com>
  8. */
  9. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10. #include <linux/clockchips.h>
  11. #include <linux/clocksource.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/irqreturn.h>
  14. #include <linux/sched_clock.h>
  15. #include <linux/slab.h>
  16. #include "timer-of.h"
  17. #define TIMER_CLK_EVT (1)
  18. #define TIMER_CLK_SRC (2)
  19. #define TIMER_SYNC_TICKS (3)
  20. /* gpt */
  21. #define GPT_IRQ_EN_REG 0x00
  22. #define GPT_IRQ_ENABLE(val) BIT((val) - 1)
  23. #define GPT_IRQ_ACK_REG 0x08
  24. #define GPT_IRQ_ACK(val) BIT((val) - 1)
  25. #define GPT_CTRL_REG(val) (0x10 * (val))
  26. #define GPT_CTRL_OP(val) (((val) & 0x3) << 4)
  27. #define GPT_CTRL_OP_ONESHOT (0)
  28. #define GPT_CTRL_OP_REPEAT (1)
  29. #define GPT_CTRL_OP_FREERUN (3)
  30. #define GPT_CTRL_CLEAR (2)
  31. #define GPT_CTRL_ENABLE (1)
  32. #define GPT_CTRL_DISABLE (0)
  33. #define GPT_CLK_REG(val) (0x04 + (0x10 * (val)))
  34. #define GPT_CLK_SRC(val) (((val) & 0x1) << 4)
  35. #define GPT_CLK_SRC_SYS13M (0)
  36. #define GPT_CLK_SRC_RTC32K (1)
  37. #define GPT_CLK_DIV1 (0x0)
  38. #define GPT_CLK_DIV2 (0x1)
  39. #define GPT_CNT_REG(val) (0x08 + (0x10 * (val)))
  40. #define GPT_CMP_REG(val) (0x0C + (0x10 * (val)))
  41. /* system timer */
  42. #define SYST_BASE (0x40)
  43. #define SYST_CON (SYST_BASE + 0x0)
  44. #define SYST_VAL (SYST_BASE + 0x4)
  45. #define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON)
  46. #define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL)
  47. /*
  48. * SYST_CON_EN: Clock enable. Shall be set to
  49. * - Start timer countdown.
  50. * - Allow timeout ticks being updated.
  51. * - Allow changing interrupt functions.
  52. *
  53. * SYST_CON_IRQ_EN: Set to allow interrupt.
  54. *
  55. * SYST_CON_IRQ_CLR: Set to clear interrupt.
  56. */
  57. #define SYST_CON_EN BIT(0)
  58. #define SYST_CON_IRQ_EN BIT(1)
  59. #define SYST_CON_IRQ_CLR BIT(4)
  60. static void __iomem *gpt_sched_reg __read_mostly;
  61. static void mtk_syst_ack_irq(struct timer_of *to)
  62. {
  63. /* Clear and disable interrupt */
  64. writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to));
  65. }
  66. static irqreturn_t mtk_syst_handler(int irq, void *dev_id)
  67. {
  68. struct clock_event_device *clkevt = dev_id;
  69. struct timer_of *to = to_timer_of(clkevt);
  70. mtk_syst_ack_irq(to);
  71. clkevt->event_handler(clkevt);
  72. return IRQ_HANDLED;
  73. }
  74. static int mtk_syst_clkevt_next_event(unsigned long ticks,
  75. struct clock_event_device *clkevt)
  76. {
  77. struct timer_of *to = to_timer_of(clkevt);
  78. /* Enable clock to allow timeout tick update later */
  79. writel(SYST_CON_EN, SYST_CON_REG(to));
  80. /*
  81. * Write new timeout ticks. Timer shall start countdown
  82. * after timeout ticks are updated.
  83. */
  84. writel(ticks, SYST_VAL_REG(to));
  85. /* Enable interrupt */
  86. writel(SYST_CON_EN | SYST_CON_IRQ_EN, SYST_CON_REG(to));
  87. return 0;
  88. }
  89. static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt)
  90. {
  91. /* Disable timer */
  92. writel(0, SYST_CON_REG(to_timer_of(clkevt)));
  93. return 0;
  94. }
  95. static int mtk_syst_clkevt_resume(struct clock_event_device *clkevt)
  96. {
  97. return mtk_syst_clkevt_shutdown(clkevt);
  98. }
  99. static int mtk_syst_clkevt_oneshot(struct clock_event_device *clkevt)
  100. {
  101. return 0;
  102. }
  103. static u64 notrace mtk_gpt_read_sched_clock(void)
  104. {
  105. return readl_relaxed(gpt_sched_reg);
  106. }
  107. static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer)
  108. {
  109. u32 val;
  110. val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
  111. writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
  112. GPT_CTRL_REG(timer));
  113. }
  114. static void mtk_gpt_clkevt_time_setup(struct timer_of *to,
  115. unsigned long delay, u8 timer)
  116. {
  117. writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
  118. }
  119. static void mtk_gpt_clkevt_time_start(struct timer_of *to,
  120. bool periodic, u8 timer)
  121. {
  122. u32 val;
  123. /* Acknowledge interrupt */
  124. writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);
  125. val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
  126. /* Clear 2 bit timer operation mode field */
  127. val &= ~GPT_CTRL_OP(0x3);
  128. if (periodic)
  129. val |= GPT_CTRL_OP(GPT_CTRL_OP_REPEAT);
  130. else
  131. val |= GPT_CTRL_OP(GPT_CTRL_OP_ONESHOT);
  132. writel(val | GPT_CTRL_ENABLE | GPT_CTRL_CLEAR,
  133. timer_of_base(to) + GPT_CTRL_REG(timer));
  134. }
  135. static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk)
  136. {
  137. mtk_gpt_clkevt_time_stop(to_timer_of(clk), TIMER_CLK_EVT);
  138. return 0;
  139. }
  140. static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk)
  141. {
  142. struct timer_of *to = to_timer_of(clk);
  143. mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
  144. mtk_gpt_clkevt_time_setup(to, to->of_clk.period, TIMER_CLK_EVT);
  145. mtk_gpt_clkevt_time_start(to, true, TIMER_CLK_EVT);
  146. return 0;
  147. }
  148. static int mtk_gpt_clkevt_next_event(unsigned long event,
  149. struct clock_event_device *clk)
  150. {
  151. struct timer_of *to = to_timer_of(clk);
  152. mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
  153. mtk_gpt_clkevt_time_setup(to, event, TIMER_CLK_EVT);
  154. mtk_gpt_clkevt_time_start(to, false, TIMER_CLK_EVT);
  155. return 0;
  156. }
  157. static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id)
  158. {
  159. struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
  160. struct timer_of *to = to_timer_of(clkevt);
  161. /* Acknowledge timer0 irq */
  162. writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
  163. clkevt->event_handler(clkevt);
  164. return IRQ_HANDLED;
  165. }
  166. static void
  167. __init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option)
  168. {
  169. writel(GPT_CTRL_CLEAR | GPT_CTRL_DISABLE,
  170. timer_of_base(to) + GPT_CTRL_REG(timer));
  171. writel(GPT_CLK_SRC(GPT_CLK_SRC_SYS13M) | GPT_CLK_DIV1,
  172. timer_of_base(to) + GPT_CLK_REG(timer));
  173. writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));
  174. writel(GPT_CTRL_OP(option) | GPT_CTRL_ENABLE,
  175. timer_of_base(to) + GPT_CTRL_REG(timer));
  176. }
  177. static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
  178. {
  179. u32 val;
  180. /* Disable all interrupts */
  181. writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
  182. /* Acknowledge all spurious pending interrupts */
  183. writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
  184. val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);
  185. writel(val | GPT_IRQ_ENABLE(timer),
  186. timer_of_base(to) + GPT_IRQ_EN_REG);
  187. }
  188. static struct timer_of to = {
  189. .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
  190. .clkevt = {
  191. .name = "mtk-clkevt",
  192. .rating = 300,
  193. .cpumask = cpu_possible_mask,
  194. },
  195. .of_irq = {
  196. .flags = IRQF_TIMER | IRQF_IRQPOLL,
  197. },
  198. };
  199. static int __init mtk_syst_init(struct device_node *node)
  200. {
  201. int ret;
  202. to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT;
  203. to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown;
  204. to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot;
  205. to.clkevt.tick_resume = mtk_syst_clkevt_resume;
  206. to.clkevt.set_next_event = mtk_syst_clkevt_next_event;
  207. to.of_irq.handler = mtk_syst_handler;
  208. ret = timer_of_init(node, &to);
  209. if (ret)
  210. return ret;
  211. clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
  212. TIMER_SYNC_TICKS, 0xffffffff);
  213. return 0;
  214. }
  215. static int __init mtk_gpt_init(struct device_node *node)
  216. {
  217. int ret;
  218. to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
  219. to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown;
  220. to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic;
  221. to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown;
  222. to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown;
  223. to.clkevt.set_next_event = mtk_gpt_clkevt_next_event;
  224. to.of_irq.handler = mtk_gpt_interrupt;
  225. ret = timer_of_init(node, &to);
  226. if (ret)
  227. return ret;
  228. /* Configure clock source */
  229. mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN);
  230. clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),
  231. node->name, timer_of_rate(&to), 300, 32,
  232. clocksource_mmio_readl_up);
  233. gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);
  234. sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to));
  235. /* Configure clock event */
  236. mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT);
  237. clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
  238. TIMER_SYNC_TICKS, 0xffffffff);
  239. mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);
  240. return 0;
  241. }
  242. TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);
  243. TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init);