timer-cadence-ttc.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * This file contains driver for the Cadence Triple Timer Counter Rev 06
  4. *
  5. * Copyright (C) 2011-2013 Xilinx
  6. *
  7. * based on arch/mips/kernel/time.c timer driver
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/clockchips.h>
  12. #include <linux/clocksource.h>
  13. #include <linux/of_address.h>
  14. #include <linux/of_irq.h>
  15. #include <linux/slab.h>
  16. #include <linux/sched_clock.h>
  17. #include <linux/module.h>
  18. #include <linux/of_platform.h>
  19. /*
  20. * This driver configures the 2 16/32-bit count-up timers as follows:
  21. *
  22. * T1: Timer 1, clocksource for generic timekeeping
  23. * T2: Timer 2, clockevent source for hrtimers
  24. * T3: Timer 3, <unused>
  25. *
  26. * The input frequency to the timer module for emulation is 2.5MHz which is
  27. * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
  28. * the timers are clocked at 78.125KHz (12.8 us resolution).
  29. * The input frequency to the timer module in silicon is configurable and
  30. * obtained from device tree. The pre-scaler of 32 is used.
  31. */
  32. /*
  33. * Timer Register Offset Definitions of Timer 1, Increment base address by 4
  34. * and use same offsets for Timer 2
  35. */
  36. #define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
  37. #define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
  38. #define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
  39. #define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
  40. #define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
  41. #define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
  42. #define TTC_CNT_CNTRL_DISABLE_MASK 0x1
  43. #define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
  44. #define TTC_CLK_CNTRL_PSV_MASK 0x1e
  45. #define TTC_CLK_CNTRL_PSV_SHIFT 1
  46. /*
  47. * Setup the timers to use pre-scaling, using a fixed value for now that will
  48. * work across most input frequency, but it may need to be more dynamic
  49. */
  50. #define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
  51. #define PRESCALE 2048 /* The exponent must match this */
  52. #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
  53. #define CLK_CNTRL_PRESCALE_EN 1
  54. #define CNT_CNTRL_RESET (1 << 4)
  55. #define MAX_F_ERR 50
  56. /**
  57. * struct ttc_timer - This definition defines local timer structure
  58. *
  59. * @base_addr: Base address of timer
  60. * @freq: Timer input clock frequency
  61. * @clk: Associated clock source
  62. * @clk_rate_change_nb Notifier block for clock rate changes
  63. */
  64. struct ttc_timer {
  65. void __iomem *base_addr;
  66. unsigned long freq;
  67. struct clk *clk;
  68. struct notifier_block clk_rate_change_nb;
  69. };
  70. #define to_ttc_timer(x) \
  71. container_of(x, struct ttc_timer, clk_rate_change_nb)
  72. struct ttc_timer_clocksource {
  73. u32 scale_clk_ctrl_reg_old;
  74. u32 scale_clk_ctrl_reg_new;
  75. struct ttc_timer ttc;
  76. struct clocksource cs;
  77. };
  78. #define to_ttc_timer_clksrc(x) \
  79. container_of(x, struct ttc_timer_clocksource, cs)
  80. struct ttc_timer_clockevent {
  81. struct ttc_timer ttc;
  82. struct clock_event_device ce;
  83. };
  84. #define to_ttc_timer_clkevent(x) \
  85. container_of(x, struct ttc_timer_clockevent, ce)
  86. static void __iomem *ttc_sched_clock_val_reg;
  87. /**
  88. * ttc_set_interval - Set the timer interval value
  89. *
  90. * @timer: Pointer to the timer instance
  91. * @cycles: Timer interval ticks
  92. **/
  93. static void ttc_set_interval(struct ttc_timer *timer,
  94. unsigned long cycles)
  95. {
  96. u32 ctrl_reg;
  97. /* Disable the counter, set the counter value and re-enable counter */
  98. ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
  99. ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
  100. writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
  101. writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
  102. /*
  103. * Reset the counter (0x10) so that it starts from 0, one-shot
  104. * mode makes this needed for timing to be right.
  105. */
  106. ctrl_reg |= CNT_CNTRL_RESET;
  107. ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
  108. writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
  109. }
  110. /**
  111. * ttc_clock_event_interrupt - Clock event timer interrupt handler
  112. *
  113. * @irq: IRQ number of the Timer
  114. * @dev_id: void pointer to the ttc_timer instance
  115. *
  116. * returns: Always IRQ_HANDLED - success
  117. **/
  118. static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
  119. {
  120. struct ttc_timer_clockevent *ttce = dev_id;
  121. struct ttc_timer *timer = &ttce->ttc;
  122. /* Acknowledge the interrupt and call event handler */
  123. readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
  124. ttce->ce.event_handler(&ttce->ce);
  125. return IRQ_HANDLED;
  126. }
  127. /**
  128. * __ttc_clocksource_read - Reads the timer counter register
  129. *
  130. * returns: Current timer counter register value
  131. **/
  132. static u64 __ttc_clocksource_read(struct clocksource *cs)
  133. {
  134. struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
  135. return (u64)readl_relaxed(timer->base_addr +
  136. TTC_COUNT_VAL_OFFSET);
  137. }
  138. static u64 notrace ttc_sched_clock_read(void)
  139. {
  140. return readl_relaxed(ttc_sched_clock_val_reg);
  141. }
  142. /**
  143. * ttc_set_next_event - Sets the time interval for next event
  144. *
  145. * @cycles: Timer interval ticks
  146. * @evt: Address of clock event instance
  147. *
  148. * returns: Always 0 - success
  149. **/
  150. static int ttc_set_next_event(unsigned long cycles,
  151. struct clock_event_device *evt)
  152. {
  153. struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
  154. struct ttc_timer *timer = &ttce->ttc;
  155. ttc_set_interval(timer, cycles);
  156. return 0;
  157. }
  158. /**
  159. * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer
  160. *
  161. * @evt: Address of clock event instance
  162. **/
  163. static int ttc_shutdown(struct clock_event_device *evt)
  164. {
  165. struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
  166. struct ttc_timer *timer = &ttce->ttc;
  167. u32 ctrl_reg;
  168. ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
  169. ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
  170. writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
  171. return 0;
  172. }
  173. static int ttc_set_periodic(struct clock_event_device *evt)
  174. {
  175. struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
  176. struct ttc_timer *timer = &ttce->ttc;
  177. ttc_set_interval(timer,
  178. DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ));
  179. return 0;
  180. }
  181. static int ttc_resume(struct clock_event_device *evt)
  182. {
  183. struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
  184. struct ttc_timer *timer = &ttce->ttc;
  185. u32 ctrl_reg;
  186. ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
  187. ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
  188. writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
  189. return 0;
  190. }
  191. static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
  192. unsigned long event, void *data)
  193. {
  194. struct clk_notifier_data *ndata = data;
  195. struct ttc_timer *ttc = to_ttc_timer(nb);
  196. struct ttc_timer_clocksource *ttccs = container_of(ttc,
  197. struct ttc_timer_clocksource, ttc);
  198. switch (event) {
  199. case PRE_RATE_CHANGE:
  200. {
  201. u32 psv;
  202. unsigned long factor, rate_low, rate_high;
  203. if (ndata->new_rate > ndata->old_rate) {
  204. factor = DIV_ROUND_CLOSEST(ndata->new_rate,
  205. ndata->old_rate);
  206. rate_low = ndata->old_rate;
  207. rate_high = ndata->new_rate;
  208. } else {
  209. factor = DIV_ROUND_CLOSEST(ndata->old_rate,
  210. ndata->new_rate);
  211. rate_low = ndata->new_rate;
  212. rate_high = ndata->old_rate;
  213. }
  214. if (!is_power_of_2(factor))
  215. return NOTIFY_BAD;
  216. if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
  217. return NOTIFY_BAD;
  218. factor = __ilog2_u32(factor);
  219. /*
  220. * store timer clock ctrl register so we can restore it in case
  221. * of an abort.
  222. */
  223. ttccs->scale_clk_ctrl_reg_old =
  224. readl_relaxed(ttccs->ttc.base_addr +
  225. TTC_CLK_CNTRL_OFFSET);
  226. psv = (ttccs->scale_clk_ctrl_reg_old &
  227. TTC_CLK_CNTRL_PSV_MASK) >>
  228. TTC_CLK_CNTRL_PSV_SHIFT;
  229. if (ndata->new_rate < ndata->old_rate)
  230. psv -= factor;
  231. else
  232. psv += factor;
  233. /* prescaler within legal range? */
  234. if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
  235. return NOTIFY_BAD;
  236. ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
  237. ~TTC_CLK_CNTRL_PSV_MASK;
  238. ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;
  239. /* scale down: adjust divider in post-change notification */
  240. if (ndata->new_rate < ndata->old_rate)
  241. return NOTIFY_DONE;
  242. /* scale up: adjust divider now - before frequency change */
  243. writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
  244. ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
  245. break;
  246. }
  247. case POST_RATE_CHANGE:
  248. /* scale up: pre-change notification did the adjustment */
  249. if (ndata->new_rate > ndata->old_rate)
  250. return NOTIFY_OK;
  251. /* scale down: adjust divider now - after frequency change */
  252. writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
  253. ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
  254. break;
  255. case ABORT_RATE_CHANGE:
  256. /* we have to undo the adjustment in case we scale up */
  257. if (ndata->new_rate < ndata->old_rate)
  258. return NOTIFY_OK;
  259. /* restore original register value */
  260. writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
  261. ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
  262. fallthrough;
  263. default:
  264. return NOTIFY_DONE;
  265. }
  266. return NOTIFY_DONE;
  267. }
  268. static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,
  269. u32 timer_width)
  270. {
  271. struct ttc_timer_clocksource *ttccs;
  272. int err;
  273. ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
  274. if (!ttccs)
  275. return -ENOMEM;
  276. ttccs->ttc.clk = clk;
  277. err = clk_prepare_enable(ttccs->ttc.clk);
  278. if (err) {
  279. kfree(ttccs);
  280. return err;
  281. }
  282. ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
  283. ttccs->ttc.clk_rate_change_nb.notifier_call =
  284. ttc_rate_change_clocksource_cb;
  285. ttccs->ttc.clk_rate_change_nb.next = NULL;
  286. err = clk_notifier_register(ttccs->ttc.clk,
  287. &ttccs->ttc.clk_rate_change_nb);
  288. if (err)
  289. pr_warn("Unable to register clock notifier.\n");
  290. ttccs->ttc.base_addr = base;
  291. ttccs->cs.name = "ttc_clocksource";
  292. ttccs->cs.rating = 200;
  293. ttccs->cs.read = __ttc_clocksource_read;
  294. ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
  295. ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
  296. /*
  297. * Setup the clock source counter to be an incrementing counter
  298. * with no interrupt and it rolls over at 0xFFFF. Pre-scale
  299. * it by 32 also. Let it start running now.
  300. */
  301. writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
  302. writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
  303. ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
  304. writel_relaxed(CNT_CNTRL_RESET,
  305. ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
  306. err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
  307. if (err) {
  308. kfree(ttccs);
  309. return err;
  310. }
  311. ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
  312. sched_clock_register(ttc_sched_clock_read, timer_width,
  313. ttccs->ttc.freq / PRESCALE);
  314. return 0;
  315. }
  316. static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
  317. unsigned long event, void *data)
  318. {
  319. struct clk_notifier_data *ndata = data;
  320. struct ttc_timer *ttc = to_ttc_timer(nb);
  321. struct ttc_timer_clockevent *ttcce = container_of(ttc,
  322. struct ttc_timer_clockevent, ttc);
  323. switch (event) {
  324. case POST_RATE_CHANGE:
  325. /* update cached frequency */
  326. ttc->freq = ndata->new_rate;
  327. clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
  328. fallthrough;
  329. case PRE_RATE_CHANGE:
  330. case ABORT_RATE_CHANGE:
  331. default:
  332. return NOTIFY_DONE;
  333. }
  334. }
  335. static int __init ttc_setup_clockevent(struct clk *clk,
  336. void __iomem *base, u32 irq)
  337. {
  338. struct ttc_timer_clockevent *ttcce;
  339. int err;
  340. ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
  341. if (!ttcce)
  342. return -ENOMEM;
  343. ttcce->ttc.clk = clk;
  344. err = clk_prepare_enable(ttcce->ttc.clk);
  345. if (err)
  346. goto out_kfree;
  347. ttcce->ttc.clk_rate_change_nb.notifier_call =
  348. ttc_rate_change_clockevent_cb;
  349. ttcce->ttc.clk_rate_change_nb.next = NULL;
  350. err = clk_notifier_register(ttcce->ttc.clk,
  351. &ttcce->ttc.clk_rate_change_nb);
  352. if (err) {
  353. pr_warn("Unable to register clock notifier.\n");
  354. goto out_kfree;
  355. }
  356. ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
  357. ttcce->ttc.base_addr = base;
  358. ttcce->ce.name = "ttc_clockevent";
  359. ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
  360. ttcce->ce.set_next_event = ttc_set_next_event;
  361. ttcce->ce.set_state_shutdown = ttc_shutdown;
  362. ttcce->ce.set_state_periodic = ttc_set_periodic;
  363. ttcce->ce.set_state_oneshot = ttc_shutdown;
  364. ttcce->ce.tick_resume = ttc_resume;
  365. ttcce->ce.rating = 200;
  366. ttcce->ce.irq = irq;
  367. ttcce->ce.cpumask = cpu_possible_mask;
  368. /*
  369. * Setup the clock event timer to be an interval timer which
  370. * is prescaled by 32 using the interval interrupt. Leave it
  371. * disabled for now.
  372. */
  373. writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
  374. writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
  375. ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
  376. writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
  377. err = request_irq(irq, ttc_clock_event_interrupt,
  378. IRQF_TIMER, ttcce->ce.name, ttcce);
  379. if (err)
  380. goto out_kfree;
  381. clockevents_config_and_register(&ttcce->ce,
  382. ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
  383. return 0;
  384. out_kfree:
  385. kfree(ttcce);
  386. return err;
  387. }
  388. static int __init ttc_timer_probe(struct platform_device *pdev)
  389. {
  390. unsigned int irq;
  391. void __iomem *timer_baseaddr;
  392. struct clk *clk_cs, *clk_ce;
  393. static int initialized;
  394. int clksel, ret;
  395. u32 timer_width = 16;
  396. struct device_node *timer = pdev->dev.of_node;
  397. if (initialized)
  398. return 0;
  399. initialized = 1;
  400. /*
  401. * Get the 1st Triple Timer Counter (TTC) block from the device tree
  402. * and use it. Note that the event timer uses the interrupt and it's the
  403. * 2nd TTC hence the irq_of_parse_and_map(,1)
  404. */
  405. timer_baseaddr = of_iomap(timer, 0);
  406. if (!timer_baseaddr) {
  407. pr_err("ERROR: invalid timer base address\n");
  408. return -ENXIO;
  409. }
  410. irq = irq_of_parse_and_map(timer, 1);
  411. if (irq <= 0) {
  412. pr_err("ERROR: invalid interrupt number\n");
  413. return -EINVAL;
  414. }
  415. of_property_read_u32(timer, "timer-width", &timer_width);
  416. clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
  417. clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
  418. clk_cs = of_clk_get(timer, clksel);
  419. if (IS_ERR(clk_cs)) {
  420. pr_err("ERROR: timer input clock not found\n");
  421. return PTR_ERR(clk_cs);
  422. }
  423. clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
  424. clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
  425. clk_ce = of_clk_get(timer, clksel);
  426. if (IS_ERR(clk_ce)) {
  427. pr_err("ERROR: timer input clock not found\n");
  428. return PTR_ERR(clk_ce);
  429. }
  430. ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
  431. if (ret)
  432. return ret;
  433. ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
  434. if (ret)
  435. return ret;
  436. pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);
  437. return 0;
  438. }
  439. static const struct of_device_id ttc_timer_of_match[] = {
  440. {.compatible = "cdns,ttc"},
  441. {},
  442. };
  443. MODULE_DEVICE_TABLE(of, ttc_timer_of_match);
  444. static struct platform_driver ttc_timer_driver = {
  445. .driver = {
  446. .name = "cdns_ttc_timer",
  447. .of_match_table = ttc_timer_of_match,
  448. },
  449. };
  450. builtin_platform_driver_probe(ttc_timer_driver, ttc_timer_probe);