timer-atcpit100.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (C) 2005-2017 Andes Technology Corporation
  3. /*
  4. * Andestech ATCPIT100 Timer Device Driver Implementation
  5. * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  6. *
  7. */
  8. #include <linux/irq.h>
  9. #include <linux/clocksource.h>
  10. #include <linux/clockchips.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/ioport.h>
  13. #include <linux/cpufreq.h>
  14. #include <linux/sched.h>
  15. #include <linux/sched_clock.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/of_platform.h>
  19. #include "timer-of.h"
  20. #ifdef CONFIG_NDS32
  21. #include <asm/vdso_timer_info.h>
  22. #endif
  23. /*
  24. * Definition of register offsets
  25. */
  26. /* ID and Revision Register */
  27. #define ID_REV 0x0
  28. /* Configuration Register */
  29. #define CFG 0x10
  30. /* Interrupt Enable Register */
  31. #define INT_EN 0x14
  32. #define CH_INT_EN(c, i) ((1<<i)<<(4*c))
  33. #define CH0INT0EN 0x01
  34. /* Interrupt Status Register */
  35. #define INT_STA 0x18
  36. #define CH0INT0 0x01
  37. /* Channel Enable Register */
  38. #define CH_EN 0x1C
  39. #define CH0TMR0EN 0x1
  40. #define CH1TMR0EN 0x10
  41. /* Channel 0 , 1 Control Register */
  42. #define CH0_CTL (0x20)
  43. #define CH1_CTL (0x20 + 0x10)
  44. /* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
  45. #define APB_CLK BIT(3)
  46. /* Channel mode , bit 0~2 */
  47. #define TMR_32 0x1
  48. #define TMR_16 0x2
  49. #define TMR_8 0x3
  50. /* Channel 0 , 1 Reload Register */
  51. #define CH0_REL (0x24)
  52. #define CH1_REL (0x24 + 0x10)
  53. /* Channel 0 , 1 Counter Register */
  54. #define CH0_CNT (0x28)
  55. #define CH1_CNT (0x28 + 0x10)
  56. #define TIMER_SYNC_TICKS 3
  57. static void atcpit100_ch1_tmr0_en(void __iomem *base)
  58. {
  59. writel(~0, base + CH1_REL);
  60. writel(APB_CLK|TMR_32, base + CH1_CTL);
  61. }
  62. static void atcpit100_ch0_tmr0_en(void __iomem *base)
  63. {
  64. writel(APB_CLK|TMR_32, base + CH0_CTL);
  65. }
  66. static void atcpit100_clkevt_time_setup(void __iomem *base, unsigned long delay)
  67. {
  68. writel(delay, base + CH0_CNT);
  69. writel(delay, base + CH0_REL);
  70. }
  71. static void atcpit100_timer_clear_interrupt(void __iomem *base)
  72. {
  73. u32 val;
  74. val = readl(base + INT_STA);
  75. writel(val | CH0INT0, base + INT_STA);
  76. }
  77. static void atcpit100_clocksource_start(void __iomem *base)
  78. {
  79. u32 val;
  80. val = readl(base + CH_EN);
  81. writel(val | CH1TMR0EN, base + CH_EN);
  82. }
  83. static void atcpit100_clkevt_time_start(void __iomem *base)
  84. {
  85. u32 val;
  86. val = readl(base + CH_EN);
  87. writel(val | CH0TMR0EN, base + CH_EN);
  88. }
  89. static void atcpit100_clkevt_time_stop(void __iomem *base)
  90. {
  91. u32 val;
  92. atcpit100_timer_clear_interrupt(base);
  93. val = readl(base + CH_EN);
  94. writel(val & ~CH0TMR0EN, base + CH_EN);
  95. }
  96. static int atcpit100_clkevt_next_event(unsigned long evt,
  97. struct clock_event_device *clkevt)
  98. {
  99. u32 val;
  100. struct timer_of *to = to_timer_of(clkevt);
  101. val = readl(timer_of_base(to) + CH_EN);
  102. writel(val & ~CH0TMR0EN, timer_of_base(to) + CH_EN);
  103. writel(evt, timer_of_base(to) + CH0_REL);
  104. writel(val | CH0TMR0EN, timer_of_base(to) + CH_EN);
  105. return 0;
  106. }
  107. static int atcpit100_clkevt_set_periodic(struct clock_event_device *evt)
  108. {
  109. struct timer_of *to = to_timer_of(evt);
  110. atcpit100_clkevt_time_setup(timer_of_base(to), timer_of_period(to));
  111. atcpit100_clkevt_time_start(timer_of_base(to));
  112. return 0;
  113. }
  114. static int atcpit100_clkevt_shutdown(struct clock_event_device *evt)
  115. {
  116. struct timer_of *to = to_timer_of(evt);
  117. atcpit100_clkevt_time_stop(timer_of_base(to));
  118. return 0;
  119. }
  120. static int atcpit100_clkevt_set_oneshot(struct clock_event_device *evt)
  121. {
  122. struct timer_of *to = to_timer_of(evt);
  123. u32 val;
  124. writel(~0x0, timer_of_base(to) + CH0_REL);
  125. val = readl(timer_of_base(to) + CH_EN);
  126. writel(val | CH0TMR0EN, timer_of_base(to) + CH_EN);
  127. return 0;
  128. }
  129. static irqreturn_t atcpit100_timer_interrupt(int irq, void *dev_id)
  130. {
  131. struct clock_event_device *evt = (struct clock_event_device *)dev_id;
  132. struct timer_of *to = to_timer_of(evt);
  133. atcpit100_timer_clear_interrupt(timer_of_base(to));
  134. evt->event_handler(evt);
  135. return IRQ_HANDLED;
  136. }
  137. static struct timer_of to = {
  138. .flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE,
  139. .clkevt = {
  140. .name = "atcpit100_tick",
  141. .rating = 300,
  142. .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  143. .set_state_shutdown = atcpit100_clkevt_shutdown,
  144. .set_state_periodic = atcpit100_clkevt_set_periodic,
  145. .set_state_oneshot = atcpit100_clkevt_set_oneshot,
  146. .tick_resume = atcpit100_clkevt_shutdown,
  147. .set_next_event = atcpit100_clkevt_next_event,
  148. .cpumask = cpu_possible_mask,
  149. },
  150. .of_irq = {
  151. .handler = atcpit100_timer_interrupt,
  152. .flags = IRQF_TIMER | IRQF_IRQPOLL,
  153. },
  154. /*
  155. * FIXME: we currently only support clocking using PCLK
  156. * and using EXTCLK is not supported in the driver.
  157. */
  158. .of_clk = {
  159. .name = "PCLK",
  160. }
  161. };
  162. static u64 notrace atcpit100_timer_sched_read(void)
  163. {
  164. return ~readl(timer_of_base(&to) + CH1_CNT);
  165. }
  166. #ifdef CONFIG_NDS32
  167. static void fill_vdso_need_info(struct device_node *node)
  168. {
  169. struct resource timer_res;
  170. of_address_to_resource(node, 0, &timer_res);
  171. timer_info.mapping_base = (unsigned long)timer_res.start;
  172. timer_info.cycle_count_down = true;
  173. timer_info.cycle_count_reg_offset = CH1_CNT;
  174. }
  175. #endif
  176. static int __init atcpit100_timer_init(struct device_node *node)
  177. {
  178. int ret;
  179. u32 val;
  180. void __iomem *base;
  181. ret = timer_of_init(node, &to);
  182. if (ret)
  183. return ret;
  184. base = timer_of_base(&to);
  185. sched_clock_register(atcpit100_timer_sched_read, 32,
  186. timer_of_rate(&to));
  187. ret = clocksource_mmio_init(base + CH1_CNT,
  188. node->name, timer_of_rate(&to), 300, 32,
  189. clocksource_mmio_readl_down);
  190. if (ret) {
  191. pr_err("Failed to register clocksource\n");
  192. return ret;
  193. }
  194. /* clear channel 0 timer0 interrupt */
  195. atcpit100_timer_clear_interrupt(base);
  196. clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
  197. TIMER_SYNC_TICKS, 0xffffffff);
  198. atcpit100_ch0_tmr0_en(base);
  199. atcpit100_ch1_tmr0_en(base);
  200. atcpit100_clocksource_start(base);
  201. atcpit100_clkevt_time_start(base);
  202. /* Enable channel 0 timer0 interrupt */
  203. val = readl(base + INT_EN);
  204. writel(val | CH0INT0EN, base + INT_EN);
  205. #ifdef CONFIG_NDS32
  206. fill_vdso_need_info(node);
  207. #endif
  208. return ret;
  209. }
  210. TIMER_OF_DECLARE(atcpit100, "andestech,atcpit100", atcpit100_timer_init);