mps2-timer.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 ARM Limited
  4. *
  5. * Author: Vladimir Murzin <vladimir.murzin@arm.com>
  6. */
  7. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  8. #include <linux/clk.h>
  9. #include <linux/clockchips.h>
  10. #include <linux/clocksource.h>
  11. #include <linux/err.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/irq.h>
  15. #include <linux/of_address.h>
  16. #include <linux/of.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/sched_clock.h>
  19. #include <linux/slab.h>
  20. #define TIMER_CTRL 0x0
  21. #define TIMER_CTRL_ENABLE BIT(0)
  22. #define TIMER_CTRL_IE BIT(3)
  23. #define TIMER_VALUE 0x4
  24. #define TIMER_RELOAD 0x8
  25. #define TIMER_INT 0xc
  26. struct clockevent_mps2 {
  27. void __iomem *reg;
  28. u32 clock_count_per_tick;
  29. struct clock_event_device clkevt;
  30. };
  31. static void __iomem *sched_clock_base;
  32. static u64 notrace mps2_sched_read(void)
  33. {
  34. return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
  35. }
  36. static inline struct clockevent_mps2 *to_mps2_clkevt(struct clock_event_device *c)
  37. {
  38. return container_of(c, struct clockevent_mps2, clkevt);
  39. }
  40. static void clockevent_mps2_writel(u32 val, struct clock_event_device *c, u32 offset)
  41. {
  42. writel_relaxed(val, to_mps2_clkevt(c)->reg + offset);
  43. }
  44. static int mps2_timer_shutdown(struct clock_event_device *ce)
  45. {
  46. clockevent_mps2_writel(0, ce, TIMER_RELOAD);
  47. clockevent_mps2_writel(0, ce, TIMER_CTRL);
  48. return 0;
  49. }
  50. static int mps2_timer_set_next_event(unsigned long next, struct clock_event_device *ce)
  51. {
  52. clockevent_mps2_writel(next, ce, TIMER_VALUE);
  53. clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL);
  54. return 0;
  55. }
  56. static int mps2_timer_set_periodic(struct clock_event_device *ce)
  57. {
  58. u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick;
  59. clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_RELOAD);
  60. clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_VALUE);
  61. clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL);
  62. return 0;
  63. }
  64. static irqreturn_t mps2_timer_interrupt(int irq, void *dev_id)
  65. {
  66. struct clockevent_mps2 *ce = dev_id;
  67. u32 status = readl_relaxed(ce->reg + TIMER_INT);
  68. if (!status) {
  69. pr_warn("spurious interrupt\n");
  70. return IRQ_NONE;
  71. }
  72. writel_relaxed(1, ce->reg + TIMER_INT);
  73. ce->clkevt.event_handler(&ce->clkevt);
  74. return IRQ_HANDLED;
  75. }
  76. static int __init mps2_clockevent_init(struct device_node *np)
  77. {
  78. void __iomem *base;
  79. struct clk *clk = NULL;
  80. struct clockevent_mps2 *ce;
  81. u32 rate;
  82. int irq, ret;
  83. const char *name = "mps2-clkevt";
  84. ret = of_property_read_u32(np, "clock-frequency", &rate);
  85. if (ret) {
  86. clk = of_clk_get(np, 0);
  87. if (IS_ERR(clk)) {
  88. ret = PTR_ERR(clk);
  89. pr_err("failed to get clock for clockevent: %d\n", ret);
  90. goto out;
  91. }
  92. ret = clk_prepare_enable(clk);
  93. if (ret) {
  94. pr_err("failed to enable clock for clockevent: %d\n", ret);
  95. goto out_clk_put;
  96. }
  97. rate = clk_get_rate(clk);
  98. }
  99. base = of_iomap(np, 0);
  100. if (!base) {
  101. ret = -EADDRNOTAVAIL;
  102. pr_err("failed to map register for clockevent: %d\n", ret);
  103. goto out_clk_disable;
  104. }
  105. irq = irq_of_parse_and_map(np, 0);
  106. if (!irq) {
  107. ret = -ENOENT;
  108. pr_err("failed to get irq for clockevent: %d\n", ret);
  109. goto out_iounmap;
  110. }
  111. ce = kzalloc(sizeof(*ce), GFP_KERNEL);
  112. if (!ce) {
  113. ret = -ENOMEM;
  114. goto out_iounmap;
  115. }
  116. ce->reg = base;
  117. ce->clock_count_per_tick = DIV_ROUND_CLOSEST(rate, HZ);
  118. ce->clkevt.irq = irq;
  119. ce->clkevt.name = name;
  120. ce->clkevt.rating = 200;
  121. ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
  122. ce->clkevt.cpumask = cpu_possible_mask;
  123. ce->clkevt.set_state_shutdown = mps2_timer_shutdown;
  124. ce->clkevt.set_state_periodic = mps2_timer_set_periodic;
  125. ce->clkevt.set_state_oneshot = mps2_timer_shutdown;
  126. ce->clkevt.set_next_event = mps2_timer_set_next_event;
  127. /* Ensure timer is disabled */
  128. writel_relaxed(0, base + TIMER_CTRL);
  129. ret = request_irq(irq, mps2_timer_interrupt, IRQF_TIMER, name, ce);
  130. if (ret) {
  131. pr_err("failed to request irq for clockevent: %d\n", ret);
  132. goto out_kfree;
  133. }
  134. clockevents_config_and_register(&ce->clkevt, rate, 0xf, 0xffffffff);
  135. return 0;
  136. out_kfree:
  137. kfree(ce);
  138. out_iounmap:
  139. iounmap(base);
  140. out_clk_disable:
  141. /* clk_{disable, unprepare, put}() can handle NULL as a parameter */
  142. clk_disable_unprepare(clk);
  143. out_clk_put:
  144. clk_put(clk);
  145. out:
  146. return ret;
  147. }
  148. static int __init mps2_clocksource_init(struct device_node *np)
  149. {
  150. void __iomem *base;
  151. struct clk *clk = NULL;
  152. u32 rate;
  153. int ret;
  154. const char *name = "mps2-clksrc";
  155. ret = of_property_read_u32(np, "clock-frequency", &rate);
  156. if (ret) {
  157. clk = of_clk_get(np, 0);
  158. if (IS_ERR(clk)) {
  159. ret = PTR_ERR(clk);
  160. pr_err("failed to get clock for clocksource: %d\n", ret);
  161. goto out;
  162. }
  163. ret = clk_prepare_enable(clk);
  164. if (ret) {
  165. pr_err("failed to enable clock for clocksource: %d\n", ret);
  166. goto out_clk_put;
  167. }
  168. rate = clk_get_rate(clk);
  169. }
  170. base = of_iomap(np, 0);
  171. if (!base) {
  172. ret = -EADDRNOTAVAIL;
  173. pr_err("failed to map register for clocksource: %d\n", ret);
  174. goto out_clk_disable;
  175. }
  176. /* Ensure timer is disabled */
  177. writel_relaxed(0, base + TIMER_CTRL);
  178. /* ... and set it up as free-running clocksource */
  179. writel_relaxed(0xffffffff, base + TIMER_VALUE);
  180. writel_relaxed(0xffffffff, base + TIMER_RELOAD);
  181. writel_relaxed(TIMER_CTRL_ENABLE, base + TIMER_CTRL);
  182. ret = clocksource_mmio_init(base + TIMER_VALUE, name,
  183. rate, 200, 32,
  184. clocksource_mmio_readl_down);
  185. if (ret) {
  186. pr_err("failed to init clocksource: %d\n", ret);
  187. goto out_iounmap;
  188. }
  189. sched_clock_base = base;
  190. sched_clock_register(mps2_sched_read, 32, rate);
  191. return 0;
  192. out_iounmap:
  193. iounmap(base);
  194. out_clk_disable:
  195. /* clk_{disable, unprepare, put}() can handle NULL as a parameter */
  196. clk_disable_unprepare(clk);
  197. out_clk_put:
  198. clk_put(clk);
  199. out:
  200. return ret;
  201. }
  202. static int __init mps2_timer_init(struct device_node *np)
  203. {
  204. static int has_clocksource, has_clockevent;
  205. int ret;
  206. if (!has_clocksource) {
  207. ret = mps2_clocksource_init(np);
  208. if (!ret) {
  209. has_clocksource = 1;
  210. return 0;
  211. }
  212. }
  213. if (!has_clockevent) {
  214. ret = mps2_clockevent_init(np);
  215. if (!ret) {
  216. has_clockevent = 1;
  217. return 0;
  218. }
  219. }
  220. return 0;
  221. }
  222. TIMER_OF_DECLARE(mps2_timer, "arm,mps2-timer", mps2_timer_init);