jcore-pit.c 6.5 KB

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  1. /*
  2. * J-Core SoC PIT/clocksource driver
  3. *
  4. * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/slab.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/clockchips.h>
  14. #include <linux/clocksource.h>
  15. #include <linux/sched_clock.h>
  16. #include <linux/cpu.h>
  17. #include <linux/cpuhotplug.h>
  18. #include <linux/of_address.h>
  19. #include <linux/of_irq.h>
  20. #define PIT_IRQ_SHIFT 12
  21. #define PIT_PRIO_SHIFT 20
  22. #define PIT_ENABLE_SHIFT 26
  23. #define PIT_PRIO_MASK 0xf
  24. #define REG_PITEN 0x00
  25. #define REG_THROT 0x10
  26. #define REG_COUNT 0x14
  27. #define REG_BUSPD 0x18
  28. #define REG_SECHI 0x20
  29. #define REG_SECLO 0x24
  30. #define REG_NSEC 0x28
  31. struct jcore_pit {
  32. struct clock_event_device ced;
  33. void __iomem *base;
  34. unsigned long periodic_delta;
  35. u32 enable_val;
  36. };
  37. static void __iomem *jcore_pit_base;
  38. static struct jcore_pit __percpu *jcore_pit_percpu;
  39. static notrace u64 jcore_sched_clock_read(void)
  40. {
  41. u32 seclo, nsec, seclo0;
  42. __iomem void *base = jcore_pit_base;
  43. seclo = readl(base + REG_SECLO);
  44. do {
  45. seclo0 = seclo;
  46. nsec = readl(base + REG_NSEC);
  47. seclo = readl(base + REG_SECLO);
  48. } while (seclo0 != seclo);
  49. return seclo * NSEC_PER_SEC + nsec;
  50. }
  51. static u64 jcore_clocksource_read(struct clocksource *cs)
  52. {
  53. return jcore_sched_clock_read();
  54. }
  55. static int jcore_pit_disable(struct jcore_pit *pit)
  56. {
  57. writel(0, pit->base + REG_PITEN);
  58. return 0;
  59. }
  60. static int jcore_pit_set(unsigned long delta, struct jcore_pit *pit)
  61. {
  62. jcore_pit_disable(pit);
  63. writel(delta, pit->base + REG_THROT);
  64. writel(pit->enable_val, pit->base + REG_PITEN);
  65. return 0;
  66. }
  67. static int jcore_pit_set_state_shutdown(struct clock_event_device *ced)
  68. {
  69. struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
  70. return jcore_pit_disable(pit);
  71. }
  72. static int jcore_pit_set_state_oneshot(struct clock_event_device *ced)
  73. {
  74. struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
  75. return jcore_pit_disable(pit);
  76. }
  77. static int jcore_pit_set_state_periodic(struct clock_event_device *ced)
  78. {
  79. struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
  80. return jcore_pit_set(pit->periodic_delta, pit);
  81. }
  82. static int jcore_pit_set_next_event(unsigned long delta,
  83. struct clock_event_device *ced)
  84. {
  85. struct jcore_pit *pit = container_of(ced, struct jcore_pit, ced);
  86. return jcore_pit_set(delta, pit);
  87. }
  88. static int jcore_pit_local_init(unsigned cpu)
  89. {
  90. struct jcore_pit *pit = this_cpu_ptr(jcore_pit_percpu);
  91. unsigned buspd, freq;
  92. pr_info("Local J-Core PIT init on cpu %u\n", cpu);
  93. buspd = readl(pit->base + REG_BUSPD);
  94. freq = DIV_ROUND_CLOSEST(NSEC_PER_SEC, buspd);
  95. pit->periodic_delta = DIV_ROUND_CLOSEST(NSEC_PER_SEC, HZ * buspd);
  96. clockevents_config_and_register(&pit->ced, freq, 1, ULONG_MAX);
  97. return 0;
  98. }
  99. static irqreturn_t jcore_timer_interrupt(int irq, void *dev_id)
  100. {
  101. struct jcore_pit *pit = this_cpu_ptr(dev_id);
  102. if (clockevent_state_oneshot(&pit->ced))
  103. jcore_pit_disable(pit);
  104. pit->ced.event_handler(&pit->ced);
  105. return IRQ_HANDLED;
  106. }
  107. static int __init jcore_pit_init(struct device_node *node)
  108. {
  109. int err;
  110. unsigned pit_irq, cpu;
  111. unsigned long hwirq;
  112. u32 irqprio, enable_val;
  113. jcore_pit_base = of_iomap(node, 0);
  114. if (!jcore_pit_base) {
  115. pr_err("Error: Cannot map base address for J-Core PIT\n");
  116. return -ENXIO;
  117. }
  118. pit_irq = irq_of_parse_and_map(node, 0);
  119. if (!pit_irq) {
  120. pr_err("Error: J-Core PIT has no IRQ\n");
  121. return -ENXIO;
  122. }
  123. pr_info("Initializing J-Core PIT at %p IRQ %d\n",
  124. jcore_pit_base, pit_irq);
  125. err = clocksource_mmio_init(jcore_pit_base, "jcore_pit_cs",
  126. NSEC_PER_SEC, 400, 32,
  127. jcore_clocksource_read);
  128. if (err) {
  129. pr_err("Error registering clocksource device: %d\n", err);
  130. return err;
  131. }
  132. sched_clock_register(jcore_sched_clock_read, 32, NSEC_PER_SEC);
  133. jcore_pit_percpu = alloc_percpu(struct jcore_pit);
  134. if (!jcore_pit_percpu) {
  135. pr_err("Failed to allocate memory for clock event device\n");
  136. return -ENOMEM;
  137. }
  138. err = request_irq(pit_irq, jcore_timer_interrupt,
  139. IRQF_TIMER | IRQF_PERCPU,
  140. "jcore_pit", jcore_pit_percpu);
  141. if (err) {
  142. pr_err("pit irq request failed: %d\n", err);
  143. free_percpu(jcore_pit_percpu);
  144. return err;
  145. }
  146. /*
  147. * The J-Core PIT is not hard-wired to a particular IRQ, but
  148. * integrated with the interrupt controller such that the IRQ it
  149. * generates is programmable, as follows:
  150. *
  151. * The bit layout of the PIT enable register is:
  152. *
  153. * .....e..ppppiiiiiiii............
  154. *
  155. * where the .'s indicate unrelated/unused bits, e is enable,
  156. * p is priority, and i is hard irq number.
  157. *
  158. * For the PIT included in AIC1 (obsolete but still in use),
  159. * any hard irq (trap number) can be programmed via the 8
  160. * iiiiiiii bits, and a priority (0-15) is programmable
  161. * separately in the pppp bits.
  162. *
  163. * For the PIT included in AIC2 (current), the programming
  164. * interface is equivalent modulo interrupt mapping. This is
  165. * why a different compatible tag was not used. However only
  166. * traps 64-127 (the ones actually intended to be used for
  167. * interrupts, rather than syscalls/exceptions/etc.) can be
  168. * programmed (the high 2 bits of i are ignored) and the
  169. * priority pppp is <<2'd and or'd onto the irq number. This
  170. * choice seems to have been made on the hardware engineering
  171. * side under an assumption that preserving old AIC1 priority
  172. * mappings was important. Future models will likely ignore
  173. * the pppp field.
  174. */
  175. hwirq = irq_get_irq_data(pit_irq)->hwirq;
  176. irqprio = (hwirq >> 2) & PIT_PRIO_MASK;
  177. enable_val = (1U << PIT_ENABLE_SHIFT)
  178. | (hwirq << PIT_IRQ_SHIFT)
  179. | (irqprio << PIT_PRIO_SHIFT);
  180. for_each_present_cpu(cpu) {
  181. struct jcore_pit *pit = per_cpu_ptr(jcore_pit_percpu, cpu);
  182. pit->base = of_iomap(node, cpu);
  183. if (!pit->base) {
  184. pr_err("Unable to map PIT for cpu %u\n", cpu);
  185. continue;
  186. }
  187. pit->ced.name = "jcore_pit";
  188. pit->ced.features = CLOCK_EVT_FEAT_PERIODIC
  189. | CLOCK_EVT_FEAT_ONESHOT
  190. | CLOCK_EVT_FEAT_PERCPU;
  191. pit->ced.cpumask = cpumask_of(cpu);
  192. pit->ced.rating = 400;
  193. pit->ced.irq = pit_irq;
  194. pit->ced.set_state_shutdown = jcore_pit_set_state_shutdown;
  195. pit->ced.set_state_periodic = jcore_pit_set_state_periodic;
  196. pit->ced.set_state_oneshot = jcore_pit_set_state_oneshot;
  197. pit->ced.set_next_event = jcore_pit_set_next_event;
  198. pit->enable_val = enable_val;
  199. }
  200. cpuhp_setup_state(CPUHP_AP_JCORE_TIMER_STARTING,
  201. "clockevents/jcore:starting",
  202. jcore_pit_local_init, NULL);
  203. return 0;
  204. }
  205. TIMER_OF_DECLARE(jcore_pit, "jcore,pit", jcore_pit_init);