mux.c 6.8 KB

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  1. /*
  2. * TI Multiplexer Clock
  3. *
  4. * Copyright (C) 2013 Texas Instruments, Inc.
  5. *
  6. * Tero Kristo <t-kristo@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13. * kind, whether express or implied; without even the implied warranty
  14. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/clk-provider.h>
  18. #include <linux/slab.h>
  19. #include <linux/err.h>
  20. #include <linux/of.h>
  21. #include <linux/of_address.h>
  22. #include <linux/clk/ti.h>
  23. #include "clock.h"
  24. #undef pr_fmt
  25. #define pr_fmt(fmt) "%s: " fmt, __func__
  26. static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
  27. {
  28. struct clk_omap_mux *mux = to_clk_omap_mux(hw);
  29. int num_parents = clk_hw_get_num_parents(hw);
  30. u32 val;
  31. /*
  32. * FIXME need a mux-specific flag to determine if val is bitwise or
  33. * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
  34. * from 0x1 to 0x7 (index starts at one)
  35. * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
  36. * val = 0x4 really means "bit 2, index starts at bit 0"
  37. */
  38. val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift;
  39. val &= mux->mask;
  40. if (mux->table) {
  41. int i;
  42. for (i = 0; i < num_parents; i++)
  43. if (mux->table[i] == val)
  44. return i;
  45. return -EINVAL;
  46. }
  47. if (val && (mux->flags & CLK_MUX_INDEX_BIT))
  48. val = ffs(val) - 1;
  49. if (val && (mux->flags & CLK_MUX_INDEX_ONE))
  50. val--;
  51. if (val >= num_parents)
  52. return -EINVAL;
  53. return val;
  54. }
  55. static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
  56. {
  57. struct clk_omap_mux *mux = to_clk_omap_mux(hw);
  58. u32 val;
  59. if (mux->table) {
  60. index = mux->table[index];
  61. } else {
  62. if (mux->flags & CLK_MUX_INDEX_BIT)
  63. index = (1 << ffs(index));
  64. if (mux->flags & CLK_MUX_INDEX_ONE)
  65. index++;
  66. }
  67. if (mux->flags & CLK_MUX_HIWORD_MASK) {
  68. val = mux->mask << (mux->shift + 16);
  69. } else {
  70. val = ti_clk_ll_ops->clk_readl(&mux->reg);
  71. val &= ~(mux->mask << mux->shift);
  72. }
  73. val |= index << mux->shift;
  74. ti_clk_ll_ops->clk_writel(val, &mux->reg);
  75. ti_clk_latch(&mux->reg, mux->latch);
  76. return 0;
  77. }
  78. /**
  79. * clk_mux_save_context - Save the parent selcted in the mux
  80. * @hw: pointer struct clk_hw
  81. *
  82. * Save the parent mux value.
  83. */
  84. static int clk_mux_save_context(struct clk_hw *hw)
  85. {
  86. struct clk_omap_mux *mux = to_clk_omap_mux(hw);
  87. mux->saved_parent = ti_clk_mux_get_parent(hw);
  88. return 0;
  89. }
  90. /**
  91. * clk_mux_restore_context - Restore the parent in the mux
  92. * @hw: pointer struct clk_hw
  93. *
  94. * Restore the saved parent mux value.
  95. */
  96. static void clk_mux_restore_context(struct clk_hw *hw)
  97. {
  98. struct clk_omap_mux *mux = to_clk_omap_mux(hw);
  99. ti_clk_mux_set_parent(hw, mux->saved_parent);
  100. }
  101. const struct clk_ops ti_clk_mux_ops = {
  102. .get_parent = ti_clk_mux_get_parent,
  103. .set_parent = ti_clk_mux_set_parent,
  104. .determine_rate = __clk_mux_determine_rate,
  105. .save_context = clk_mux_save_context,
  106. .restore_context = clk_mux_restore_context,
  107. };
  108. static struct clk *_register_mux(struct device *dev, const char *name,
  109. const char * const *parent_names,
  110. u8 num_parents, unsigned long flags,
  111. struct clk_omap_reg *reg, u8 shift, u32 mask,
  112. s8 latch, u8 clk_mux_flags, u32 *table)
  113. {
  114. struct clk_omap_mux *mux;
  115. struct clk *clk;
  116. struct clk_init_data init;
  117. /* allocate the mux */
  118. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  119. if (!mux)
  120. return ERR_PTR(-ENOMEM);
  121. init.name = name;
  122. init.ops = &ti_clk_mux_ops;
  123. init.flags = flags;
  124. init.parent_names = parent_names;
  125. init.num_parents = num_parents;
  126. /* struct clk_mux assignments */
  127. memcpy(&mux->reg, reg, sizeof(*reg));
  128. mux->shift = shift;
  129. mux->mask = mask;
  130. mux->latch = latch;
  131. mux->flags = clk_mux_flags;
  132. mux->table = table;
  133. mux->hw.init = &init;
  134. clk = ti_clk_register(dev, &mux->hw, name);
  135. if (IS_ERR(clk))
  136. kfree(mux);
  137. return clk;
  138. }
  139. /**
  140. * of_mux_clk_setup - Setup function for simple mux rate clock
  141. * @node: DT node for the clock
  142. *
  143. * Sets up a basic clock multiplexer.
  144. */
  145. static void of_mux_clk_setup(struct device_node *node)
  146. {
  147. struct clk *clk;
  148. struct clk_omap_reg reg;
  149. unsigned int num_parents;
  150. const char **parent_names;
  151. u8 clk_mux_flags = 0;
  152. u32 mask = 0;
  153. u32 shift = 0;
  154. s32 latch = -EINVAL;
  155. u32 flags = CLK_SET_RATE_NO_REPARENT;
  156. num_parents = of_clk_get_parent_count(node);
  157. if (num_parents < 2) {
  158. pr_err("mux-clock %pOFn must have parents\n", node);
  159. return;
  160. }
  161. parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
  162. if (!parent_names)
  163. goto cleanup;
  164. of_clk_parent_fill(node, parent_names, num_parents);
  165. if (ti_clk_get_reg_addr(node, 0, &reg))
  166. goto cleanup;
  167. of_property_read_u32(node, "ti,bit-shift", &shift);
  168. of_property_read_u32(node, "ti,latch-bit", &latch);
  169. if (of_property_read_bool(node, "ti,index-starts-at-one"))
  170. clk_mux_flags |= CLK_MUX_INDEX_ONE;
  171. if (of_property_read_bool(node, "ti,set-rate-parent"))
  172. flags |= CLK_SET_RATE_PARENT;
  173. /* Generate bit-mask based on parent info */
  174. mask = num_parents;
  175. if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
  176. mask--;
  177. mask = (1 << fls(mask)) - 1;
  178. clk = _register_mux(NULL, node->name, parent_names, num_parents,
  179. flags, &reg, shift, mask, latch, clk_mux_flags,
  180. NULL);
  181. if (!IS_ERR(clk))
  182. of_clk_add_provider(node, of_clk_src_simple_get, clk);
  183. cleanup:
  184. kfree(parent_names);
  185. }
  186. CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
  187. struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
  188. {
  189. struct clk_omap_mux *mux;
  190. int num_parents;
  191. if (!setup)
  192. return NULL;
  193. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  194. if (!mux)
  195. return ERR_PTR(-ENOMEM);
  196. mux->shift = setup->bit_shift;
  197. mux->latch = -EINVAL;
  198. mux->reg.index = setup->module;
  199. mux->reg.offset = setup->reg;
  200. if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
  201. mux->flags |= CLK_MUX_INDEX_ONE;
  202. num_parents = setup->num_parents;
  203. mux->mask = num_parents - 1;
  204. mux->mask = (1 << fls(mux->mask)) - 1;
  205. return &mux->hw;
  206. }
  207. static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
  208. {
  209. struct clk_omap_mux *mux;
  210. unsigned int num_parents;
  211. u32 val;
  212. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  213. if (!mux)
  214. return;
  215. if (ti_clk_get_reg_addr(node, 0, &mux->reg))
  216. goto cleanup;
  217. if (!of_property_read_u32(node, "ti,bit-shift", &val))
  218. mux->shift = val;
  219. if (of_property_read_bool(node, "ti,index-starts-at-one"))
  220. mux->flags |= CLK_MUX_INDEX_ONE;
  221. num_parents = of_clk_get_parent_count(node);
  222. if (num_parents < 2) {
  223. pr_err("%pOFn must have parents\n", node);
  224. goto cleanup;
  225. }
  226. mux->mask = num_parents - 1;
  227. mux->mask = (1 << fls(mux->mask)) - 1;
  228. if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
  229. return;
  230. cleanup:
  231. kfree(mux);
  232. }
  233. CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
  234. of_ti_composite_mux_clk_setup);