gate.c 7.4 KB

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  1. /*
  2. * OMAP gate clock support
  3. *
  4. * Copyright (C) 2013 Texas Instruments, Inc.
  5. *
  6. * Tero Kristo <t-kristo@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13. * kind, whether express or implied; without even the implied warranty
  14. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/clk-provider.h>
  18. #include <linux/slab.h>
  19. #include <linux/io.h>
  20. #include <linux/of.h>
  21. #include <linux/of_address.h>
  22. #include <linux/clk/ti.h>
  23. #include "clock.h"
  24. #undef pr_fmt
  25. #define pr_fmt(fmt) "%s: " fmt, __func__
  26. static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
  27. static const struct clk_ops omap_gate_clkdm_clk_ops = {
  28. .init = &omap2_init_clk_clkdm,
  29. .enable = &omap2_clkops_enable_clkdm,
  30. .disable = &omap2_clkops_disable_clkdm,
  31. .restore_context = clk_gate_restore_context,
  32. };
  33. const struct clk_ops omap_gate_clk_ops = {
  34. .init = &omap2_init_clk_clkdm,
  35. .enable = &omap2_dflt_clk_enable,
  36. .disable = &omap2_dflt_clk_disable,
  37. .is_enabled = &omap2_dflt_clk_is_enabled,
  38. .restore_context = clk_gate_restore_context,
  39. };
  40. static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
  41. .init = &omap2_init_clk_clkdm,
  42. .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
  43. .disable = &omap2_dflt_clk_disable,
  44. .is_enabled = &omap2_dflt_clk_is_enabled,
  45. .restore_context = clk_gate_restore_context,
  46. };
  47. /**
  48. * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
  49. * from HSDivider PWRDN problem Implements Errata ID: i556.
  50. * @clk: DPLL output struct clk
  51. *
  52. * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
  53. * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
  54. * valueafter their respective PWRDN bits are set. Any dummy write
  55. * (Any other value different from the Read value) to the
  56. * corresponding CM_CLKSEL register will refresh the dividers.
  57. */
  58. static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw)
  59. {
  60. struct clk_omap_divider *parent;
  61. struct clk_hw *parent_hw;
  62. u32 dummy_v, orig_v;
  63. int ret;
  64. /* Clear PWRDN bit of HSDIVIDER */
  65. ret = omap2_dflt_clk_enable(hw);
  66. /* Parent is the x2 node, get parent of parent for the m2 div */
  67. parent_hw = clk_hw_get_parent(clk_hw_get_parent(hw));
  68. parent = to_clk_omap_divider(parent_hw);
  69. /* Restore the dividers */
  70. if (!ret) {
  71. orig_v = ti_clk_ll_ops->clk_readl(&parent->reg);
  72. dummy_v = orig_v;
  73. /* Write any other value different from the Read value */
  74. dummy_v ^= (1 << parent->shift);
  75. ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg);
  76. /* Write the original divider */
  77. ti_clk_ll_ops->clk_writel(orig_v, &parent->reg);
  78. }
  79. return ret;
  80. }
  81. static struct clk *_register_gate(struct device *dev, const char *name,
  82. const char *parent_name, unsigned long flags,
  83. struct clk_omap_reg *reg, u8 bit_idx,
  84. u8 clk_gate_flags, const struct clk_ops *ops,
  85. const struct clk_hw_omap_ops *hw_ops)
  86. {
  87. struct clk_init_data init = { NULL };
  88. struct clk_hw_omap *clk_hw;
  89. struct clk *clk;
  90. clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
  91. if (!clk_hw)
  92. return ERR_PTR(-ENOMEM);
  93. clk_hw->hw.init = &init;
  94. init.name = name;
  95. init.ops = ops;
  96. memcpy(&clk_hw->enable_reg, reg, sizeof(*reg));
  97. clk_hw->enable_bit = bit_idx;
  98. clk_hw->ops = hw_ops;
  99. clk_hw->flags = clk_gate_flags;
  100. init.parent_names = &parent_name;
  101. init.num_parents = 1;
  102. init.flags = flags;
  103. clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
  104. if (IS_ERR(clk))
  105. kfree(clk_hw);
  106. return clk;
  107. }
  108. static void __init _of_ti_gate_clk_setup(struct device_node *node,
  109. const struct clk_ops *ops,
  110. const struct clk_hw_omap_ops *hw_ops)
  111. {
  112. struct clk *clk;
  113. const char *parent_name;
  114. struct clk_omap_reg reg;
  115. u8 enable_bit = 0;
  116. u32 val;
  117. u32 flags = 0;
  118. u8 clk_gate_flags = 0;
  119. if (ops != &omap_gate_clkdm_clk_ops) {
  120. if (ti_clk_get_reg_addr(node, 0, &reg))
  121. return;
  122. if (!of_property_read_u32(node, "ti,bit-shift", &val))
  123. enable_bit = val;
  124. }
  125. if (of_clk_get_parent_count(node) != 1) {
  126. pr_err("%pOFn must have 1 parent\n", node);
  127. return;
  128. }
  129. parent_name = of_clk_get_parent_name(node, 0);
  130. if (of_property_read_bool(node, "ti,set-rate-parent"))
  131. flags |= CLK_SET_RATE_PARENT;
  132. if (of_property_read_bool(node, "ti,set-bit-to-disable"))
  133. clk_gate_flags |= INVERT_ENABLE;
  134. clk = _register_gate(NULL, node->name, parent_name, flags, &reg,
  135. enable_bit, clk_gate_flags, ops, hw_ops);
  136. if (!IS_ERR(clk))
  137. of_clk_add_provider(node, of_clk_src_simple_get, clk);
  138. }
  139. static void __init
  140. _of_ti_composite_gate_clk_setup(struct device_node *node,
  141. const struct clk_hw_omap_ops *hw_ops)
  142. {
  143. struct clk_hw_omap *gate;
  144. u32 val = 0;
  145. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  146. if (!gate)
  147. return;
  148. if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg))
  149. goto cleanup;
  150. of_property_read_u32(node, "ti,bit-shift", &val);
  151. gate->enable_bit = val;
  152. gate->ops = hw_ops;
  153. if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
  154. return;
  155. cleanup:
  156. kfree(gate);
  157. }
  158. static void __init
  159. of_ti_composite_no_wait_gate_clk_setup(struct device_node *node)
  160. {
  161. _of_ti_composite_gate_clk_setup(node, NULL);
  162. }
  163. CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock",
  164. of_ti_composite_no_wait_gate_clk_setup);
  165. #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  166. static void __init of_ti_composite_interface_clk_setup(struct device_node *node)
  167. {
  168. _of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait);
  169. }
  170. CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock",
  171. of_ti_composite_interface_clk_setup);
  172. #endif
  173. static void __init of_ti_composite_gate_clk_setup(struct device_node *node)
  174. {
  175. _of_ti_composite_gate_clk_setup(node, &clkhwops_wait);
  176. }
  177. CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock",
  178. of_ti_composite_gate_clk_setup);
  179. static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
  180. {
  181. _of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL);
  182. }
  183. CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
  184. of_ti_clkdm_gate_clk_setup);
  185. static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
  186. {
  187. _of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops,
  188. &clkhwops_wait);
  189. }
  190. CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
  191. of_ti_hsdiv_gate_clk_setup);
  192. static void __init of_ti_gate_clk_setup(struct device_node *node)
  193. {
  194. _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL);
  195. }
  196. CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup);
  197. static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
  198. {
  199. _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait);
  200. }
  201. CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
  202. of_ti_wait_gate_clk_setup);
  203. #ifdef CONFIG_ARCH_OMAP3
  204. static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
  205. {
  206. _of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
  207. &clkhwops_am35xx_ipss_module_wait);
  208. }
  209. CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
  210. of_ti_am35xx_gate_clk_setup);
  211. static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
  212. {
  213. _of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
  214. &clkhwops_omap3430es2_dss_usbhost_wait);
  215. }
  216. CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
  217. of_ti_dss_gate_clk_setup);
  218. #endif