fapll.c 15 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or
  3. * modify it under the terms of the GNU General Public License as
  4. * published by the Free Software Foundation version 2.
  5. *
  6. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  7. * kind, whether express or implied; without even the implied warranty
  8. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  9. * GNU General Public License for more details.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/clk-provider.h>
  13. #include <linux/delay.h>
  14. #include <linux/err.h>
  15. #include <linux/io.h>
  16. #include <linux/math64.h>
  17. #include <linux/of.h>
  18. #include <linux/of_address.h>
  19. #include <linux/clk/ti.h>
  20. /* FAPLL Control Register PLL_CTRL */
  21. #define FAPLL_MAIN_MULT_N_SHIFT 16
  22. #define FAPLL_MAIN_DIV_P_SHIFT 8
  23. #define FAPLL_MAIN_LOCK BIT(7)
  24. #define FAPLL_MAIN_PLLEN BIT(3)
  25. #define FAPLL_MAIN_BP BIT(2)
  26. #define FAPLL_MAIN_LOC_CTL BIT(0)
  27. #define FAPLL_MAIN_MAX_MULT_N 0xffff
  28. #define FAPLL_MAIN_MAX_DIV_P 0xff
  29. #define FAPLL_MAIN_CLEAR_MASK \
  30. ((FAPLL_MAIN_MAX_MULT_N << FAPLL_MAIN_MULT_N_SHIFT) | \
  31. (FAPLL_MAIN_DIV_P_SHIFT << FAPLL_MAIN_DIV_P_SHIFT) | \
  32. FAPLL_MAIN_LOC_CTL)
  33. /* FAPLL powerdown register PWD */
  34. #define FAPLL_PWD_OFFSET 4
  35. #define MAX_FAPLL_OUTPUTS 7
  36. #define FAPLL_MAX_RETRIES 1000
  37. #define to_fapll(_hw) container_of(_hw, struct fapll_data, hw)
  38. #define to_synth(_hw) container_of(_hw, struct fapll_synth, hw)
  39. /* The bypass bit is inverted on the ddr_pll.. */
  40. #define fapll_is_ddr_pll(va) (((u32)(va) & 0xffff) == 0x0440)
  41. /*
  42. * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock,
  43. * and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output.
  44. */
  45. #define is_ddr_pll_clk1(va) (((u32)(va) & 0xffff) == 0x044c)
  46. #define is_audio_pll_clk1(va) (((u32)(va) & 0xffff) == 0x04a8)
  47. /* Synthesizer divider register */
  48. #define SYNTH_LDMDIV1 BIT(8)
  49. /* Synthesizer frequency register */
  50. #define SYNTH_LDFREQ BIT(31)
  51. #define SYNTH_PHASE_K 8
  52. #define SYNTH_MAX_INT_DIV 0xf
  53. #define SYNTH_MAX_DIV_M 0xff
  54. struct fapll_data {
  55. struct clk_hw hw;
  56. void __iomem *base;
  57. const char *name;
  58. struct clk *clk_ref;
  59. struct clk *clk_bypass;
  60. struct clk_onecell_data outputs;
  61. bool bypass_bit_inverted;
  62. };
  63. struct fapll_synth {
  64. struct clk_hw hw;
  65. struct fapll_data *fd;
  66. int index;
  67. void __iomem *freq;
  68. void __iomem *div;
  69. const char *name;
  70. struct clk *clk_pll;
  71. };
  72. static bool ti_fapll_clock_is_bypass(struct fapll_data *fd)
  73. {
  74. u32 v = readl_relaxed(fd->base);
  75. if (fd->bypass_bit_inverted)
  76. return !(v & FAPLL_MAIN_BP);
  77. else
  78. return !!(v & FAPLL_MAIN_BP);
  79. }
  80. static void ti_fapll_set_bypass(struct fapll_data *fd)
  81. {
  82. u32 v = readl_relaxed(fd->base);
  83. if (fd->bypass_bit_inverted)
  84. v &= ~FAPLL_MAIN_BP;
  85. else
  86. v |= FAPLL_MAIN_BP;
  87. writel_relaxed(v, fd->base);
  88. }
  89. static void ti_fapll_clear_bypass(struct fapll_data *fd)
  90. {
  91. u32 v = readl_relaxed(fd->base);
  92. if (fd->bypass_bit_inverted)
  93. v |= FAPLL_MAIN_BP;
  94. else
  95. v &= ~FAPLL_MAIN_BP;
  96. writel_relaxed(v, fd->base);
  97. }
  98. static int ti_fapll_wait_lock(struct fapll_data *fd)
  99. {
  100. int retries = FAPLL_MAX_RETRIES;
  101. u32 v;
  102. while ((v = readl_relaxed(fd->base))) {
  103. if (v & FAPLL_MAIN_LOCK)
  104. return 0;
  105. if (retries-- <= 0)
  106. break;
  107. udelay(1);
  108. }
  109. pr_err("%s failed to lock\n", fd->name);
  110. return -ETIMEDOUT;
  111. }
  112. static int ti_fapll_enable(struct clk_hw *hw)
  113. {
  114. struct fapll_data *fd = to_fapll(hw);
  115. u32 v = readl_relaxed(fd->base);
  116. v |= FAPLL_MAIN_PLLEN;
  117. writel_relaxed(v, fd->base);
  118. ti_fapll_wait_lock(fd);
  119. return 0;
  120. }
  121. static void ti_fapll_disable(struct clk_hw *hw)
  122. {
  123. struct fapll_data *fd = to_fapll(hw);
  124. u32 v = readl_relaxed(fd->base);
  125. v &= ~FAPLL_MAIN_PLLEN;
  126. writel_relaxed(v, fd->base);
  127. }
  128. static int ti_fapll_is_enabled(struct clk_hw *hw)
  129. {
  130. struct fapll_data *fd = to_fapll(hw);
  131. u32 v = readl_relaxed(fd->base);
  132. return v & FAPLL_MAIN_PLLEN;
  133. }
  134. static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,
  135. unsigned long parent_rate)
  136. {
  137. struct fapll_data *fd = to_fapll(hw);
  138. u32 fapll_n, fapll_p, v;
  139. u64 rate;
  140. if (ti_fapll_clock_is_bypass(fd))
  141. return parent_rate;
  142. rate = parent_rate;
  143. /* PLL pre-divider is P and multiplier is N */
  144. v = readl_relaxed(fd->base);
  145. fapll_p = (v >> 8) & 0xff;
  146. if (fapll_p)
  147. do_div(rate, fapll_p);
  148. fapll_n = v >> 16;
  149. if (fapll_n)
  150. rate *= fapll_n;
  151. return rate;
  152. }
  153. static u8 ti_fapll_get_parent(struct clk_hw *hw)
  154. {
  155. struct fapll_data *fd = to_fapll(hw);
  156. if (ti_fapll_clock_is_bypass(fd))
  157. return 1;
  158. return 0;
  159. }
  160. static int ti_fapll_set_div_mult(unsigned long rate,
  161. unsigned long parent_rate,
  162. u32 *pre_div_p, u32 *mult_n)
  163. {
  164. /*
  165. * So far no luck getting decent clock with PLL divider,
  166. * PLL does not seem to lock and the signal does not look
  167. * right. It seems the divider can only be used together
  168. * with the multiplier?
  169. */
  170. if (rate < parent_rate) {
  171. pr_warn("FAPLL main divider rates unsupported\n");
  172. return -EINVAL;
  173. }
  174. *mult_n = rate / parent_rate;
  175. if (*mult_n > FAPLL_MAIN_MAX_MULT_N)
  176. return -EINVAL;
  177. *pre_div_p = 1;
  178. return 0;
  179. }
  180. static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate,
  181. unsigned long *parent_rate)
  182. {
  183. u32 pre_div_p, mult_n;
  184. int error;
  185. if (!rate)
  186. return -EINVAL;
  187. error = ti_fapll_set_div_mult(rate, *parent_rate,
  188. &pre_div_p, &mult_n);
  189. if (error)
  190. return error;
  191. rate = *parent_rate / pre_div_p;
  192. rate *= mult_n;
  193. return rate;
  194. }
  195. static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate,
  196. unsigned long parent_rate)
  197. {
  198. struct fapll_data *fd = to_fapll(hw);
  199. u32 pre_div_p, mult_n, v;
  200. int error;
  201. if (!rate)
  202. return -EINVAL;
  203. error = ti_fapll_set_div_mult(rate, parent_rate,
  204. &pre_div_p, &mult_n);
  205. if (error)
  206. return error;
  207. ti_fapll_set_bypass(fd);
  208. v = readl_relaxed(fd->base);
  209. v &= ~FAPLL_MAIN_CLEAR_MASK;
  210. v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT;
  211. v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT;
  212. writel_relaxed(v, fd->base);
  213. if (ti_fapll_is_enabled(hw))
  214. ti_fapll_wait_lock(fd);
  215. ti_fapll_clear_bypass(fd);
  216. return 0;
  217. }
  218. static const struct clk_ops ti_fapll_ops = {
  219. .enable = ti_fapll_enable,
  220. .disable = ti_fapll_disable,
  221. .is_enabled = ti_fapll_is_enabled,
  222. .recalc_rate = ti_fapll_recalc_rate,
  223. .get_parent = ti_fapll_get_parent,
  224. .round_rate = ti_fapll_round_rate,
  225. .set_rate = ti_fapll_set_rate,
  226. };
  227. static int ti_fapll_synth_enable(struct clk_hw *hw)
  228. {
  229. struct fapll_synth *synth = to_synth(hw);
  230. u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
  231. v &= ~(1 << synth->index);
  232. writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
  233. return 0;
  234. }
  235. static void ti_fapll_synth_disable(struct clk_hw *hw)
  236. {
  237. struct fapll_synth *synth = to_synth(hw);
  238. u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
  239. v |= 1 << synth->index;
  240. writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
  241. }
  242. static int ti_fapll_synth_is_enabled(struct clk_hw *hw)
  243. {
  244. struct fapll_synth *synth = to_synth(hw);
  245. u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET);
  246. return !(v & (1 << synth->index));
  247. }
  248. /*
  249. * See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info
  250. */
  251. static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw,
  252. unsigned long parent_rate)
  253. {
  254. struct fapll_synth *synth = to_synth(hw);
  255. u32 synth_div_m;
  256. u64 rate;
  257. /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */
  258. if (!synth->div)
  259. return 32768;
  260. /*
  261. * PLL in bypass sets the synths in bypass mode too. The PLL rate
  262. * can be also be set to 27MHz, so we can't use parent_rate to
  263. * check for bypass mode.
  264. */
  265. if (ti_fapll_clock_is_bypass(synth->fd))
  266. return parent_rate;
  267. rate = parent_rate;
  268. /*
  269. * Synth frequency integer and fractional divider.
  270. * Note that the phase output K is 8, so the result needs
  271. * to be multiplied by SYNTH_PHASE_K.
  272. */
  273. if (synth->freq) {
  274. u32 v, synth_int_div, synth_frac_div, synth_div_freq;
  275. v = readl_relaxed(synth->freq);
  276. synth_int_div = (v >> 24) & 0xf;
  277. synth_frac_div = v & 0xffffff;
  278. synth_div_freq = (synth_int_div * 10000000) + synth_frac_div;
  279. rate *= 10000000;
  280. do_div(rate, synth_div_freq);
  281. rate *= SYNTH_PHASE_K;
  282. }
  283. /* Synth post-divider M */
  284. synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
  285. return DIV_ROUND_UP_ULL(rate, synth_div_m);
  286. }
  287. static unsigned long ti_fapll_synth_get_frac_rate(struct clk_hw *hw,
  288. unsigned long parent_rate)
  289. {
  290. struct fapll_synth *synth = to_synth(hw);
  291. unsigned long current_rate, frac_rate;
  292. u32 post_div_m;
  293. current_rate = ti_fapll_synth_recalc_rate(hw, parent_rate);
  294. post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M;
  295. frac_rate = current_rate * post_div_m;
  296. return frac_rate;
  297. }
  298. static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth,
  299. unsigned long rate,
  300. unsigned long parent_rate)
  301. {
  302. u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v;
  303. post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate);
  304. post_div_m = post_div_m / SYNTH_MAX_INT_DIV;
  305. if (post_div_m > SYNTH_MAX_DIV_M)
  306. return -EINVAL;
  307. if (!post_div_m)
  308. post_div_m = 1;
  309. for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) {
  310. synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate *
  311. SYNTH_PHASE_K *
  312. 10000000,
  313. rate * post_div_m);
  314. synth_frac_div = synth_int_div % 10000000;
  315. synth_int_div /= 10000000;
  316. if (synth_int_div <= SYNTH_MAX_INT_DIV)
  317. break;
  318. }
  319. if (synth_int_div > SYNTH_MAX_INT_DIV)
  320. return -EINVAL;
  321. v = readl_relaxed(synth->freq);
  322. v &= ~0x1fffffff;
  323. v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24;
  324. v |= (synth_frac_div & 0xffffff);
  325. v |= SYNTH_LDFREQ;
  326. writel_relaxed(v, synth->freq);
  327. return post_div_m;
  328. }
  329. static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rate,
  330. unsigned long *parent_rate)
  331. {
  332. struct fapll_synth *synth = to_synth(hw);
  333. struct fapll_data *fd = synth->fd;
  334. unsigned long r;
  335. if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
  336. return -EINVAL;
  337. /* Only post divider m available with no fractional divider? */
  338. if (!synth->freq) {
  339. unsigned long frac_rate;
  340. u32 synth_post_div_m;
  341. frac_rate = ti_fapll_synth_get_frac_rate(hw, *parent_rate);
  342. synth_post_div_m = DIV_ROUND_UP(frac_rate, rate);
  343. r = DIV_ROUND_UP(frac_rate, synth_post_div_m);
  344. goto out;
  345. }
  346. r = *parent_rate * SYNTH_PHASE_K;
  347. if (rate > r)
  348. goto out;
  349. r = DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M);
  350. if (rate < r)
  351. goto out;
  352. r = rate;
  353. out:
  354. return r;
  355. }
  356. static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate,
  357. unsigned long parent_rate)
  358. {
  359. struct fapll_synth *synth = to_synth(hw);
  360. struct fapll_data *fd = synth->fd;
  361. unsigned long frac_rate, post_rate = 0;
  362. u32 post_div_m = 0, v;
  363. if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate)
  364. return -EINVAL;
  365. /* Produce the rate with just post divider M? */
  366. frac_rate = ti_fapll_synth_get_frac_rate(hw, parent_rate);
  367. if (frac_rate < rate) {
  368. if (!synth->freq)
  369. return -EINVAL;
  370. } else {
  371. post_div_m = DIV_ROUND_UP(frac_rate, rate);
  372. if (post_div_m && (post_div_m <= SYNTH_MAX_DIV_M))
  373. post_rate = DIV_ROUND_UP(frac_rate, post_div_m);
  374. if (!synth->freq && !post_rate)
  375. return -EINVAL;
  376. }
  377. /* Need to recalculate the fractional divider? */
  378. if ((post_rate != rate) && synth->freq)
  379. post_div_m = ti_fapll_synth_set_frac_rate(synth,
  380. rate,
  381. parent_rate);
  382. v = readl_relaxed(synth->div);
  383. v &= ~SYNTH_MAX_DIV_M;
  384. v |= post_div_m;
  385. v |= SYNTH_LDMDIV1;
  386. writel_relaxed(v, synth->div);
  387. return 0;
  388. }
  389. static const struct clk_ops ti_fapll_synt_ops = {
  390. .enable = ti_fapll_synth_enable,
  391. .disable = ti_fapll_synth_disable,
  392. .is_enabled = ti_fapll_synth_is_enabled,
  393. .recalc_rate = ti_fapll_synth_recalc_rate,
  394. .round_rate = ti_fapll_synth_round_rate,
  395. .set_rate = ti_fapll_synth_set_rate,
  396. };
  397. static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd,
  398. void __iomem *freq,
  399. void __iomem *div,
  400. int index,
  401. const char *name,
  402. const char *parent,
  403. struct clk *pll_clk)
  404. {
  405. struct clk_init_data *init;
  406. struct fapll_synth *synth;
  407. struct clk *clk = ERR_PTR(-ENOMEM);
  408. init = kzalloc(sizeof(*init), GFP_KERNEL);
  409. if (!init)
  410. return ERR_PTR(-ENOMEM);
  411. init->ops = &ti_fapll_synt_ops;
  412. init->name = name;
  413. init->parent_names = &parent;
  414. init->num_parents = 1;
  415. synth = kzalloc(sizeof(*synth), GFP_KERNEL);
  416. if (!synth)
  417. goto free;
  418. synth->fd = fd;
  419. synth->index = index;
  420. synth->freq = freq;
  421. synth->div = div;
  422. synth->name = name;
  423. synth->hw.init = init;
  424. synth->clk_pll = pll_clk;
  425. clk = clk_register(NULL, &synth->hw);
  426. if (IS_ERR(clk)) {
  427. pr_err("failed to register clock\n");
  428. goto free;
  429. }
  430. return clk;
  431. free:
  432. kfree(synth);
  433. kfree(init);
  434. return clk;
  435. }
  436. static void __init ti_fapll_setup(struct device_node *node)
  437. {
  438. struct fapll_data *fd;
  439. struct clk_init_data *init = NULL;
  440. const char *parent_name[2];
  441. struct clk *pll_clk;
  442. int i;
  443. fd = kzalloc(sizeof(*fd), GFP_KERNEL);
  444. if (!fd)
  445. return;
  446. fd->outputs.clks = kzalloc(sizeof(struct clk *) *
  447. MAX_FAPLL_OUTPUTS + 1,
  448. GFP_KERNEL);
  449. if (!fd->outputs.clks)
  450. goto free;
  451. init = kzalloc(sizeof(*init), GFP_KERNEL);
  452. if (!init)
  453. goto free;
  454. init->ops = &ti_fapll_ops;
  455. init->name = node->name;
  456. init->num_parents = of_clk_get_parent_count(node);
  457. if (init->num_parents != 2) {
  458. pr_err("%pOFn must have two parents\n", node);
  459. goto free;
  460. }
  461. of_clk_parent_fill(node, parent_name, 2);
  462. init->parent_names = parent_name;
  463. fd->clk_ref = of_clk_get(node, 0);
  464. if (IS_ERR(fd->clk_ref)) {
  465. pr_err("%pOFn could not get clk_ref\n", node);
  466. goto free;
  467. }
  468. fd->clk_bypass = of_clk_get(node, 1);
  469. if (IS_ERR(fd->clk_bypass)) {
  470. pr_err("%pOFn could not get clk_bypass\n", node);
  471. goto free;
  472. }
  473. fd->base = of_iomap(node, 0);
  474. if (!fd->base) {
  475. pr_err("%pOFn could not get IO base\n", node);
  476. goto free;
  477. }
  478. if (fapll_is_ddr_pll(fd->base))
  479. fd->bypass_bit_inverted = true;
  480. fd->name = node->name;
  481. fd->hw.init = init;
  482. /* Register the parent PLL */
  483. pll_clk = clk_register(NULL, &fd->hw);
  484. if (IS_ERR(pll_clk))
  485. goto unmap;
  486. fd->outputs.clks[0] = pll_clk;
  487. fd->outputs.clk_num++;
  488. /*
  489. * Set up the child synthesizers starting at index 1 as the
  490. * PLL output is at index 0. We need to check the clock-indices
  491. * for numbering in case there are holes in the synth mapping,
  492. * and then probe the synth register to see if it has a FREQ
  493. * register available.
  494. */
  495. for (i = 0; i < MAX_FAPLL_OUTPUTS; i++) {
  496. const char *output_name;
  497. void __iomem *freq, *div;
  498. struct clk *synth_clk;
  499. int output_instance;
  500. u32 v;
  501. if (of_property_read_string_index(node, "clock-output-names",
  502. i, &output_name))
  503. continue;
  504. if (of_property_read_u32_index(node, "clock-indices", i,
  505. &output_instance))
  506. output_instance = i;
  507. freq = fd->base + (output_instance * 8);
  508. div = freq + 4;
  509. /* Check for hardwired audio_pll_clk1 */
  510. if (is_audio_pll_clk1(freq)) {
  511. freq = NULL;
  512. div = NULL;
  513. } else {
  514. /* Does the synthesizer have a FREQ register? */
  515. v = readl_relaxed(freq);
  516. if (!v)
  517. freq = NULL;
  518. }
  519. synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance,
  520. output_name, node->name,
  521. pll_clk);
  522. if (IS_ERR(synth_clk))
  523. continue;
  524. fd->outputs.clks[output_instance] = synth_clk;
  525. fd->outputs.clk_num++;
  526. clk_register_clkdev(synth_clk, output_name, NULL);
  527. }
  528. /* Register the child synthesizers as the FAPLL outputs */
  529. of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs);
  530. /* Add clock alias for the outputs */
  531. kfree(init);
  532. return;
  533. unmap:
  534. iounmap(fd->base);
  535. free:
  536. if (fd->clk_bypass)
  537. clk_put(fd->clk_bypass);
  538. if (fd->clk_ref)
  539. clk_put(fd->clk_ref);
  540. kfree(fd->outputs.clks);
  541. kfree(fd);
  542. kfree(init);
  543. }
  544. CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup);